EDA技术的概念第12章

EDA 技术实用教程第 12 章 系统仿真

12.1 仿真仿真也称模拟(Simulation) 是对电路设计的一种间接的检测方法，是利用计算机对整 个硬件系统进行模拟检测，但却可以不接触具体的硬件系 统。

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12.2 VHDL源程序仿真VHDL文本 VHDL图形 输入 翻译成文本

VHDL编译

设计库

设计库管理

VHDL仿真

仿真结果 (数据和波形)

图12-1

VHDL仿真流程

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12.2 VHDL源程序仿真【例12-1】 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY and1 IS PORT(aaa,bbb : IN STD_LOGIC; ccc: OUT STD_LOGIC); END and1; ARCHITECTURE one OF and1 IS BEGIN ccc <= aaa AND bbb; END;

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12.2 VHDL源程序仿真【例12-2】 LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY TRIBUF_and1 IS GENERIC ( ttri: TIME := 1 ns; ttxz: TIME := 1 ns; ttzx: TIME := 1 ns); PORT ( in1 : IN std_logic; oe : IN std_logic; y : OUT std_logic); END TRIBUF_and1; ARCHITECTURE behavior OF TRIBUF_and1 IS BEGIN PROCESS (in1, oe) BEGIN IF oe‘EVENT THEN

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IF oe = '0' THEN y <= TRANSPORT 'Z' AFTER ttxz; ELSIF oe = '1' THEN y <= TRANSPORT in1 AFTER ttzx; END IF; ELSIF oe = '1' THEN y <= TRANSPORT in1 AFTER ttri; ELSIF oe = '0' THEN y <= TRANSPORT 'Z' AFTER ttxz; END IF; END PROCESS; END behavior; LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE work.tribuf_and1; ENTITY and1 IS PORT ( aaa : IN std_logic; bbb : IN std_logic; ccc : OUT std_logic); END and1; ARCHITECTURE EPF10K10LC84_a3 OF and1 IS . . . . . . END EPF10K10LC84_a3;

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12.3 仿真激励信号的产生第一种方法 ：

【例12-3】 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY ADDER4 IS PORT ( a, b : IN INTEGER RANGE 0 TO 15; c : OUT INTEGER RANGE 0 TO 15 ); END ADDER4; ARCHITECTURE one OF ADDER4 IS BEGIN c <= a + b; END one;康芯科技

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12.3 仿真激励信号的产生【例12-4】 ENTITY SIGGEN IS PORT ( sig1 : OUT INTEGER RANGE 0 TO 15; sig2 : OUT INTEGER RANGE 0 TO 15 ); END; ARCHITECTURE Sim OF SIGGEN IS BEGIN sig1 <= 10, 5 AFTER 200 ns, 8 AFTER 400 ns; sig2 <= 3, 4 AFTER 100 ns, 6 AFTER 300 ns; END;

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12.3 仿真激励信号的产生

图12-2 SIGGEN的仿真输出波形

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12.3 仿真激励信号的产生【例12-5】 ENTITY BENCH IS END; ARCHITECTURE one OF BENCH IS COMPONENT ADDER4 PORT ( a, b : integer range 0 to 15; c : OUT INTEGER RANGE 0 TO 15 ); END COMPONENT; COMPONENT SIGGEN PORT ( sig1 : OUT INTEGER RANGE 0 TO 15; sig2 : OUT INTEGER RANGE 0 TO 15 ); END COMPONENT; SIGNAL a, b, c : INTEGER RANGE 0 TO 15; BEGIN U1 : ADDER4 PORT MAP (a, b, c); U2 : SIGGEN PORT MAP (sig1=>a, sig2=>b); 康芯科技 KX END;

12.3 仿真激励信号的产生

图12-3 BENCH仿真波形图

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12.3 仿真激励信号的产生第二种方法 ：force <信号名> <值> [<时间>][, <值> <时间> …] [-repeat <周期>] force a 0 force b 0 0, 1 10 (强制信号的当前值为0) (强

制信号b在时刻0的值为0,在时刻10的值为1)

force clk 0 0, 1 15 –repeat 20 (clk为周期信号，周期为20 force a 10 0, 5 200, 8 400 force b 3 0, 4 100, 6 300

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12.4 VHDL测试基准【例12-6】 Library IEEE; use IEEE.std_logic_1164.all; entity counter8 is port ( CLK,CE,LOAD,DIR,RESET: in STD_LOGIC; DIN: in INTEGER range 0 to 255; COUNT: out INTEGER range 0 to 255 ); end counter8; architecture counter8_arch of counter8 is begin process (CLK, RESET) variable COUNTER: INTEGER range 0 to 255; begin if RESET='1' then COUNTER := 0; elsif CLK='1' and CLK'event then if LOAD='1' then COUNTER := DIN; (接下页) 康芯科技

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Else if CE='1' then if DIR='1' then if COUNTER =255 then Else COUNTER := end if; else if COUNTER =0 then Else COUNTER := end if; end if; end if; end if; end if; COUNT <= COUNTER; end process; end counter8_arch;

COUNTER := 0; COUNTER + 1;

COUNTER := 255; COUNTER - 1;

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12.4 VHDL测试基准【例12-7】 Entity testbench is end testbench; Architecture testbench_arch of testbench is File RESULTS: TEXT open WRITE_MODE is "results.txt"; Component counter8 port ( CLK: in STD_LOGIC; RESET: in STD_LOGIC; CE, LOAD, DIR: in STD_LOGIC; DIN: in INTEGER range 0 to 255; COUNT: out INTEGER range 0 to 255 ); end component; shared variable end_sim : BOOLEAN := false; signal CLK, RESET, CE, LOAD, DIR: STD_LOGIC; signal DIN: INTEGER range 0 to 255; signal COUNT: INTEGER range 0 to 255; procedure WRITE_RESULTS ( CLK,CE,LOAD,LOAD,RESET : STD_LOGIC; 康芯科技 (接下页) KX

DIN,COUNT : INTEGER ) is Variable V_OUT : LINE; Begin write(V_OUT, now, right, 16, ps); write(V_OUT, CLK, right, 2); write(V_OUT, RESET, right, 2); write(V_OUT, CE, right, 2); write(V_OUT, LOAD, right, 2); write(V_OUT, DIR, right, 2); write(V_OUT, DIN, right, 257); --write outputs write(V_OUT, COUNT, right, 257); writeline(RESULTS,V_OUT); end WRITE_RESULTS; begin UUT: COUNTER8 port map (CLK => CLK,RESET => RESET, CE => CE, LOAD => LOAD, DIR => DIR, DIN => DIN, COUNT => COUNT ); CLK_IN: process Begin

-- 输入时间

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if end_sim = false then CLK <= '0'; Wait for 15 ns; CLk <='1'; Wait for 15 ns; Else Wait; end if; end process; STIMULUS: process Begin RESET <= '1'; CE <= '1'; -- 计数使能 DIR <= '1'; -- 加法计数 DIN <= 250; -- 输入数据 LOAD <= '0'; -- 禁止加载输入的数据 wait for 15 ns; RESET <= '0'; wait for 1 us; CE <= '0'; -- 禁止计数脉冲信号进入 wait for 200 ns; CE <= '1'; wait for 200 ns; (接下页) 康芯科技

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DIR

<= '0'; wait for 500 ns; LOAD <= '1'; wait for 60 ns; LOAD <= '0'; wait for 500 ns; DIN <= 60; DIR <= '1'; LOAD <= '1'; wait for 60 ns; LOAD <= '0'; wait for 1 us; CE <= '0'; wait for 500 ns; CE <= '1'; wait for 500 ns; end_sim :=true; wait; end process; WRITE_TO_FILE: WRITE_RESULTS(CLK,RESET,CE,LOAD,DIR,DIN,COUNT); End testbench_arch;

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12.4 VHDL测试基准

图12-4 8位计数器

测试基准仿真部分波形图

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12.5 VHDL系统级仿真

12.5 VHDL系统级仿真

89C51 VHDL模型

专用集成电路 VHDL描述

图12-5 VHDL系统仿真模型示意图

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12.6 使用ModelSim进行仿真【例12-8】 LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY cnt4 IS 12.5 VHDL系统级仿真 PORT ( rst : IN STD_LOGIC; d : IN STD_LOGIC_VECTOR(3 downto 0); load : IN STD_LOGIC; clk,ce : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR(3 downto 0); cout : OUT STD_LOGIC ); END cnt4; ARCHITECTURE syn OF cnt4 IS signal count : std_logic_vector(3 downto 0); 康芯科技 KX BEGIN (接下页)

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