CFP MSA Management Interface Specification Draft 1_4_R5

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CFP MSA Management Interface Specification

June 22, 2010

Version 1.4 _______________________________________________________________________

11 CFP MSA Management Interface 12 Specification 13

100/40 Gigabit Transceiver Package Multi-Source Agreement 15

Version 1.4 19

June 22, 2010

CFP MSA Management Interface Specification

June 22, 2010

Version 1.4 _______________________________________________________________________

CFP MSA Group Contacts 2 3

Technical Editor Jiashu Chen jiashu.chen@d71e75c08bd63186bcebbce4

4 Finisar Corp. Chris Cole chris.cole@d71e75c08bd63186bcebbce4

Avago Technologies, Ltd. John Petrilla John.petrilla@d71e75c08bd63186bcebbce4 Opnext Inc. Matt Traverso mtraverso@d71e75c08bd63186bcebbce4 Sumitomo Electric Industries, Ltd. Eddie Tsumura tsumura-eiji@sei.co.jp 5

CFP MSA Management Interface Specification

June 22, 2010

Version 1.4 _______________________________________________________________________

REVISION HISTORY ........................................................................................................... 7 2

REFERENCES ..................................................................................................................... 8 3

LIST OF FIGURES ............................................................................................................... 9 4

LIST OF TABLES .............................................................................................................. 10 5

1 DOCUMENT SUMMARY ............................................................................................ 11 6

1.1 B ACKGROUND ........................................................................................................................................ 11 7 1.2 CFP M ANAGEMENT I NTERFACE ............................................................................................................... 11 8 1.3 C ONTENT OF THIS DOCUMENT ................................................................................................................. 11 9 1.4 N OTATIONS ............................................................................................................................................ 11 10 1.4.1 Hardware Signal Name ............................................................................................................... 11 11 1.4.2 Soft (MDIO) Signal Name ............................................................................................................ 11 12 1.4.3 CFP Register Name and Address ............................................................................................... 12 13 1.4.4 Numbers ...................................................................................................................................... 12 14 1.4.5 Special Characters ...................................................................................................................... 12 15 1.5 G LOSSARY ............................................................................................................................................. 12 16

2 CFP MANAGEMENT INTERFACE ............................................................................ 14 17

2.1 O VERVIEW ............................................................................................................................................. 14 18 2.2 S PECIFICATIONS ..................................................................................................................................... 14 19 2.2.1 Optional Features ........................................................................................................................ 14 20 2.2.1.1 Optional Controls .................................................................................................................................... 15 21 2.2.1.2 Optional FAWS signals ........................................................................................................................... 15 22 2.3 I NTERFACE A RCHITECTURE ..................................................................................................................... 15 23 2.4 MDIO M ANAGEMENT F RAME S TRUCTURE ............................................................................................... 16 24

3 CFP REGISTER OVERVIEW ..................................................................................... 17 25

3.1 CFP R EGISTER S PACE ........................................................................................................................... 17 26 3.2 N ON -VOLATILE R EGISTERS (NVR S ) ........................................................................................................ 17 27 3.2.1 CFP NVR Tables ......................................................................................................................... 17 28 3.2.2 Vendor NVR Tables .................................................................................................................... 17 29 3.2.3 User NVR Tables ........................................................................................................................ 17 30 3.2.4 NVR Content Management ......................................................................................................... 17 31 3.2.5 User Private Use Registers ......................................................................................................... 18 32 3.3 V OLATILE R EGISTERS (VR S ) ................................................................................................................... 19 33 3.3.1 CFP Module NV 1 Table ............................................................................................................. 19 34 3.3.2 Network Lane Specific Register Table ........................................................................................ 19 35 3.3.3 Host Lane Specific Register Table .............................................................................................. 19 36 3.4 M ODULE V ENDOR P RIVATE R EGISTERS ................................................................................................... 19 37 3.5 R ESERVED CFP R EGISTERS ................................................................................................................... 19 38 3.5.1 Un-implemented Registers .......................................................................................................... 19 39 3.6 CFP R EGISTER D ATA T YPES .................................................................................................................. 20 40 3.6.1 Byte ............................................................................................................................................. 20 41 3.6.2 Word ............................................................................................................................................ 20 42 3.6.3 Bit Field ........................................................................................................................................ 20 43 3.6.4 Two’s Complement ...................................................................................................................... 20 44

CFP CONTROL AND SIGNALING THEORY (21)

CFP MSA Management Interface Specification

June 22, 2010

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Copyright ? 2008-2010 CFP MSA Page 4 of 90 4.1 CFP M ODULE S TATES AND R ELATED S IGNALS ........................................................................................ 21 1 4.1.1 Signals Affecting Transition of CFP Module States .................................................................... 21 2 4.1.1.1 Combined Module Reset Signal MOD_RSTs ......................................................................................... 21 3 4.1.1.2 Combined Module Low Power Signal MOD_LOPWRs ........................................................................... 21 4 4.1.1.3 Combined Transmitter Disable Signal TX_DISs ..................................................................................... 22 5 4.1.1.4 Fault Conditions ...................................................................................................................................... 22 6 4.1.1.5 Minimum Signal Duration ....................................................................................................................... 22 7 4.1.2 Signals Affected by Module Insertion or State Transition ........................................................... 23 8 4.1.2.1 MOD_ABS .............................................................................................................................................. 23 9 4.1.2.2 GLB_ALRM ............................................................................................................................................ 23 10 4.1.2.3 INIT_DONE ............................................................................................................................................ 23 11 4.1.2.4 HIPWR_ON ............................................................................................................................................ 23 12 4.1.2.5 MOD_READY (Ready State) .................................................................................................................. 23 13 4.1.2.6 MOD_FAULT (Fault State) ..................................................................................................................... 23 14 4.1.3 CFP Module States ..................................................................................................................... 23 15 4.1.3.1 Reset State (Steady) .............................................................................................................................. 24 16 4.1.3.2 Initialize State (Transient) ....................................................................................................................... 24 17 4.1.3.3 Low-Power State (Steady) ...................................................................................................................... 24 18 4.1.3.4 High-Power-up State (Transient) ............................................................................................................ 25 19 4.1.3.5 TX-Off State (Steady) ............................................................................................................................. 25 20 4.1.3.6 TX-Turn-on State (Transient) .................................................................................................................. 25 21 4.1.3.7 Ready State (Steady) ............................................................................................................................. 26 22 4.1.3.8 TX-Turn-off State (Transient) .................................................................................................................. 26 23 4.1.3.9 High-Power-Down State (Transient) ....................................................................................................... 26 24 4.1.3.10 Fault State (Steady) ........................................................................................................................... 26 25 4.2 S TATE T RANSITION D IAGRAM .................................................................................................................. 27 26 4.3 E XAMPLES OF M ODULE S TARTUP AND T URN -OFF S EQUENCE ................................................................... 29 27 4.3.1 Power-up CFP Module to Ready State without Host Transition Control..................................... 29 28 4.3.2 Power-up the Module with Full Host Transition Control .............................................................. 30 29 4.3.3 Power-Up the Module with Some Host Transition Control .......................................................... 30 30 4.3.4 Example of Module Turn-off Sequence ....................................................................................... 30 31 4.4 S PECIAL M ODES OF O PERATION ............................................................................................................. 30 32 4.5 B EHAVIOR OF FAWS IN CFP S TATES ..................................................................................................... 36 33 4.6 G LOBAL A LARM S YSTEM L OGIC ............................................................................................................... 37 34 4.7 S PECIFIC H OST C ONTROLS OVER M ANAGEMENT I NTERFACE .................................................................... 41 35 4.7.1 Soft Module Reset (A010h.15) Function ..................................................................................... 41 36 4.7.2 Soft Global Alarm Test (A010h.9) Function ................................................................................ 41 37 4.8 T IMING FOR M ANAGEMENT I NTERFACE CONTROL AND STATUS REPORTING ................................................ 41 38 4.8.1 Miscellaneous Timing .................................................................................................................. 43 39 4.9 B IT E RROR R ATE C ALCULATION .............................................................................................................. 44 40 4.9.1 Network Lane PRBS Setup ......................................................................................................... 44 41 4.9.2 Network Lane BER Calculation ................................................................................................... 44 42 4.9.3 Host Lane PRBS Control ............................................................................................................. 45 43 4.9.4 Host Lane BER Calculation ......................................................................................................... 45 44 4.10 CFP R EGISTER A CCESS .................................................................................................................... 45 45 4.10.1 Read and Write Accesses ....................................................................................................... 45 46 4.10.2 User NVR Restore and Save Functions ................................................................................. 46 47 4.10.2.1 User NVR Restore and Save Command (Bit 5) ................................................................................. 46 48 4.10.2.2 Command Status (bits 3, 2) ............................................................................................................... 48 49 4.10.2.3 Extended Commands (bits 1, 0) ........................................................................................................ 48 50 4.10.2.4 NVR Data Safety in Save Function .................................................................................................... 48 51 4.11 S ETUP OF P ROGRAMMABLE C ONTROL AND A LARM P INS ...................................................................... 50 52 4.11.1 Programmable Control Functions for PRG_CNTLs ................................................................ 50 53 4.11.2 Programmable Alarm Sources for PRG_ALRMs .................................................................... 50 54

CFP REGISTER DESCRIPTION ................................................................................ 51 55

CFP MSA Management Interface Specification

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Version 1.4 _______________________________________________________________________

Copyright ? 2008-2010 CFP MSA Page 5 of 90 5.1 CFP NVR 1 T ABLE : B ASE ID R EGISTERS ................................................................................................ 51 1 5.1.1 Module Identifier (8000h) ............................................................................................................ 51 2 5.1.2 Extended Identifier (8001h) ......................................................................................................... 51 3 5.1.2.1 Power Class ........................................................................................................................................... 51 4 5.1.2.2 Lane Ratio Type ..................................................................................................................................... 52 5 5.1.2.3 WDM Type.............................................................................................................................................. 52 6 5.1.3 Connector Type Code (8002h) .................................................................................................... 52 7 5.1.4 Ethernet Application Code (8003h) ............................................................................................. 52 8 5.1.5 Fiber Channel Application Code (8004h) .................................................................................... 52 9 5.1.6 Copper Link Application Code (8005h) ....................................................................................... 52 10 5.1.7 SONET/SDH Application Code (8006h) ...................................................................................... 52 11 5.1.8 OTN Application Code (8007h) ................................................................................................... 53 12 5.1.9 Additional Capable Rates Supported (8008h) ............................................................................. 53 13 5.1.10 Number of Lanes Supported (8009h) ..................................................................................... 53 14 5.1.10.1 Number of Network Lanes ................................................................................................................. 53 15 5.1.10.2 Number of Host Lanes ....................................................................................................................... 53 16 5.1.11 Media Properties (800Ah) ....................................................................................................... 53 17 5.1.11.1 Media Type ........................................................................................................................................ 53 18 5.1.11.2 Directionality ...................................................................................................................................... 53 19 5.1.11.3 Optical Multiplexing and De-Multiplexing ........................................................................................... 53 20 5.1.11.4 Active Fiber per Connector ................................................................................................................ 54 21 5.1.12 Maximum Network Lane Bit Rate (800Bh) ............................................................................. 54 22 5.1.13 Maximum Host Lane Bit Rate (800Ch) ................................................................................... 54 23 5.1.14 Maximum Single Mode Optical Fiber Length (800Dh) ............................................................ 54 24 5.1.15 Maximum Multi-Mode Optical Fiber Length (800Eh) .............................................................. 54 25 5.1.16 Maximum Copper Cable Length (800Fh)................................................................................ 54 26 5.1.17 Transmitter Spectral Characteristics 1 (8010h) ...................................................................... 54 27 5.1.17.1 Number of Active Transmit Fibers ..................................................................................................... 54 28 5.1.18 Transmitter Spectral Characteristics 2 (8011h) ...................................................................... 55 29 5.1.18.1 Number of Wavelengths per Active Transmit Fiber ........................................................................... 55 30 5.1.19 Minimum Wavelength per Active Fiber (8012h, 8013h) .......................................................... 55 31 5.1.20 Maximum Wavelength per Active Fiber (8014h, 8015h) ......................................................... 55 32 5.1.21 Maximum per Lane Optical Width (8016h, 8017h) ................................................................. 55 33 5.1.22 Device Technology 1 (8018h) ................................................................................................. 55 34 5.1.22.1 Laser Source Technology .................................................................................................................. 55 35 5.1.22.2 Transmitter Modulation Technology ................................................................................................... 55 36 5.1.23 Device Technology 2 (8019h) ................................................................................................. 55 37 5.1.23.1 Wavelength Control ........................................................................................................................... 56 38 5.1.23.2 Cooled Transmitter ............................................................................................................................ 56 39 5.1.23.3 Tunability ........................................................................................................................................... 56 40 5.1.23.4 VOA Implemented ............................................................................................................................. 56 41 5.1.23.5 Detector Type .................................................................................................................................... 56 42 5.1.23.6 CDR with EDC ................................................................................................................................... 56 43 5.1.24 Signal Code (801Ah) ............................................................................................................... 56 44 5.1.24.1 Modulation ......................................................................................................................................... 56 45 5.1.24.2 Signal Coding .................................................................................................................................... 57 46 5.1.25 Maximum Total Optical Output Power per Connector (801Bh) .............................................. 57 47 5.1.26 Maximum Optical Input Power per Network Lane (801Ch) .................................................... 57 48 5.1.27 Maximum Power Consumption (801Dh) ................................................................................. 57 49 5.1.28 Maximum Power Consumption in Low Power Mode (801Eh) ................................................ 57 50 5.1.29 Maximum Operating Case Temp Range (801Fh) ................................................................... 57 51 5.1.30 Minimum Operating Case Temp Range (8020h) .................................................................... 57 52 5.1.31 Vendor Name (8021h) ............................................................................................................ 57 53 5.1.32 Vendor OUI (8031h) ................................................................................................................ 58 54 5.1.33 Vendor Part Number (8034h) .................................................................................................. 58 55 5.1.34 Vendor Serial Number (8044h) ............................................................................................... 58 56

CFP MSA Management Interface Specification

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Copyright ? 2008-2010 CFP MSA Page 6 of 90 5.1.35 Date Code (8054h) .................................................................................................................. 58 1 5.1.36 Lot Code (805Ch) .................................................................................................................... 58 2 5.1.37 CLEI Code (805Eh) ................................................................................................................. 59 3 5.1.38 CFP MSA Hardware Specification Revision Number (8068h) ................................................ 59 4 5.1.39 CFP MSA Management Interface Specification Revision Number (8069h) ........................... 59 5 5.1.40 Module Hardware Version Number (806Ah) ........................................................................... 59 6 5.1.41 Module Firmware Version Number (806Ch) ........................................................................... 59 7 5.1.42 Digital Diagnostic Monitoring Type (806Eh) ........................................................................... 59 8 5.1.43 Digital Diagnostic Monitoring Capability 1 (806Fh) ................................................................. 59 9 5.1.44 Digital Diagnostic Monitoring Capability 2 (8070h) ................................................................. 59 10 5.1.45 Module Enhanced Options (8071h) ........................................................................................ 60 11 5.1.46 Maximum High-Power-up Time (8072h) ................................................................................. 60 12 5.1.47 Maximum TX-Turn-on Time (8073h) ....................................................................................... 60 13 5.1.48 Host Lane Signal Spec (8074h) .............................................................................................. 60 14 5.1.49 Heat Sink Type (8075h) .......................................................................................................... 60 15 5.1.50 Maximum TX-Turn-off Time (8076h) ....................................................................................... 60 16 5.1.51 Maximum High-Power-down Time (8077h) ............................................................................ 60 17 5.1.52 Module Enhanced Options 2 (8078h) ..................................................................................... 61 18 5.1.53 Transmitter Monitor Clock Options (8079h) ............................................................................ 61 19 5.1.54 Receiver Monitor Clock Options (807Ah)................................................................................ 61 20 5.1.55 Module Enhanced Options 3 (807Bh) ..................................................................................... 61 21 5.1.56 CFP NVR 1 Checksum (807Fh) .............................................................................................. 61 22 5.2 CFP NVR 2 T ABLE : A LARM /W ARNING T HRESHOLD R EGISTERS ............................................................... 67 23 5.3 CFP NVR 3 T ABLE : N ETWORK L ANE BOL M EASUREMENT R EGISTERS .................................................... 69 24 5.4 CFP NVR 4 T ABLE ................................................................................................................................ 70 25 5.5 CFP M ODULE VR 1 T ABLE ..................................................................................................................... 70 26 5.5.1 CFP Command/Setup Registers ................................................................................................. 70 27 5.5.1.1 NVR Access Control (A004h) ................................................................................................................. 71 28 5.5.1.2 PRG_CNTLs Function Select (A005h, A006, A007h) ............................................................................. 71 29 5.5.1.3 PRG_ALRMs Source Select (A008h, A009h, A00Ah) ............................................................................ 71 30 5.5.1.4 Module Bi-/Uni- Directional Operating Mode Select (A00Bh) ................................................................. 71 31 5.5.2 Module Control Registers (A010h~A014h) ................................................................................. 71 32 5.5.3 Module State Register (A016h) ................................................................................................... 71 33 5.5.4 Module Alarm Summary Registers (A018h, A019h, A01Ah, A01Bh) ......................................... 71 34 5.5.5 Module FAWS Registers (A01Dh, A01Eh, A01Fh, A020h) ........................................................ 71 35 5.5.6 Module FAWS Latch Registers (A022h, A023h, A024h, A025h, A026h) ................................... 71 36 5.5.7 Module FAWS Enable Registers (A028h, A029h, A02Ah, A02Bh, A02Ch) ............................... 72 37 5.5.8 Module Analog A/D Value Registers (A02Fh, A030h, A031h, A032h, A033h) ........................... 72 38 5.5.9 Module PRBS Registers (A038h, A039h) ................................................................................... 72 39 5.6 N ETWORK L ANE S PECIFIC R EGISTER T ABLES .......................................................................................... 85 40 5.7 H OST L ANE S PECIFIC R EGISTER T ABLE ................................................................................................... 89 41

CFP MSA Management Interface Specification

June 22, 2010

Version 1.4 _______________________________________________________________________

1 Revision Date Objective

By External NDA Draft 0.1 12/23/2008 Initial release, work in progress

Jiashu Chen External NDA Draft 0.2 01/26/2009 2nd release for review

Jiashu Chen External NDA Draft 0.3 02/19/2009 3rd release for review

Jiashu Chen External NDA Draft 0.4E 04/03/2009 4th release for review

Jiashu Chen External NDA Draft 0.4F 04/07/2009 Error corrected version of 0.4E for review

Jiashu Chen Publication Draft 1.0 04/13/2009 First full draft for releasing to public.

Jiashu Chen External NDA Draft 1.1 6/22/2009 Pre Public release Draft 1.2

Jiashu Chen External NDA Draft 1.2 R1 8/31/2009 Pre Public release Draft 1.2

Jiashu Chen External NDA Draft 1.2 R2 9/14/2009 Pre Public release Draft 1.2

Jiashu Chen External NDA Draft 1.2 R2C 9/23/2009 Pre Public release Draft 1.2

Jiashu Chen External NDA Draft 1.2 R2D 9/29/2009 Pre Public release Draft 1.2

Jiashu Chen Publication Draft 1.2 9/30/2009 Second full draft for release to public

Jiashu Chen External NDA Draft 1.3R5 4/16/2010 Pre Public Release for Draft 1.4

Jiashu Chen External NDA Draft 1.3R6 5/20/2010 Pre Public Release for Draft 1.4

Jiashu Chen Publication Version 1.4 (r1) 6/4/2010 Pre Publication release

Jiashu Chen Publication Version 1.4 (r2) 6/4/2010 Pre Publication release

Jiashu Chen Publication Version 1.4 (r3) 6/15/2010 Pre Publication release for MSA Members

Jiashu Chen Publication Version 1.4 (r4) 6/21/2010 Pre Publication release

Jiashu Chen Publication Version 1.4 (r5) 6/22/2010 Publication release Jiashu Chen

CFP MSA Management Interface Specification

June 22, 2010

Version 1.4 _______________________________________________________________________

1. IEEE Standard 80

2.3-2008 2

2. IEEE Standard P802.3ba, Draft 2.0 3

3. INF-8074i, XENPAK MSA Issue 3.0 4

4. INF-8077i, XFP Specification Rev. 4.5 5

5. CFP MSA Hardware Specification Draft 1.4

CFP MSA Management Interface Specification

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Figure 1 CFP Management Interface Architecture .............................................................. 16 2

Figure 2 CFP MDIO Management Frame Structure ............................................................ 16 3

Figure 3 State Transition Diagram during Startup and Turn-off .......................................... 28 4

Figure 4 Module Startup Sequence Example 1: No Host Transition Control ...................... 31 5

Figure 5 Module Startup Sequence Example 2: Full Host Transition Control ..................... 32 6

Figure 6 Module Startup Sequence Example 3: Some Host Transition Control ................. 33 7

Figure 7 Module Turn-off Sequence Example: No Host Transition Control ........................ 34 8

Figure 8 Module Start-up Sequence Example: Operating in RX Only Mode ...................... 35 9

Figure 9 FAWS Signal Model for a Single Bit ...................................................................... 36 10

Figure 10 Global Alarm Signal Aggregation ......................................................................... 40 11

Figure 11 CFP Built-in PRBS Components and Test Signal Flow ...................................... 44 12

Figure 12 Restore and Save Command Execution State Diagram ..................................... 49 13

CFP MSA Management Interface Specification

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Table 1 Glossary .................................................................................................................. 12 2

Table 2 CFP Register Allocation .......................................................................................... 18 3

Table 3 Bit Pattern of a Two’s Complement Byte Data ....................................................... 20 4

Table 4 Behavior of Signals Affected by Module State Transition ....................................... 29 5

Table 5 Behavior of FAWS Type in Different Module States ............................................... 37 6

Table 6 Global Alarm Related Registers .............................................................................. 38 7

Table 7 Global Alarm Query Hierarchy ................................................................................ 39 8

Table 8 Timing for Management Interface Control and Status ............................................ 41 9

Table 9 Miscellaneous Timing .............................................................................................. 43 10

Table 10 CFP Ad-hoc Floating Point Number Examples ..................................................... 45 11

Table 11 User NVRs Access Control Register (A004h) ...................................................... 46 12

Table 12 Restore and Save Command State Definitions .................................................... 47 13

Table 13 Restore and Save Command State Transitions ................................................... 47 14

Table 14 Programmable Control Functions ......................................................................... 50 15

Table 15 Programmable Alarm Sources .............................................................................. 50 16

Table 16 Table Column Description ..................................................................................... 51 17

Table 17 Date Code Example .............................................................................................. 58 18

Table 18 CFP NVR 1 ............................................................................................................ 61 19

Table 19 CFP NVR 2 ............................................................................................................ 68 20

Table 20 CFP NVR 3 ............................................................................................................ 69 21

Table 21 CFP NVR 4 ............................................................................................................ 70 22

Table 22 CFP Module VR 1 ................................................................................................. 72 23

Table 23 Network Lane VR 1 ............................................................................................... 85 24

Table 24 Network Lane VR 2 ............................................................................................... 88 25

Table 25 Host Lane VR 1 ..................................................................................................... 89 26

CFP MSA Management Interface Specification

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Version 1.4 _______________________________________________________________________

1 DOCUMENT SUMMARY 1 1.1 Background 2

This technical document, CFP MSA Management Interface Specification, has been created 3

by the CFP MSA group as a basis for a technical agreement between CFP module users 4

and vendors, together with its companion document CFP MSA Hardware Specification . 5

This document is not a warranted document. Each CFP module supplier will have their 7

own datasheet. If the users wish to find a warranted document, they should consult the 8

datasheet of the chosen module vendor. 9

The CFP MSA group reserves the rights at any time to add, amend, or withdraw technical 11

data contained in this document. 12

1.2 CFP Management Interface 13 CFP MSA Hardware Specification specifies the use of Management Data Input/Output 14

(MDIO) as the management interface between a Host and a CFP module. While the 15

hardware specification defines the hardware aspects of the MDIO interface such as its 16

electrical characteristics and timing requirements, this document defines a set of MDIO 17

registers suitable for CFP module applications following MDIO interface definition in IEEE 18

802.3 Clause 45. 19

1.3 Content of this document 20

Section 1 is the summary of this document. Section 2 provides an overview of the CFP 21

management interface, including a sample block diagram, MDIO command frame, and the 22

CFP register set. Section 3 layouts the overview of the CFP register set. Section 4 23

presents detailed discussions of the Host/Module control and signaling theory. Finally 24

Section 5 gives a series of tables describing the details of all CFP registers. 25 1.4 Notations 26

1.4.1 Hardware Signal Name 27

Signals transmitted over CFP module connector pins are considered as hardware signals. 28

Hardware signals names are directly quoted from the CFP MSA Hardware Specification, 29

formed with all upper case letters and numbers with the exception of a lower case letter as 30

the post script for some cases. Examples are MOD_LOPWR and MOD_RSTn. 31

1.4.2 Soft (MDIO) Signal Name 32

Signals transmitted over CFP Management Interface are considered as “Soft” signals or 33

MDIO signals. They are represented by CFP Registers or register bits. Soft signals have 34

their names denoted by one or more words or acronyms connected with or without 35

underscores. If the name consists of multiple words each word shall have its first character

CFP MSA Management Interface Specification

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Copyright ? 2008-2010 CFP MSA Page 12 of 90 capitalized. Examples are Soft GLB_ALRM Test, Soft Module Reset, etc. Some Soft 1

signals used as the defaults for programmable hardware pins are denoted in the manner of 2

Hardware Signal names, such as GLB_ALRM, HIPWR_ON, and MOD_READY. 3

1.4.3 CFP Register Name and Address 4

The names of CFP registers are formed with one or more English words, with each word’s 5

first character capitalized and space in between. Each register address is a 16-bit hex 6

number. When a particular bit in a register is addressed its address is denoted by x.y 7

where the x is the register address and y is the bit address, a decimal number ranging from 8

0 to 15. When several bits in a register are addressed the address format is x.y~z, where y 9

and z are boundary bits. The sign “~” is used to represent all the bits in between. 10 1.4.4 Numbers 11

Hex numbers are post-fixed by a lower case letter “h”, for example, A000h. Binary 12

numbers are post-fixed by a lower case letter such as 11b and 1101b. Decimal numbers 13

have neither prefix nor postfix. With this notation, an example of bit 15 at register A001 14

(hex) has the format of A001h.15. 15

1.4.5 Special Characters 16

Whenever possible, the special characters are avoided. For example, the symbol of 17

micrometer is designated as “um” or micro-meter instead of “μm” to prevent format loss in 18

the editing process. 19 1.5 Glossary 20

The often used nomenclatures in this document are listed in the following glossary table for 21

reference. 22

23 Table 1 Glossary

24 Terminology Description

APD Avalanche Photodiode

BOL Beginning Of Life

IEEE 802.3 IEEE Standard 802.3-2008

CFP MSA Specifications CFP MSA Specifications define a hot-pluggable optical transceiver form factor

to enable 40Gbps and 100Gbps applications, including next-generation High

Speed Ethernet (40GbE and 100GbE).

CFP MSA Specifications consist of two major documents: CFP MSA Hardware

Specification and CFP MSA Management Interface Specification (this

document).

CFP module A transceiver compliant to CFP MSA. The term “module” refers to CFP module

unless otherwise specified.

CFP register(s) A CFP register collects certain related management information in a basic form

of a 16-bit word, occupying one MDIO register address. The term “register”

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refers to CFP register unless otherwise specified.

CMU Clock Multiplier Circuit.

Control It refers to the Host control functions to the module over Management Interface.

It also includes the support of programmable control pin logic.

DDM Digital Diagnostic Monitoring. It includes CFP module functions of A/D value

reporting, FAWS logic, and programmable alarm pin logic.

FAWS Fault, Alarm, Warning, and Status.

GLB_ALRM It is a CFP module internally generated signal that drives GLB_ALRMn pin. GLB_ALRMn Global alarm hardware signal pin defined in CFP MSA Hardware Specification. HIPWR_ON High power mode of module operation.

Host It is equivalent to Station Management Entity (STA) of IEEE 802.3. It sources

MDC (MDIO Clock).

Host Lane It refers to high speed data lane between a Host and a CFP module. HW_Interlock It is a logic signal CFP module generates internally based on Hardware

Interlock [Reference 5]. It is defined as follows:

1 if CFP module power dissipation/consumption is greater than the Host

cooling capacity

0 if CFP module power dissipation/consumption is equal or less than the Host

cooling capacity or if Hardware Interlock is not used.

MOD_LOPWR Hardware signal driving CFP module into Low-Power State. Reference CFP

MSA Hardware Specification Rev. 1.4 for details.

MOD_LOPWRs Combined Module Low Power Signal. Refer to Section 4.1.1.2.

MOD_RSTn Hardware signal driving CFP module into Reset State. Reference CFP MSA

Hardware Specification Rev. 1.4 for details.

MOD_RSTs Combined Module Reset Signal. Refer to Section 4.1.1.1.

Network Lane It refers to data lane between CFP module and network, say, optical network. NVM Non-Volatile Memory

NVR Non-Volatile Register

PMD Physical Medium Dependent

Signal Information represented by hardware pins or CFP register bits and/or

transmitted over the management interface or hardware connector.

SOA Solid-State Optical Amplifier

TX_DIS Refer to [Reference 5] for description.

TX_DISs Combined Transmitter Disable Signal. Refer to Section 4.1.1.3.

User The customer of CFP module.

Vendor The manufacturer of CFP module.

VR Volatile Register

CFP MSA Management Interface Specification

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CFP Management Interface is the main communication interface between a Host and a 3

CFP module. Host uses this interface to control and monitor the startup, shutdown, and 4

normal operation of the CFP modules it manages. This interface operates over a set of 5

hardware pins through the CFP module connector and a set of software based protocols. 6

The primary protocol of CFP Management Interface is specified using MDIO bus structure 8

following the general specification of IEEE 802.3 Clause 45 and on-going IEEE 802.3 9

40GbE and 100GbE standardization project. 10

From a hardware point of view, CFP Management Interface consists of following 8 12

hardware signals: 2 hardware signals of MDC and MDIO, 5 hardware signals of Port 13

Address, and 1 hardware signal GLB_ALRMn. MDC is the MDIO Clock line driven by the 14

Host and MDIO is the bi-directional data line driven by both the Host and module 15

depending upon the data directions. The CFP Management Interface uses these hardware 16

signals in the electrical connector to instantiate the MDIO interface, listed in Table 2.1 17

MDIO Interface Pins, in CFP MSA Hardware Specification . 18

From a software/protocol point of view, CFP Management Interface consists of the MDIO 20

management frame, a set of CFP registers, and a set of rules for host control, module 21

initialization, and signal exchange between these two. To avoid the conflict with IEEE 22

802.3, CFP register set does not use the addresses from 0000h to 7FFFh at the present 23

time. The CFP registers use the addresses from 8000h to FFFFh, totaling 32768 24

addresses. 25 2.2 Specifications 26

With compliance to IEEE 802.3 Clause 45, CFP MSA defines the following additional 27

specifications for CFP MDIO interface. 28

a) Support of MDC rate up to 4 MHz while maintaining the downward compatibility to 29

100 kHz. 30

b) Both read and write activities occurring on the rising edge of the MDC clock only. 31

c) Supports MDIO Device Address 1 only, among 32 available addresses. 32

2.2.1 Optional Features 33

This specification provides a number of optional features. Compliance with this 34

specification does not require the implementation of these optional features by the module 35

supplier. All such optional features shall be clearly identified as "Optional" in the 36

corresponding register and bit definitions as well as the related text. 37

CFP MSA Management Interface Specification

June 22, 2010

Version 1.4 _______________________________________________________________________

The module supplier shall explicitly indicate the presence (or absence) of each optional 2

control in the Module Enhanced Options registers in NVR register space. This allows the 3

host to dynamically determine feature availability on a module-by-module basis. 4

2.2.1.2 Optional FAWS signals 5

Optional FAWS register bits do not require identification in Module Enhanced Options 6

registers in NVR register space. 7

2.3 Interface Architecture 8

CFP MSA exemplifies a MDIO interface architecture illustrated in Figure 1 CFP 9 Management Interface Architecture . This architecture recommends a dedicated MDIO logic 10

block in the CFP module to handle the high rate MDIO data and a CFP register set that is 11

pided into two register groups, the Non-Volatile Registers (NVR) and the Volatile 12

Registers (VR). The NVRs are connected to a Non-Volatile Memory device for 13

ID/Configuration data storage. Over the internal bus system, the VRs are connected to a 14

device that executes the Host control commands and reports various Digital Diagnostic 15

Monitoring (DDM) data. Note in the rest of this documentation, independent of 16

implementation, CFP registers are also referred as NVRs or VRs. 17

In implementation, CFP registers shall use fast memory to shadow the NVM data and the 19

DDM data. The shadow registers decouple the Host-side timing requirements from module 20

vendor’s internal processing, timing, and hardware control circuit introduced latency. Then 21

this CFP shadow register set shall meet the following requirements: 22

a) It supports dual access from the Host and from module internal operations such as 24

NVM and DDM data transfers. 25

b) It supports continuous Host access (read and write) with fast access memory at 26

maximum MDC rate of 4 MHz. 27

c) It allows the uploading of NVM content into the CFP register shadow during module 28

initialization. The data saving from CFP register shadow to NVM shall also be 29

supported. 30

d) It supports the DDM data update periodically during the whole operation of the 31

module. The maximum data refresh period shall meet the 100 ms for single network 32

lane applications. If the number of lanes is greater than one, then the maximum 33

data refresh period shall be 50 * (N + 1) ms, where N = number of network lanes 34

supported in the application. 35

e) It supports the whole CFP register set including all NVRs and VRs. 36

f) Incomplete or otherwise corrupted MDIO bus transactions shall be purged from 37

memory and disregarded. 38

g) The port address shall be allowed to change in fly without a module reset. 39

CFP MSA Management Interface Specification June 22, 2010

Version 1.4

_______________________________________________________________________

Figure 1 CFP Management Interface Architecture

3 2.

4 MDIO Management Frame Structure

4 CFP MDIO interface uses the communication data frame structure defined in IEEE 802.3

5 Clause 45. Each frame can be either an address frame or a data frame. The total bit

6 length of each frame is 64, consisting of 32 bits preamble, and the frame command body.

7 The command body consists of 6 parts illustrated in Figure 2 CFP MDIO Management

8 Frame Structure . 9

10 Figure 2 CFP MDIO Management Frame Structure

PHYADR

DEVADD

16-bit ADDRESS/DATA

32-bit Preamble

ST = start bits (2 bits),

OP = operation code (2 bits),

PHYADR = physical port address (5 bits),

DEVADD = MDIO device address (or called device type, 5 bits),TA = turn around bits (2 bits),

16-bit ADDRESS/DATA is the payload.

CFP MSA Management Interface Specification

June 22, 2010

Version 1.4 _______________________________________________________________________

3.1 CFP Register Space 2

The total CFP register space (from 8000h to FFFFh) is logically pided into 8 pages with 3

each page starting at even hex thousand, that is, 8000h, 9000h, A000h, …, F000h. Each 4

page has 4096 addresses and is further pided into 32 tables. Each table has 128 CFP 5

The sole purpose of this logical segmentation is for the convenience of CFP register space 7

allocation and access control. The overview of the CFP register allocation is listed in Table 8 2 CFP Register Allocation . 9

3.2 Non-volatile Registers (NVRs) 10

CFP MSA specifies the starting address of all non-volatile registers at 8000h and it 11

specifies 8 NVR tables for storing module ID information, setup data, and additional data 12

stored by vendor and user. All NVR tables are implemented with lower 8-bit of space filled 13

with data and the upper 8-bit of space reserved. A fully populated table shall require a 14

maximum of 128 bytes of NVM to back up. 15

3.2.1 CFP NVR Tables 16

CFP MSA specifies CFP NVR 1 table for storing Basic ID data, CFP NVR 2 table for storing 17

Extended ID data, CFP NVR 3 table for storing Network Lane Specific data. CFP NVR 4 18

table is allocated for storing Host Lane Specific data. Currently only the checksum of CFP 19

NVR 3 is stored in CFP NVR 4 table. 20

3.2.2 Vendor NVR Tables 21

Vendor NVR 1 and Vendor NVR 2 tables are allocated for storing additional data that can 22

be used by the vendor. 23

3.2.3 User NVR Tables 24

The User NVR 1 and User NVR 2 tables are allocated for module user to store data. User 25

has the full read/write access to these tables. 26

3.2.4 NVR Content Management 27

All populated CFP NVR tables shall be backed up by physical non-volatile memory (NVM). 28

On module Initialize, CFP NVR tables shall be uploaded with stored NVM values. CFP 29

module vendor shall manage the content of CFP NVR tables. 30

The content and management of Vendor NVR tables and User NVR tables are subject to 32

additional agreement between user and vendor.

CFP MSA Management Interface Specification

June 22, 2010

Version 1.4 _______________________________________________________________________

Starting at 8F00h, two additional tables are allocated for “User private use”. CFP MSA 2

does not specify nor restricts the use of these tables. The use of these User Private Use 3

Registers is subject to additional agreement between CFP module users and vendors. 4

5 Table 2 CFP Register Allocation

6 CFP Register Allocation

Starting

Address

in Hex

Ending Address in Hex Access Type Allocated Size Data Bit Width Table Name and Description 0000

7FFF N/A 32768 N/A Reserved for IEEE 802.3 use. 8000

807F RO 128 8 CFP NVR 1. Basic ID registers. 8080

80FF RO 128 8 CFP NVR 2. Extended ID registers. 8100

817F RO 128 8 CFP NVR 3. Network lane specific registers. 8180

81FF RO 128 8 CFP NVR 4. 8200

83FF RO 4x128 N/A MSA Reserved. 8400

847F RO 128 8 Vendor NVR 1. Vendor data registers. 8480

84FF RO 128 8 Vendor NVR 2. Vendor data registers. 8500

87FF RO 6x128 N/A Reserved by CFP MSA. 8800

887F R/W 128 8 User NVR 1. User data registers. 8880

88FF R/W 128 8 User NVR 2. User data registers. 8900

8EFF RO 12x128 N/A Reserved by CFP MSA. 8F00

8FFF N/A 2x128 N/A Reserved for User private use. 9000

9FFF RO 4096 N/A Reserved for vendor private use. A000

A07F R/W 128 16 CFP Module VR 1. CFP Module level control and DDM registers. A080

A0FF RO 128 16 Reserved by CFP MSA. A100

A1FF RO 2x128 N/A Reserved by CFP MSA. A200

A27F R/W 128 16 Network Lane VR 1. Network lane specific registers. A280

A2FF R/W 128 16 Network Lane VR 2. Network lane specific registers. A300

A3FF RO 2x128 N/A Reserved by CFP MSA. A400

A47F R/W 128 16 Host Lane VR 1. Host lane specific registers. A480

AFFF RO 23x128 N/A Reserved by CFP MSA. B000 FFFF RO 5x4096 N/A Reserved by CFP MSA.

CFP MSA Management Interface Specification

June 22, 2010

Version 1.4 _______________________________________________________________________

Page A000h is allocated for volatile registers. CFP MSA specifies 4 VR tables for module 2

configuration, control, and various DDM related functions. All VR registers are 16-bit data 3

with unused bits reserved. A fully populated table requires a maximum of 256 bytes of 4

physical memory. There is no NVM backup for VR registers but CFP MSA specifies their 5

initial values. 6

3.3.1 CFP Module NV 1 Table 7

This table, starting at address A000h, contains command/setup, module control, lane 8

control, Module state, FAWS (fault/alarm/warning/status), FAWS Summary, and other DDM 9

related registers. All registers are assigned with initial values to insure the correct startup 10

condition. 11

3.3.2 Network Lane Specific Register Table 12

Two tables starting from A200h and ending at A2FFh are allocated to support network lane 13

specific registers including lane FAWS, controls, and A/D values (For copper network lanes 14

some of the DDM register support may not apply.). For each supported register, CFP MSA 15

allocates a 16-lane array for it. Should in the future more than 16 lanes are needed 16

additional tables can be allocated in the subsequent reserved addresses. 17

3.3.3 Host Lane Specific Register Table 18

One table starting at A400h is allocated to support host lane specific registers. For each 19

supported parameter, CFP MSA allocates a 16-lane array for it. Should in the future more 20

than 16 lanes are considered additional tables can be allocated in the subsequent reserved 21

addresses. 22

3.4 Module Vendor Private Registers 23

Page 9000h is reserved exclusively for module vendors of CFP module for their 24

development and implementation needs. 25

3.5 Reserved CFP Registers 26

All reserved CFP registers and all the reserved bits in a CFP register shall be “read-only” 27

and they shall be read as all-zeros. Writing to reserved CFP registers or bits shall have no 28

effect. CFP registers related to unused lanes for a specific module type shall be treated as 29

reserved CFP registers. An example would be CFP registers relating to network lanes 15:4 30

for a 100GBASE-LR4 module (in which only network lanes 3:0 are active). 31

3.5.1 Un-implemented Registers 32

A particular CFP module may not implement every function by this Specification. The 33

registers or bits in the registers representing the un-implemented functions shall be read as 34

0. Writing to these registers or register bits has no effect.

CFP MSA Management Interface Specification June 22, 2010

Version 1.4

_______________________________________________________________________

Page 20 of 90

3.6 CFP Register Data Types

1 A CFP register collects management information in a basic form of a 16-bit word,

2 occupying one MDIO register address. CFP Registers support the following data types.

3 3.6.1 Byte

4 A byte can represent a signed number, unsigned number, or an array of 8-bit value. If a

5 CFP register only contains one byte of data, it allocates the least significant 8 bits for it, with

6 all most significant 8 bits reserved. All the non-volatile registers contain a byte with bit

7 7 being the most significant bit.

8 3.6.2 Word

9 A word is a 16-bit-wide data type. It can represent a signed number, unsigned number, or 10 an array of 16-bit values. It can also be used as 2 bytes, the most significant byte and the 11 least significant byte. The most significant byte occupies the bits from 15 to 8. The least 12 significant byte occupies the bits from 7 to 0. All the volatile registers contain a word with 13 bit 15 being the most significant bit. 14 3.6.3 Bit Field

15 A CFP register can contain one or more bit fields. A bit field consists of one or more bits, 16 which can represent a number or an array of bit values. If a bit field represents a number 17 the bit with the highest bit number is the most significant bit. 18 3.6.4 Two’s Complement

19 Wherever signed byte is used, two’s complement is assumed. Table 3 illustrates the 20 example bit patterns and values of a signed byte in two’s complement form. For a 16-bit 21 signed word, the same format applies with the most significant bit (bit 15) to be the sign bit. 22 The value of +32767 = 7FFFh and the value of -32768 = 8000h. 23

24 Table 3 Bit Pattern of a Two’s Complement Byte Data

BIT 7 (SIGN BIT) BIT 6 BIT 5 BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

VALUE 0 1 1 1 1 1 1 1 = +127 0 0 0 0 0 0 0 1 = +1 0 0 0 0 0 0 0 0 = 0 1 1 1 1 1 1 1 1 = -1 1 0 0 0 0 0 0 1 = -127 1

0 0 0 0 0 0 0

-128

CFP MSA Management Interface Specification

June 22, 2010

Version 1.4 _______________________________________________________________________

4.1 CFP Module States and Related Signals 2

To facilitate a well-defined CFP module startup and module turn-off sequences and other 3

applications, CFP MSA specifies a list of CFP module states that CFP module shall 4

support. 5

In association with these states, a set of signals that are related to state transitions are also 7

defined. In the following text, a signal name with a lower-case "s" suffix stands for a 8

combination of multiple signals. 9

4.1.1 Signals Affecting Transition of CFP Module States 10

Three inputs and one internally generated signal are defined and each of them is a logical 11

combination of hardware signal status, CFP register bit status, and module internally 12

generated logic signals in some cases. These signals affect the state transition. 13

4.1.1.1 Combined Module Reset Signal MOD_RSTs 14

For reset operation, CFP module internally defines MOD_RSTs as follows: 15

MOD_RSTs = (NOT MOD_RSTn) OR (Soft Module Reset) OR Vcc_Reset, 16

where, 17

MOD_RSTn is the hardware pin input, 18

Soft Module Reset is a CFP register bit, de-asserted in Reset and, 19

Vcc_Reset is the CFP internally generated logic signal indicating the validity of Vcc 20

Vcc_Reset = 1 if Vcc at connector is lower than a specified threshold, 22

= 0 if Vcc is within range. 23

Note that Vcc_Reset does not correspond to the operating voltage range specified in 25

the CFP MSA Hardware specification. Vcc_Reset is the threshold voltage below 26

which the module is held in reset, and above which normal operation can be 27

initiated. 28

The threshold for Vcc_Reset is vendor specific and shall be lower than Vcc Low 30

Alarm Threshold (808Eh). 31

4.1.1.2 Combined Module Low Power Signal MOD_LOPWRs 32

MOD_LOPWRs = MOD_LOPWR OR (Soft Module Low Power) OR HW_Interlock, 34

where, 35

MOD_LOPWR is the hardware pin input, 36

Soft Module Low Power is the CFP register bit, de-asserted in Reset, HW_Interlock 37

is defined below.

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