MOSFET-Only Wideband LNA with Noise Cancelling and Gain Optimization(MOS Only NF lees 2)

全CMOS噪声抵消和增益优化的宽带LNA

MIXDES 2010, 17th International Conference "Mixed Design of Integrated Circuits and Systems", June 24-26, 2010, Wroc aw, Poland

MOSFET-Only Wideband LNA

with Noise Cancelling and Gain Optimization

Ivan Bastos, Luis B. Oliveira, João Goes

CTS-UNINOVA, Dep.º de Eng.ª Electrotécnica, Faculdade de Ciências e Tecnologia, FCT, Universidade Nova de Lisboa

Monte da Caparica, Portugal {iib14351, l.oliveira}@fct.unl.pt

Abstract—In this paper we present a MOFET-only implementation of a balun LNA. This LNA is based on the combination of a common-gate and a common-source stage with cancelling of the noise of the common-gate stage. In this circuit, we replace resistors by transistors, to reduce area and cost, and minimize the effect of process and supply variations and mismatches. In addition we obtain a higher gain for the same voltage drop. Thus, the LNA gain is optimized and the noise figure (NF) is reduced. We derive equations for the gain, input matching and NF. We compare the performance of this new topology with that of a conventional LNA with resistors. Simulation results with a 130 nm CMOS technology show that we obtain a balun LNA with a peak 19.8 dB gain (about 2 dB improvement), a spot NF lower than 1.9 dB (0.5 dB reduction). SThe total power consumption is only 4.8 mW for a wide bandwidth higher than 6 GHz.

Index Terms—CMOS LNAs, MOSFET-only circuits, Noise canceling, Wideband LNA.

Manuel Silva

INESC-ID Lisboa Tech. University of Lisbon

Lisbon, Portugal manuel.silva@inesc-id.pt

In this paper our main goal is to design a very low area and low-cost LNA, and at the same time obtain less circuit variability, by implementing the resistors using transistors (MOSFET-only design) [6]. As it will be shown, this approach adds a new degree of freedom, which can be used to maximize the LNA gain, and, therefore, minimize the circuit noise figure.

We start by reviewing the basic amplification stages, common-gate (CG) and common-source (CS). For each circuit we derive equations, with different levels of approximation, for the gain, input matching and noise figure. By comparing the results obtained with the different equations with those obtained by simulation, we select the level of approximation required for the frequency range in which we are interested. For the complete LNA (combined CG and CS balun topology), we compare the conventional design with resistors, and the new MOSFET-only implementation optimized for gain and noise figure. Simulation results of a circuit example designed in a standard 130 nm CMOS technology validate the proposed methodology.

This paper is organized as follows. In section II we derive the equations for the basic CG and CS stages. In section III we present simulation results for the conventional LNA with resistors, which confirm the theory. In Section IV we present the MOSFET-only LNA and we describe the optimization of gain and noise figure. We compare performance of this LNA with others in the literature. Finally, a discussion and some conclusions are given in Section V.

MON-GATE AND COMMON-SOURCE STAGES

Figs. 1 and 2 show, respectively, the CG and CS stages, normally employed in RC LNAs. We derive equations using three different levels of approximation: a) transistors’ complete model including the parasitic capacitances; b) low frequency approximation; c) low-frequency approximation neglecting the transistors’ output resistance.

mon-Gate Stage

In the equations below gm1 and gmb1 are the transistor’s transconductance and body effect transconductance, respectively, and ro1 is the transistor’s output resistance. The capacitance CS represents the source-bulk and source-gate

I.INTRODUCTION

Nowadays, the demand for mobile and portable equipment has led to a large increase in wireless communication applications. In order to achieve full integration and low cost, modern receiver architectures (Low-IF and zero-IF receivers), require inductorless circuits [1 - 4]. The LNA, which is a key block in the design of such receivers, is investigated in this paper.

LNAs can be either narrowband or wideband [1, 2]. Narrowband LNAs use inductors and have very low noise figure, but they occupy a large area and require a technology with RF options to have inductors with high Q. Wideband LNAs with multiple narrowband inputs have low noise, but their design is complicated and the area and cost are high [1, 2]. RC LNAs are very simple and inherently wideband, but conventional topologies have large noise figures. Recently, wideband LNAs with noise and distortion cancelling [5] have been proposed, which can have noise figures below 3 dB.

Inductorless circuits have reduced die area and cost [4]. However, they are usually realized with MiM capacitors, which require an additional insulator/metal layer, and they use poly or/and diffusion resistors, which have large process and mismatch variations (typically ±25%).

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全CMOS噪声抵消和增益优化的宽带LNA

capacitances and CRs is the signal source resistance and Lthe drain-bulk and drain-gate capacitance. R1 is the load resistance.

Figure 1. Common-Gate Stage.

1)Gain (1a)

(1b)

(1c)

2)Input Impedance

(2a)

where,

,

,

,

(2b)

(2c) 3)Noise Figure

(3)

where k is the Boltzmann constant ccapacitance, Woxis the oxide gate 1 and L1 are the transistor channel’s width and

length, respectively, T is the absolute temperature in Kelvin, γis the excess noise factor, kparameters, which depends on the size of the MOSFET f and αfare intrinsic process transistors [7, 8]. mon Source Stage

Figure 2. Common-Source Stage.

In the following equations gtransconductance and output impedance. The capacitances m2 and ro2 are the transistor’s ccgs2, cgd2, and db2 are the gate-source, gate-drain and drain-bulk capacitances, respectively. R2 is the load resistor. 1)Gain

(4a)

(4b)

(4c)

2)Input Impedance

(5)

3)Noise Figure

(6)

III.LNA

In the design of a wideband LNA there is an important choice to be made. A single-ended input simplifies the connection to the antenna and RF filters (they are usually single-ended) and avoids the need of a balun for the single to differential conversion (the balun usually has high loss and

degrades the NF significantly). A differential input leads to

全CMOS噪声抵消和增益优化的宽带LNA

reduced harmonic distortion and to better power supply and substrate noise rejection.

In this paper we study a single-ended input LNA (Fig. 3), which combines the balun and LNA functionalities in order to obtain a simple and low cost LNA (trying to get the best of the two above described approaches).

We obtain a low noise figure LNA (NF < 3 dB), since the thermal noise of M1 is cancelled out. The noise produced by M1appears in phase at the two outputs, while the signals are in opposition. Thus, we double the gain and cancel the noise. The gain matching of the two stages is critical: we need the same Assuming a infinite transistor’s output impedance we can simplify (11) into,

AvLNA_c = + (12)

To achieve noise cancellation and balun operation (converting a single-ended input to a differential output) the CG and CS’s stages gain should be equal. Considering ro1(gmb1+gm1) >> 1 and for the same current and length (L) on M1 and M2, their output impedance (ro) are approximately equal, and making (gm1+gmb1) = gm2 = gm and R1=R2=RD, we gain to maximize the circuit performance.

Figure 3. Balun LNA with noise canceling [9].

1)Input Impedance

The LNA input impedance is the parallel of those of the CG and CS stages,

(7)

if it is assumed that the CS input impedance is very high,

and if the low frequency approximation is considered (2b),

(9) 2)Gain

Since the output signal is differential, and vthe CG and CS outputs, the differential gain is given by out1 and vout2 are

(10)

and if the low frequencies approximation is used (1b and 4b),

(11)

jy3

obtain from (11),

3)Noise Figure

Assuming the same approach for noise cancellation, the simplified noise factor is given by,

(14) 4)Dimensions and Biasing

The LNA is designed for 50 input impedance using

equation (2c) as a first approximation and imposing the transconductance of M1. Mresistors values are about 200 1 is biased with 2 mA.. The load to give a DC level at output that avoid signal limitation and to keep Msaturation region. The DC voltage V1 and M2 in the Mbias is used to adjust the DC current of 2 to the same value as that of M1. The dimensions are shown on table I.

TABLE I. LNA PARAMETERS

D m bias GS (mA)

( )

(mS)

(µm)

(µm)

(mv)

(mV)

M1 M2

5)Simulation Results

To validate the equations obtained previously for the

LNA’s performance parameters, and to find out the required level of approximation, a comparison is made with the simulation results.

The real part of the input impedance (Figs. 4 and 5) remains almost constant up to 10 GHz, and the imaginary part starts to be significant above 1 GHz, so the input matching must be

designed carefully for wideband applications. Equation (9) can be used for this purpose.

We confirm by simulations that equations (9) and (11) are accurate for our design, as shown in Figs. 4-6.

全CMOS噪声抵消和增益优化的宽带LNA

Figure 4. LNA input impedance (real part).

Figure 5. LNA input impedance (imaginary part).

Figure 6. LNA Gain.

For the noise figure simulation we have considered kf = 4x10-23V2Hz and αf = 1.2 for the 130 nm technology [7, 8].

Figure 7. LNA noise figure.

IV.MOSFET-ONLY LNA

A.Initial Design

In the MOSFET-only LNA (Fig. 8) the load resistors are replaced by PMOS transistors (M3, M4) operating in the triode region, which are modeled ideally by a resistor between the drain and source ,

where gds is the channel conductance. To make a comparison with the LNA with load resistors, r . The biasing parameters are

ds is dimensioned to have the same resistance value of 200 on table II.

Figure 8. MOSFET-Only LNA

TABLE II. MOSFET PARAMETERS (INITIAL DESIGN)

D ds m bias GS (mA)

(

)

(mS)

(µm)

(µm)

(mv)

(mV)

M1 M2 M3 M4

全CMOS噪声抵消和增益优化的宽带LNA

B.Optimization Results

MOS transistor operating in triode region can be modeled C.Simulation Results

In figs. 11-13, we present the simulation results for our MOSFET-only design (initial and optimized) and we compare it with the traditional LNA with resistors.

by a resistor if gds / gm >> 10, otherwise the transistor should be modeled by a resistance in parallel with a current source. The saturation region is reached when ggm is of about the same magnitude as ds. This means that we can increase the incremental load resistance without increasing the DC voltage drop. This allows the gain to be increased with respect to the circuit with true resistors. By simulations we find the boundary between triode and saturation (Fig. 9) and we obtain the gains and noise figure as a function of gds (Fig. 10).

Saturation

Triode

Figure 9. Transistor gm VS gds.

Figure 10. LNA gain optimization project point.

By inspection of Fig. 10 we find that the better operation is before the single stages gain becomes unbalanced (gmS), which occurs before the load transistors reach the ds≈ 3.8 saturation. The circuit parameters are given on table III.

TABLE III. MOSFET PARAMETERS (OPTIMIZED)

D ds m bias

GS

(mA)

( )

(mS)

(µm)

(µm)

(mv)

(mV)

M1

M2 M3 M4

jRy

Figure 11. LNA input impedance.

Figure 12. LNA Gain.

Figure 13. LNA Noise Figure.

全CMOS噪声抵消和增益优化的宽带LNA

Comparing the results of our optimized MOSFET-only design with those for state-of-the-art inductorless LNAs (table IV), we can conclude it has the advantages of high gain and low noise figure; the drawbacks are a reduction of available bandwidth and the increase of the circuit non-linearity (reduction of IIP3).

TABLE IV. LNACOMPARISON

Band

(nm) (GHz)

Gain (dB)

NF (dB)

IIP3 (dBm)

Power (mW) Balun

ACKNOWLEDGMENT

This work was supported by the Portuguese Foundation for Science and Technology (CTS-UNINOVA and INESC-ID multiannual funding and project TARDE (PTDC/EEA-ELC/65710/2006)) through the PIDDAC Program funds.

REFERENCES

B. Razavi, RF Microelectronics, Prentice-Hall, 1998.

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V.DISCUSSION AND CS

ONCLUSIONS

In this paper we have presented a MOSFET-only

implementation of an LNA based on the combination of a common-gate and a common-source stage. We have derived simple equations for gain, input matching and noise figure, which are validated through simulation for our range of frequencies.

In MOSFET-only LNAs the replacement of resistors by transistors, reduces the area and cost, and minimizes the effect of process and supply variation and of mismatch [6]. Moreover, the LNA gain can be controlled by changing the bias of the PMOS transistors used to replace the resistors (this is still under investigation).

This new approach adds a new degree of freedom, which can be used to optimize the LNA gain and minimize the noise figure: we can obtain a higher gain than using resistors for the same DC voltage drop. As a drawback this approach increases the distortion, which can be seen by the decrease of the IIP3 value.

Simulation results of a circuit implemented in a 130 nm CMOS technology are presented. For comparison, we also show the performance of a conventional LNA with resistors. Both circuits have the same power consumption of 4.8 mW. For the MOSFET-only LNA we obtain a gain improvement of 2 dB (gain of 19.8 dB), and a reduction in NF of about 0.5 dB (below 1.9 dB in the frequency range).

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