序列检测器VHDL程序代码

序列检测器

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity detect110 is port(clk,D_in:in std_logic; en:in std_logic; D_out:out std_logic ); end entity;

architecture behav of detect110 is

type state is(s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11); signal n:state; signal p:state; begin process(clk) begin

if clk'event and clk='1' then n<=p; end if; end process; process(D_in,clk) begin if(en='1') then case n is when s0=> if(D_in='1') then p<=s1; else p<=s0; end if; D_out<='0'; when s1=>

if(D_in='1') then p<=s2; else p<=s0; end if; D_out<='0'; when s2=> if(D_in='1') then p<=s2; else p<=s3; end if;

D_out<='0';

when s3=> if(D_in='1') then p<=s0;

else p<=s4; end if; D_out<='0'; when s4=> if(D_in='1') then p<=s5; else p<=s0; end if; D_out<='0'; when s5=> if(D_in='1') then p<=s6; else p<=s0; end if; D_out<='0'; when s6=> if(D_in='1') then p<=s7; else p<=s3; end if; D_out<='0'; when s7=> if(D_in='0') then p<=s3; else p<=s8; end if;

D_out<='0'; when s8=> if(D_in='1') then p<=s2; else p<=s9; end if; D_out<='0'; when s9=>

if(D_in='1') then p<=s0; else p<=s10; end if; D_out<='0'; when s10=> if(D_in='1') then

p<=s5; else p<=s11; end if; D_out<='0'; when s11=> if(D_in='0') then p<=s0;

else p<=s0; D_out<='1'; end if; when others=>null; end case; else D_out<='0'; end if; end process; end behav;

交通灯 library IEEE;

use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity light is

port(clk: in std_logic;

dclk1:out std_logic; ra:out std_logic; ga:out std_logic; ya:out std_logic; rb:out std_logic; gb:out std_logic; yb:out std_logic ); end light;

architecture Behavioral of light is signal clk1: std_logic := '1'; signal q: integer range 0 to 24000000:=0;

begin

dclk1<=clk1; t1: process(clk) begin if clk'event and clk='1' then

if q=129 then q<=0;clk1<=not clk1; else

q<=q+1; end if ; end if; end process;

t3: process(q) begin

if q=0 then

ra<='0';ga<='1';ya<='0';rb<='1';gb<='0';yb<='0'; else if q=59 then ra<='0';ga<='0';ya<='1';rb<='1';gb<='0';yb<='0'; else if q=64 then ra<='1';ga<='0';ya<='0';rb<='0';gb<='1';yb<='0'; else if q=124 then ra<='1';ga<='0';ya<='0';rb<='0';gb<='0';yb<='1'; end if; end if; end if; end if; end process;

end Behavioral;

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