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Data Sheet, V2.3, March 2006

XC161CJ-16F

16-Bit Single-Chip Microcontroller withC166SV2 Core

Microcontrollers

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Edition 2006-03

Published by

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characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third http://www.77cn.com.cnrmation

For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (http://www.77cn.com.cn).Warnings

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© Infineon Technologies AG 2006.

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Data Sheet, V2.3, March 2006

XC161CJ-16F

16-Bit Single-Chip Microcontroller withC166SV2 Core

Microcontrollers

XC161

Revision History: V2.3, 2006-03Previous Version(s):V2.2, 2003-06V2.1, 2002-11V2.0, 2002-10V1.1, 2002-07V1.0, 2002-03Pageall7183

Subjects (major changes since last revision)

Layout of graphics and text structures has been adapted to the new company documentation rules.Minimum oscillator period correctedChapter “Package and Reliability” added.

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Table of Contents

Table of Contents

122.12.233.13.23.33.43.53.63.73.83.93.103.113.123.133.143.153.163.173.183.1944.14.24.34.44.4.14.4.24.4.34.4.44.4.555.15.2

Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Pin Configuration and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Memory Subsystem and Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20External Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26On-Chip Debug Support (OCDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Capture/Compare Units (CAPCOM1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 32General Purpose Timer (GPT12E) Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Asynchronous/Synchronous Serial Interfaces (ASC0/ASC1) . . . . . . . . . . 42High Speed Synchronous Serial Channels (SSC0/SSC1) . . . . . . . . . . . . 43Serial Data Link Module (SDLM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44TwinCAN Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45IIC Bus Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Analog/Digital Converter Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66Definition of Internal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66On-chip Flash Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70External Clock Drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

16-Bit Single-Chip Microcontroller withC166SV2 CoreXC166Family

XC161

1

Summary of Features

High Performance 16-bit CPU with 5-Stage Pipeline

–25 ns Instruction Cycle Time at 40 MHz CPU Clock (Single-Cycle Execution)–1-Cycle Multiplication (16 × 16 bit), Background Division (32 / 16 bit) in 21 Cycles–1-Cycle Multiply-and-Accumulate (MAC) Instructions–Enhanced Boolean Bit Manipulation Facilities–Zero-Cycle Jump Execution

–Additional Instructions to Support HLL and Operating Systems–Register-Based Design with Multiple Variable Register Banks

–Fast Context Switching Support with Two Additional Local Register Banks–16 Mbytes Total Linear Address Space for Code and Data

–1024 Bytes On-Chip Special Function Register Area (C166 Family Compatible)16-Priority-Level Interrupt System with 73 Sources, Sample-Rate down to 50 ns8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via

Peripheral Event Controller (PEC), 24-Bit Pointers Cover Total Address SpaceClock Generation via on-chip PLL (factors 1:0.15 … 1:10), orvia Prescaler (factors 1:1 … 60:1)On-Chip Memory Modules

–2 Kbytes On-Chip Dual-Port RAM (DPRAM)–4 Kbytes On-Chip Data SRAM (DSRAM)

–2 Kbytes On-Chip Program/Data SRAM (PSRAM)

–128 Kbytes On-Chip Program Memory (Flash Memory)On-Chip Peripheral Modules

–12-Channel A/D Converter with Programmable Resolution (10-bit or 8-bit) andConversion Time (down to 2.55 µs or 2.15 µs)

–Two 16-Channel General Purpose Capture/Compare Units (32 Input/Output Pins)–Multi-Functional General Purpose Timer Unit with 5 Timers–Two Synchronous/Asynchronous Serial Channels (USARTs)–Two High-Speed-Synchronous Serial Channels

–On-Chip TwinCAN Interface (Rev. 2.0B active) with 32 Message Objects(Full CAN/Basic CAN) on Two CAN Nodes, and Gateway Functionality–Serial Data Link Module (SDLM), compliant with J1850, supporting Class2–IIC Bus Interface (10-bit addressing, 400 kbit/s) with 3 Channels (multiplexed)–On-Chip Real Time Clock, Driven by Dedicated Oscillator

Idle, Sleep, and Power Down Modes with Flexible Power ManagementProgrammable Watchdog Timer and Oscillator Watchdog

Summary of Features

Up to 12 Mbytes External Address Space for Code and Data

–Programmable External Bus Characteristics for Different Address Ranges–Multiplexed or Demultiplexed External Address/Data Buses–Selectable Address Bus Width–16-Bit or 8-Bit Data Bus Width

–Five Programmable Chip-Select Signals

–Hold- and Hold-Acknowledge Bus Arbitration SupportUp to 99 General Purpose I/O Lines,

partly with Selectable Input Thresholds and HysteresisOn-Chip Bootstrap Loader

Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators,Logic Analyzer Disassemblers, Programming BoardsOn-Chip Debug Support via JTAG Interface144-Pin TQFP Package, 0.5 mm (19.7 mil) pitch

Ordering Information

The ordering code for Infineon microcontrollers provides an exact reference to therequired product. This ordering code identifies:

the derivative itself, i.e. its function set, the temperature range, and the supply voltagethe package and the type of delivery.

For the available ordering codes for the XC161 please refer to the “Product CatalogMicrocontrollers”, which summarizes all available microcontroller variants.

Note:The ordering codes for Mask-ROM versions are defined for each product after

verification of the respective ROM code.This document describes several derivatives of the XC161 group. Table1 enumeratesthese derivatives and summarizes the differences. As this document refers to all of thesederivatives, some descriptions may not apply to a specific product.

For simplicity all versions are referred to by the term XC161 throughout this document.

Table1Derivative1)

SAK-XC161CJ-16F40F,SAK-XC161CJ-16F20F

XC161 Derivative Synopsis

Temp. Range

Program Memory

On-Chip RAM

InterfacesASC0, ASC1,SSC0, SSC1,CAN0, CAN1,SDLM, IICASC0, ASC1,SSC0, SSC1,CAN0, CAN1,SDLM, IIC

Summary of Features

-40°C to 128 Kbytes 2 Kbytes DPRAM,125°CFlash4 Kbytes DSRAM,

2 Kbytes PSRAM-40 °C to 128 Kbytes 2 Kbytes DPRAM,85 °CFlash4 Kbytes DSRAM,

2 Kbytes PSRAM

SAF-XC161CJ-16F40F,SAF-XC161CJ-16F20F

1)This Data Sheet is valid for devices starting with and including design step AD.

General Device Information

2

2.1

General Device Information

Introduction

The XC161 derivatives are high-performance members of the Infineon XC166Family offull featured single-chip CMOS microcontrollers. These devices extend the functionalityand performance of the C166Family in terms of instructions (MAC unit), peripherals, andspeed. They combine high CPU performance (up to 40 million instructions per second)with high peripheral functionality and enhanced IO-capabilities. They also provide clockgeneration via PLL and various on-chip memory modules such as program Flash,program RAM, and data RAM.

Figure1

Logic Symbol

General Device Information

2.2Pin Configuration and Definition

The pins of the XC161 are described in detail in Table2, including all their alternatefunctions. Figure2 summarizes all pins in a condensed way, showing their location onthe 4 sides of the package. E*) and C*) mark pins to be used as alternate externalinterrupt inputs, C*) marks pins that can have CAN/SDLM interface lines assigned tothem.

Figure2Pin Configuration (top view)

Table2Sym-bolNMI

Pin Definitions and FunctionsPin Num.4

Input Outp.IOI

Function

For details, please refer to the description of P20.

Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the XC161 into power down mode. If NMI is high, when PWRDN is executed, the part will continue to run in normal mode.

If not used, pin NMI should be pulled high externally.Port6 is an 8-bit bidirectional I/O port. Each pin can be programmed for input (output driver in high-impedance state) or output (configurable as push/pull or open drain driver). The input threshold of Port6 is selectable (standard or special).

The Port6 pins also serve for alternate functions:CS0Chip Select 0 Output,CC0IOCAPCOM1: CC0 Capture Inp./Compare OutputCS1Chip Select 1 Output,CC1IOCAPCOM1: CC1 Capture Inp./Compare OutputCS2Chip Select 2 Output,CC2IOCAPCOM1: CC2 Capture Inp./Compare OutputCS3Chip Select 3 Output,CC3IOCAPCOM1: CC3 Capture Inp./Compare OutputCS4Chip Select 4 Output,CC4IOCAPCOM1: CC4 Capture Inp./Compare OutputHOLDExternal Master Hold Request Input,CC5IOCAPCOM1: CC5 Capture Inp./Compare OutputHLDAHold Acknowledge Output (master mode) or

Input (slave mode),

CC6IOCAPCOM1: CC6 Capture Inp./Compare OutputBREQBus Request Output,CC7IOCAPCOM1: CC7 Capture Inp./Compare Output

General Device Information

P20.123

P6IO

P6.0P6.1P6.2P6.3P6.4P6.5P6.6

78910111213O

I/OOI/OOI/OOI/OOI/OII/OO/II/OOI/O

P6.714

Table2Sym-bolP7

Pin Definitions and Functions (cont’d)Pin Num.

Input Outp.IO

Function

Port7 is a 4-bit bidirectional I/O port. Each pin can be programmed for input (output driver in high-impedance state) or output (configurable as push/pull or open drain driver). The input threshold of Port7 is selectable (standard or special).

Port7 pins provide inputs/outputs for CAPCOM2 and serial interface lines.1)CC28IOCAPCOM2: CC28 Capture Inp./Compare Outp.,CAN2_RxDCAN Node 2 Receive Data Input,EX7INFast External Interrupt 7 Input (alternate pin B)CC29IOCAPCOM2: CC29 Capture Inp./Compare Outp.,CAN2_TxDCAN Node 2 Transmit Data Output,EX6INFast External Interrupt 6 Input (alternate pin B)CC30IOCAPCOM2: CC30 Capture Inp./Compare Outp.,CAN1_RxDCAN Node 1 Receive Data Input,SDL_TxDSDLM Transmit Data Output,EX7INFast External Interrupt 7 Input (alternate pin A)CC31IOCAPCOM2: CC31 Capture Inp./Compare Outp.,CAN1_TxDCAN Node 1 Transmit Data Output,SDL_RxDSDLM Receive Data Input,EX6INFast External Interrupt 6 Input (alternate pin A)

General Device Information

P7.415

P7.516

P7.617

I/O

III/OOII/OIII/OOII

P7.718

Table2Sym-bolP9

Pin Definitions and Functions (cont’d)Pin Num.

Input Outp.IO

Function

Port9 is a 6-bit bidirectional I/O port. Each pin can be programmed for input (output driver in high-impedance state) or output (configurable as push/pull or open drain driver). The input threshold of Port9 is selectable (standard or special).

The following Port9 pins also serve for alternate functions:1)CC16IOCAPCOM2: CC16 Capture Inp./Compare Outp.,CAN2_RxDCAN Node 2 Receive Data Input,SDA0IIC Bus Data Line 0CC17IOCAPCOM2: CC17 Capture Inp./Compare Outp.,CAN2_TxDCAN Node 2 Transmit Data Output,SCL0IIC Bus Clock Line 0CC18IOCAPCOM2: CC18 Capture Inp./Compare Outp.,CAN1_RxDCAN Node 1 Receive Data Input,SDL_TxDSDLM Transmit Data Output,SDA1IIC Bus Data Line 1CC19IOCAPCOM2: CC19 Capture Inp./Compare Outp.,CAN1_TxDCAN Node 1 Transmit Data Output,SDL_RxDSDLM Receive Data Input,SCL1IIC Bus Clock Line 1CC20IOCAPCOM2: CC20 Capture Inp./Compare Outp.,SDA2IIC Bus Data Line 2CC21IOCAPCOM2: CC21 Capture Inp./Compare Outp.,SCL2IIC Bus Clock Line 2Port5 is a 12-bit input-only port.

The pins of Port5 also serve as analog input channels for the A/D converter, or they serve as timer inputs:AN0AN1AN2AN3AN4AN5AN6AN7AN12,T6INGPT2 Timer T6 Count/Gate InputAN13,T5INGPT2 Timer T5 Count/Gate InputAN14,T4EUDGPT1 Timer T4 Ext. Up/Down Ctrl. Inp.AN15,T2EUDGPT1 Timer T2 Ext. Up/Down Ctrl. Inp.

General Device Information

P9.021

P9.122

P9.223

P9.324

P9.4P9.5P5

2526

I/O

II/OI/OOI/OI/OIOI/OI/OOII/OI/OI/OI/OI/OI

P5.0P5.1P5.2P5.3P5.4P5.5P5.6P5.7P5.12P5.13P5.14P5.15293031323334394043444546IIIIIIIIIIII

Table2Sym-bolP2

Pin Definitions and Functions (cont’d)Pin Num.

Input Outp.IO

Function

Port2 is an 8-bit bidirectional I/O port. Each pin can be programmed for input (output driver in high-impedance state) or output (configurable as push/pull or open drain driver). The input threshold of Port2 is selectable (standard or special).

The following Port2 pins also serve for alternate functions:CC8IOCAPCOM1: CC8 Capture Inp./Compare Output,EX0INFast External Interrupt 0 Input (default pin)CC9IOCAPCOM1: CC9 Capture Inp./Compare Output,EX1INFast External Interrupt 1 Input (default pin)CC10IOCAPCOM1: CC10 Capture Inp./Compare Outp.,EX2INFast External Interrupt 2 Input (default pin)CC11IOCAPCOM1: CC11 Capture Inp./Compare Outp.,EX3INFast External Interrupt 3 Input (default pin)CC12IOCAPCOM1: CC12 Capture Inp./Compare Outp.,EX4INFast External Interrupt 4 Input (default pin)CC13IOCAPCOM1: CC13 Capture Inp./Compare Outp.,EX5INFast External Interrupt 5 Input (default pin)CC14IOCAPCOM1: CC14 Capture Inp./Compare Outp.,EX6INFast External Interrupt 6 Input (default pin)CC15IOCAPCOM1: CC15 Capture Inp./Compare Outp.,EX7INFast External Interrupt 7 Input (default pin),T7INCAPCOM2: Timer T7 Count InputTest-System Reset Input. A high-level at this pin activates the XC161’s debug system.

Note:For normal system operation, pin TRST should be

held low.

General Device Information

P2.8P2.9P2.10P2.11P2.12P2.13P2.14P2.15

4950515253545556

I/OII/OII/OII/OII/OII/OII/OII/OIII

TRST57

Table2Sym-bolP3

Pin Definitions and Functions (cont’d)Pin Num.

Input Outp.IO

Function

Port3 is a 15-bit bidirectional I/O port. Each pin can be programmed for input (output driver in high-impedance state) or output (configurable as push/pull or open drain driver). The input threshold of Port3 is selectable (standard or special).

The following Port3 pins also serve for alternate functions:T0INCAPCOM1 Timer T0 Count Input,TxD1ASC1 Clock/Data Output (Async./Sync),EX1INFast External Interrupt 1 Input (alternate pin B)T6OUTGPT2 Timer T6 Toggle Latch Output,RxD1ASC1 Data Input (Async.) or Inp./Outp. (Sync.),EX1INFast External Interrupt 1 Input (alternate pin A)CAPINGPT2 Register CAPREL Capture InputT3OUTGPT1 Timer T3 Toggle Latch OutputT3EUDGPT1 Timer T3 External Up/Down Control InputT4INGPT1 Timer T4 Count/Gate/Reload/Capture InpT3INGPT1 Timer T3 Count/Gate InputT2INGPT1 Timer T2 Count/Gate/Reload/Capture InpMRST0SSC0 Master-Receive/Slave-Transmit In/Out.MTSR0SSC0 Master-Transmit/Slave-Receive Out/In.TxD0ASC0 Clock/Data Output (Async./Sync.),EX2INFast External Interrupt 2 Input (alternate pin B)RxD0ASC0 Data Input (Async.) or Inp./Outp. (Sync.),EX2INFast External Interrupt 2 Input (alternate pin A)BHEExternal Memory High Byte Enable Signal,WRHExternal Memory High Byte Write Strobe,EX3INFast External Interrupt 3 Input (alternate pin B)SCLK0SSC0 Master Clock Output/Slave Clock Input.,EX3INFast External Interrupt 3 Input (alternate pin A)CLKOUTMaster Clock Output,FOUTProgrammable Frequency OutputDebug System: JTAG Clock InputDebug System: JTAG Data InDebug System: JTAG Data Out

Debug System: JTAG Test Mode Selection

General Device Information

P3.059

P3.160

P3.2

P3.3P3.4P3.5P3.6P3.7P3.8P3.9P3.10P3.11P3.12

6162636465666768697075

P3.13P3.15TCKTDITDOTMS

767771727374

IOIOI/OIIOIIIII/OI/OOII/OIOOII/OIOOIIOI

Table2Sym-bolP4

Pin Definitions and Functions (cont’d)Pin Num.

Input Outp.IO

Function

Port4 is an 8-bit bidirectional I/O port. Each pin can be programmed for input (output driver in high-impedance state) or output (configurable as push/pull or open drain driver). The input threshold of Port4 is selectable (standard or special).

Port4 can be used to output the segment address lines, the optional chip select lines, and for serial interface lines:1)A16Least Significant Segment Address LineA17Segment Address LineA18Segment Address LineA19Segment Address LineA20Segment Address Line,

CAN2_RxDCAN Node 2 Receive Data Input,SDL_RxDSDLM Receive Data Input,EX5INFast External Interrupt 5 Input (alternate pin B)A21Segment Address Line,

CAN1_RxDCAN Node 1 Receive Data Input,EX4INFast External Interrupt 4 Input (alternate pin B)A22Segment Address Line,

CAN1_TxDCAN Node 1 Transmit Data Output,SDL_RxDSDLM Receive Data Input,EX5INFast External Interrupt 5 Input (alternate pin A)A23Most Significant Segment Address Line,CAN1_RxDCAN Node 1 Receive Data Input,CAN2_TxDCAN Node 2 Transmit Data Output,SDL_TxDSDLM Transmit Data Output,EX4INFast External Interrupt 4 Input (alternate pin A)

General Device Information

P4.0

P4.1P4.2P4.3P4.48081828384

P4.585

P4.686

P4.787

OOOOOIIIOIIOOIIOIOOI

Table2Sym-bolP20

Pin Definitions and Functions (cont’d)Pin Num.

Input Outp.IO

Function

Port20 is a 6-bit bidirectional I/O port. Each pin can be programmed for input (output driver in high-impedance state) or output. The input threshold of Port20 is selectable (standard or special).

The following Port20 pins also serve for alternate functions:

External Memory Read Strobe, activated for RD

every external instruction or data read access.

WR/WRLExternal Memory Write Strobe.

In WR-mode this pin is activated for every external data write access.

In WRL-mode this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus.

READYREADY Input. When the READY function is

enabled, memory cycle time waitstates can be forced via this pin during an external access.

ALEAddress Latch Enable Output.

Can be used for latching the address into external memory or an address latch in the multiplexed bus modes.

EAExternal Access Enable pin.

A low-level at this pin during and after Reset forces the XC161 to latch the configuration from PORT0 and pin RD, and to begin instruction execution out of external memory.

A high-level forces the XC161 to latch the configuration from pins RD, ALE, and WR, and to begin instruction execution out of the internal program memory. “ROMless” versions must have this pin tied to ‘0’.

RSTOUTInternal Reset Indication Output.

Is activated asynchronously with an external hardware reset. It may also be activated (selectable) synchronously with an internal software or watchdog reset.

Is deactivated upon the execution of the EINIT instruction, optionally at the end of reset, or at any time (before EINIT) via user software.Note:Port20 pins may input configuration values (see EA).

General Device Information

P20.0P20.1

9091

OO

P20.292I

P20.493O

P20.594I

P20.123O

Table2Sym-bolPORT0P0L.0 - P0L.7, P0H.0,P0H.1, P0H.2 - P0H.7

95 - 102,105,106,111 - 116

Pin Definitions and Functions (cont’d)Pin Num.

Input Outp.IO

Function

PORT0 consists of the two 8-bit bidirectional I/O ports P0L and P0H. Each pin can be programmed for input (output driver in high-impedance state) or output.

In case of an external bus configuration, PORT0 serves as the address (A) and address/data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes.

Demultiplexed bus modes:

8-bit data bus: P0H = I/O, P0L = D7 - D0

16-bit data bus: P0H = D15 - D8, P0L = D7 - D0Multiplexed bus modes:

8-bit data bus: P0H = A15 - A8, P0L = AD7 - AD0

16-bit data bus: P0H = AD15 - AD8, P0L = AD7 - AD0Note:At the end of an external reset (EA = 0) PORT0 also

may input configuration values.

PORT1

IO

PORT1 consists of the two 8-bit bidirectional I/O ports P1L and P1H. Each pin can be programmed for input (output driver in high-impedance state) or output.

PORT1 is used as the 16-bit address bus (A) in

demultiplexed bus modes (also after switching from a demultiplexed to a multiplexed bus mode).

The following PORT1 pins also serve for alt. functions:(A0-6)Address output onlyCC22IOCC23IOEX0INMRST1MTSR1SCLK1EX0INCC24IOCC25IOCC26IOCC27IO

CAPCOM2: CC22 Capture Inp./Compare Outp.CAPCOM2: CC23 Capture Inp./Compare Outp.,Fast External Interrupt 0 Input (alternate pin B)SSC1 Master-Receive/Slave-Transmit In/Outp.SSC1 Master-Transmit/Slave-Receive Out/Inp.SSC1 Master Clock Output/Slave Clock Input,Fast External Interrupt 0 Input (alternate pin A)CAPCOM2: CC24 Capture Inp./Compare Outp.CAPCOM2: CC25 Capture Inp./Compare Outp.CAPCOM2: CC26 Capture Inp./Compare Outp.CAPCOM2: CC27 Capture Inp./Compare Outp.

General Device Information

P1L.0 - P1L.6P1L.7P1H.0P1H.1P1H.2P1H.3P1H.4P1H.5P1H.6P1H.7

117 - 123124127128129130131132133134

OI/OI/OII/OI/OI/OII/OI/OI/OI/O

Table2Sym-bolXTAL2XTAL1

Pin Definitions and Functions (cont’d)Pin Num.137138

Input Outp.OI

Function

Output of the main oscillator amplifier circuitInput to the main oscillator amplifier and input to the internal clock generator

To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed.

Input to the auxiliary (32-kHz) oscillator amplifierOutput of the auxiliary (32-kHz) oscillator amplifier circuit

To clock the device from an external source, drive XTAL3, while leaving XTAL4 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed.

Reset Input with Schmitt-Trigger characteristics. A low-level at this pin while the oscillator is running resets the XC161.A spike filter suppresses input pulses < 10 ns. Input pulses >100 ns safely pass the filter. The minimum duration for a safe recognition should be 100 ns + 2 CPU clock cycles.Note:The reset duration must be sufficient to let the

hardware configuration signals settle.

External circuitry must guarantee low-level at theRSTIN pin at least until both power supply voltageshave reached the operating range.

BRK OUTBRKINNC

1431441, 2, 107 - 1104142

OI–

Debug System: Break OutDebug System: Break In

No connection.

It is recommended not to connect these pins to the PCB.Reference voltage for the A/D converter.Reference ground for the A/D converter.Digital Core Supply Voltage (On-Chip Modules):+2.5 V during normal operation and idle mode.Please refer to the Operating Conditions.XTAL3:XTAL4:XTAL2:XTAL1:

General Device Information

XTAL3XTAL4140141IO

RSTIN142I

VAREFVAGNDVDDI

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48, 78, –135

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