NAND02GR4B2CN1F中文资料

November 2006 Rev 31/62

NAND01G-B2B NAND02G-B2C

1 Gbit,

2 Gbit,

2112 Byte/1056 Word Page, 1.8V/3V , NAND Flash Memory

Features

■

High Density NAND Flash memories –Up to 2 Gbit memory array –

Cost effective solutions for mass storage applications ■

NAND interface –x8 or x16 bus width –Multiplexed Address/ Data –

Pinout compatibility for all densities

■Supply voltage: 1.8V/3.0V ■

Page size –x8 device: (2048 + 64 spare) Bytes –

x16 device: (1024 + 32 spare) Words

■

Block size –x8 device: (128K + 4K spare) Bytes –

x16 device: (64K + 2K spare) Words ■

Page Read/Program –Random access: 25μs (max)–Sequential access: 30ns (min)–

Page program time: 200μs (typ)

■Copy Back Program mode

■Cache Program and Cache Read modes ■Fast Block Erase: 2ms (typ)■Status Register ■Electronic Signature ■

Chip Enable ‘don’t care’

■Serial Number option ■

Data protection –Hardware Block Locking

–

Hardware Program/Erase locked during Power transitions

■

Data integrity –100,000 Program/Erase cycles –

10 years Data Retention

■ECOPACK ? packages ■

Development tools –Error Correction Code models –Bad Blocks Management and Wear Leveling algorithms

–

Hardware simulation models

Table 1.

Product List

Reference Part Number

NAND01G-B2B

NAND01GR3B2B, NAND01GW3B2B NAND01GR4B2B , NAND01GW4B2B (1)NAND02G-B2C

NAND02GR3B2C, NAND02GW3B2C NAND02GR4B2C, NAND02GW4B2C (1)

1.x16 organization only available for MCP Products.

8dc0c28c83d049649b6658df

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元器件交易网8dc0c28c83d049649b6658df

Contents NAND01G-B2B, NAND02G-B2C

Contents

1Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.1Bad blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3Signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1Inputs/Outputs (I/O0-I/O7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.2Inputs/Outputs (I/O8-I/O15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.3Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.4Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.5Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.6Read Enable (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.7Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.8Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.9Ready/Busy (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.10V DD Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.11V SS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1Command Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.2Address Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.3Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.4Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.5Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.6Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6Device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.1Read Memory Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.1.1Random Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.1.2Page Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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NAND01G-B2B, NAND02G-B2C Contents

6.2Cache Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.3Page Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.3.1Sequential Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.3.2Random Data Input in a page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.4Copy Back Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.5Cache Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.6Block Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.7Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.8Read Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.8.1Write Protection Bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.8.2P/E/R Controller and Cache Ready/Busy Bit (SR6) . . . . . . . . . . . . . . . 31

6.8.3P/E/R Controller Bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.8.4Cache Program Error Bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.8.5Error Bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.8.6SR4, SR3 and SR2 are Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.9Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8Software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

8.1Bad Block Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

8.2NAND Flash memory failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

8.3Garbage Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.4Wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.5Error Correction Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.6Hardware Simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.6.1Behavioral simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.6.2IBIS simulations models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

9Program and Erase Times and Endurance cycles . . . . . . . . . . . . . . . . 40

10Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

11DC And AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

11.1Ready/Busy Signal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 54

11.2Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

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Contents NAND01G-B2B, NAND02G-B2C

12Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

13Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

14Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

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NAND01G-B2B, NAND02G-B2C List of tables

List of tables

Table 1.Product List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2.Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 3.Signal Names. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 4.Valid Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 5.Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 6.Address Insertion, x8 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 7.Address Insertion, x16 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 8.Address Definitions, x8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 9.Address Definitions, x16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 8dc0c28c83d049649b6658dfmands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 11.Copy Back Program x8 Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 12.Copy Back Program x16 Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 13.Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 14.Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 15.Electronic Signature Byte 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 16.Electronic Signature Byte/Word 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 17.NAND Flash failure modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 18.Program, Erase Times and Program Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . . 40

Table 19.Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 20.Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 21.Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 22.DC Characteristics, 1.8V Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 23.DC Characteristics, 3V Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 24.AC Characteristics for Command, Address, Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 25.AC Characteristics for Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 26.TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Mechanical Data. . . 57

Table 27.VFBGA63 9.5x12mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data. . 58

Table 28.VFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data . . . 59

Table 29.Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 30.Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

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List of figures NAND01G-B2B, NAND02G-B2C

List of figures

Figure 1.Logic Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 2.Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 3.TSOP48 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 4.VFBGA63 Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 5.Memory Array Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 6.Read Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 7.Random Data Output During Sequential Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 8.Cache Read Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 9.Page Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 10.Random Data Input During Sequential Data Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 11.Copy Back Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 12.Page Copy Back Program with Random Data Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 13.Cache Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 14.Block Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 15.Bad Block Management Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 16.Garbage Collection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 17.Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 18.Equivalent Testing Circuit for AC Characteristics Measurement . . . . . . . . . . . . . . . . . . . . 43

Figure 8dc0c28c83d049649b6658dfmand Latch AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 20.Address Latch AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 21.Data Input Latch AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 22.Sequential Data Output after Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 23.Read Status Register AC waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 24.Read Electronic Signature AC waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 25.Page Read operation AC waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 26.Page Program AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 27.Block Erase AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 28.Reset AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 29.Program/Erase Enable waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 30.Program/Erase Disable waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 31.Ready/Busy AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 32.Ready/Busy Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 33.Resistor value versus waveform timings for Ready/Busy signal. . . . . . . . . . . . . . . . . . . . . 56

Figure 34.Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 35.TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline . . . . . . . . . . 57

Figure 36.VFBGA63 9.5x12mm - 6x8 active ball array, 0.80mm pitch, Package Outline. . . . . . . . . . 58

Figure 37.VFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, Package Outline . . . . . . . . . . . 59

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NAND01G-B2B, NAND02G-B2C Description

1 Description

ST NAND01G-B2B and NAND02G-B2C Flash 2112 Byte/ 1056 Word Page is a family of

non-volatile Flash memories that uses NAND cell technology. The devices range from 1 Gbit

to 2 Gbits and operate with either a 1.8V or 3V voltage supply. The size of a Page is either

2112 Bytes (2048 + 64 spare) or 1056 Words (1024 + 32 spare) depending on whether the

device has a x8 or x16 bus width.

The address lines are multiplexed with the Data Input/Output signals on a multiplexed x8 or

x16 Input/Output bus. This interface reduces the pin count and makes it possible to migrate

to other densities without changing the footprint.

Each block can be programmed and erased over 100,000 cycles. T o extend the lifetime of

NAND Flash devices it is strongly recommended to implement an Error Correction Code

(ECC).

The devices feature a Write Protect pin that allows performing hardware protection against

program and erase operations.

The devices feature an open-drain Ready/Busy output that can be used to identify if the

Program/Erase/Read (P/E/R) Controller is currently active. The use of an open-drain output

allows the Ready/Busy pins from several memories to be connected to a single pull-up

resistor.

A Copy Back Program command is available to optimize the management of defective

blocks. When a Page Program operation fails, the data can be programmed in another page

without having to resend the data to be programmed.

Each device has Cache Program and Cache Read features which improve the program and

read throughputs for large files. During Cache Programming, the device loads the data in a

Cache Register while the previous data is transferred to the Page Buffer and programmed

into the memory array. During Cache Reading, the device loads the data in a Cache

Register while the previous data is transferred to the I/O Buffers to be read.

All devices have the Chip Enable Don’t Care feature, which allows code to be directly

downloaded by a microcontroller, as Chip Enable transitions during the latency time do not

stop the read operation.

All devices have the option of a Unique Identifier (serial number), which allows each device

to be uniquely identified.

The Unique Identifier options is subject to an NDA (Non Disclosure Agreement) and so not

described in the datasheet. For more details of this option contact your nearest ST Sales

office.

The devices are available in the following packages:

●TSOP48 (12 x 20mm)

●VFBGA63 (9.5 x 12 x 1mm, 0.8mm pitch) for NAND02G-B2C devices.

●VFBGA63 (9 x 11 x 1mm, 0.8mm pitch) for NAND01G-B2B devices.

In order to meet environmental requirements, ST offers the NAND01G-B2B and NAND02G-

B2C in ECOPACK? packages. ECOPACK packages are Lead-free. The category of second

Level Interconnect is marked on the package and on the inner box label, in compliance with

JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also

marked on the inner box label. ECOPACK is an ST trademark.

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Description NAND01G-B2B, NAND02G-B2C

8/62For information on how to order these options refer to Table29: Ordering Information Scheme. Devices are shipped from the factory with Block 0 always valid and the memory content bits, in valid blocks, erased to ’1’.

See Table2: Product Description, for all the devices available in the family.

Table 2.Product Description

Reference Part Number Density

Bus

Width

Page

Size

Block

Size

Memory

Array

Operatin

g Voltage

Timings

Package

Random

access

time

(max)

Sequential

access

time

(min)

Page

Program

time

(typ)

Block

Erase

(typ)

NAND01G

-B2B NAND01GR3B2B

1Gbit

x8

2048+

64

Bytes

128K+

4K

Bytes64

Pages x

1024

Blocks

1.7 to

1.95V

25μs50ns

200μs

2ms

VFBGA63

9x11mm NAND01GW3B2B

2.7 to

3.6V

25μs30ns TSOP48 NAND01GR4B2B

x16

1024+

32

Words

64K+

2K

Words

1.7 to

1.95V

25μs50ns(1) NAND01GW4B2B

2.7 to

3.6V

25μs30ns(1)

NAND02G

-B2C NAND02GR3B2C

2Gbit

x8

2048+

64

Bytes

128K+

4K

Bytes64

Pages x

2048

Blocks

1.7 to

1.95V

25μs50ns

2ms

VFBGA63

9.5x12mm NAND02GW3B2C

2.7 to

3.6V

25μs30ns TSOP48 NAND02GR4B2C

x16

1024+

32

Words

64K+

2K

Words

1.7 to

1.95V

25μs50ns(1) NAND02GW4B2C

2.7 to

3.6V

25μs30ns(1)

1.x16 organization only available for MCP 元器件交易网8dc0c28c83d049649b6658df

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NAND01G-B2B, NAND02G-B2C Description

1.x16 organization only available for MCP

9/62

Description NAND01G-B2B, NAND02G-B2C

10/62Table 3.Signal Names

I/O8-15Data Input/Outputs for x16 devices

I/O0-7

Data Input/Outputs, Address Inputs, or Command Inputs for x8 and

x16 devices

AL Address Latch Enable

CL Command Latch Enable

E Chip Enable

R Read Enable

RB Ready/Busy (open-drain output)

W Write Enable

WP Write Protect

V DD Supply Voltage

V SS Ground

NC Not Connected Internally

DU Do Not Use

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元器件交易网8dc0c28c83d049649b6658df

NAND01G-B2B, NAND02G-B2C Description

1.Available only for NAND01GW3B2B and NAND02GW3B2C 8-bit devices.

11/62

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Description NAND01G-B2B, NAND02G-B2C

1.Available only for NAND01GR3B2B and NAND02GR3B2C 8-bit devices.

12/62

NAND01G-B2B, NAND02G-B2C Memory array organization 13/622 Memory array organization

The memory array is made up of NAND structures where 32 cells are connected in series.

The memory array is organized in blocks where each block contains 64 pages. The array is

split into two areas, the main area and the spare area. The main area of the array is used to

store data whereas the spare area is typically used to store Error correction Codes, software

flags or Bad Block identification.

In x8 devices the pages are split into a 2048 Byte main area and a spare area of 64 Bytes.

In the x16 devices the pages are split into a 1,024 Word main area and a 32 Word spare

area. Refer to Figure 5: Memory Array Organization .

2.1 Bad blocks

The NAND Flash 2112 Byte/ 1056 Word Page devices may contain Bad Blocks, that is

blocks that contain one or more invalid bits whose reliability is not guaranteed. Additional

Bad Blocks may develop during the lifetime of the device.

The Bad Block Information is written prior to shipping (refer to Section 8.1: Bad Block

Management for more details).

Table 4: Valid Blocks shows the minimum number of valid blocks in each device. The values

shown include both the Bad Blocks that are present when the device is shipped and the Bad

Blocks that could develop later on.

These blocks need to be managed using Bad Blocks Management, Block Replacement or

Error Correction Codes (refer to Section 8: Software algorithms ).

Table 4.Valid Blocks

Density of Device

Min Max 2 Gbits

200820481 Gbit 10041024

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Memory array organization NAND01G-B2B, NAND02G-B2C

14/62

NAND01G-B2B, NAND02G-B2C Signals description 15/623 Signals description

See Figure 2: Logic Diagram , and T able 3: Signal Names , for a brief overview of the signals

connected to this device.

3.1 Inputs/Outputs (I/O0-I/O7)

Input/Outputs 0 to 7 are used to input the selected address, output the data during a Read

operation or input a command or data during a Write operation. The inputs are latched on

the rising edge of Write Enable. I/O0-I/O7 are left floating when the device is deselected or

the outputs are disabled.

3.2 Inputs/Outputs (I/O8-I/O15)

Input/Outputs 8 to 15 are only available in x16 devices. They are used to output the data

during a Read operation or input data during a Write operation. Command and Address

Inputs only require I/O0 to I/O7.

The inputs are latched on the rising edge of Write Enable. I/O8-I/O15 are left floating when

the device is deselected or the outputs are disabled.

3.3 Address Latch Enable (AL)

The Address Latch Enable activates the latching of the Address inputs in the Command

Interface. When AL is high, the inputs are latched on the rising edge of Write Enable.

3.4 Command Latch Enable (CL)

The Command Latch Enable activates the latching of the Command inputs in the Command

Interface. When CL is high, the inputs are latched on the rising edge of Write Enable.

3.5 The Chip Enable input activates the memory control logic, input buffers, decoders and

sense amplifiers. When Chip Enable is low, V IL , the device is selected. If Chip Enable goes

high, v IH , while the device is busy, the device remains selected and does not go into standby

mode.

3.6 The Read Enable pin, R, controls the sequential data output during Read operations. Data

is valid t RLQV after the falling edge of R. The falling edge of R also increments the internal

column address counter by one.

元器件交易网8dc0c28c83d049649b6658df

Signals description NAND01G-B2B, NAND02G-B2C 16/62 3.7 Data latches. Both addresses and data are latched on the rising edge of Write Enable.

During power-up and power-down a recovery time of 10μs (min) is required before the

Command Interface is ready to accept a command. It is recommended to keep Write Enable high during the recovery time.

3.8 Write Protect (WP)

The Write Protect pin is an input that gives a hardware protection against unwanted program

or erase operations. When Write Protect is Low, V IL , the device does not accept any

program or erase operations.

It is recommended to keep the Write Protect pin Low, V IL , during power-up and power-down.

3.9 Ready/Busy (RB)

Controller is currently active. When Ready/Busy is Low, V OL , a read, program or erase

operation is in progress. When the operation completes Ready/Busy goes High, V OH .

The use of an open-drain output allows the Ready/Busy pins from several memories to be

connected to a single pull-up resistor. A Low will then indicate that one, or more, of the

memories is busy.

Refer to the Section 11.1: Ready/Busy Signal electrical characteristics for details on how to

calculate the value of the pull-up resistor.

3.10 V DD Supply Voltage

V DD provides the power supply to the internal core of the memory device. It is the main

power supply for all operations (read, program and erase).

An internal voltage detector disables all functions whenever V DD is below V LKO (see

Table 22 and Table 23) to protect the device from any involuntary program/erase during

power-transitions.

Each device in a system should have V DD decoupled with a 0.1μF capacitor. The PCB track

widths should be sufficient to carry the required program and erase currents.

3.11 V SS Ground

Ground, V SS, is the reference for the power supply. It must be connected to the system

ground.

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NAND01G-B2B, NAND02G-B2C Bus operations 17/624 Bus operations

There are six standard bus operations that control the memory. Each of these is described

in this section, see Table 5: Bus Operations , for a summary.

Typically, glitches of less than 5 ns on Chip Enable, Write Enable and Read Enable are

ignored by the memory and do not affect bus operations.

4.1 Command Input

Command Input bus operations are used to give commands to the memory. Commands are

accepted when Chip Enable is Low, Command Latch Enable is High, Address Latch Enable

is Low and Read Enable is High. They are latched on the rising edge of the Write Enable

signal.

Only I/O0 to I/O7 are used to input commands.

See Figure 19 and T able 24 for details of the timings requirements.

4.2 Address Input

Address Input bus operations are used to input the memory addresses. Four bus cycles are

required to input the addresses for 1Gb devices whereas five bus cycles are required for the

2Gb device (refer to Table 6 and Table 7, Address Insertion).

The addresses are accepted when Chip Enable is Low, Address Latch Enable is High,

Command Latch Enable is Low and Read Enable is High. They are latched on the rising

edge of the Write Enable signal. Only I/O0 to I/O7 are used to input addresses.

See Figure 20 and T able 24 for details of the timings requirements.

4.3 Data Input

Data Input bus operations are used to input the data to be programmed.

Data is accepted only when Chip Enable is Low, Address Latch Enable is Low, Command

Latch Enable is Low and Read Enable is High. The data is latched on the rising edge of the

Write Enable signal. The data is input sequentially using the Write Enable signal.

See Figure 21 and T able 24 and Table 25 for details of the timings requirements.

4.4 Data Output

Data Output bus operations are used to read: the data in the memory array, the Status

Register, the lock status, the Electronic Signature and the Unique Identifier.

Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low,

and Command Latch Enable is Low. The data is output sequentially using the Read Enable

signal.

See Figure 22 and T able 25 for details of the timings requirements.

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Bus operations NAND01G-B2B, NAND02G-B2C

18/62

4.5 Write Protect

Write Protect bus operations are used to protect the memory against program or erase

operations. When the Write Protect signal is Low the device will not accept program or erase operations and so the contents of the memory array cannot be altered. The Write Protect signal is not latched by Write Enable to ensure protection even during power-up.

4.6 Standby

When Chip Enable is High the memory enters Standby mode, the device is deselected, outputs are disabled and power consumption is reduced.

Table 5.

Bus Operations

Bus Operation E AL CL R W WP I/O0 - I/O7I/O8 - I/O15(1)

1.Only for x16 devices.

Command Input V IL V IL V IH V IH Rising X (2)2.WP must be V IH when issuing a program or erase command.

Command X Address Input V IL V IH V IL V IH Rising X Address X Data Input V IL V IL V IL V IH Rising V IH Data Input Data Input Data Output V IL V IL V IL Fallin g V IH X Data Output

Data Output

Write Protect X X X X X V IL X X Standby

V IH

X

X

X

X

V IL /V D

D

X

X

Table 6.

Address Insertion, x8 Devices

Bus Cycle (1)

1.Any additional address input cycles will be ignored.

I/O7I/O6I/O5I/O4I/O3I/O2I/O1I/O01st A7A6A5A4A3A2A1A02nd V IL V IL V IL V IL A11A10A9A83rd A19A18A17A16A15A14A13A124th A27A26A25A24A23A22A21A205th(2)

2.The fifth cycle is valid for 2Gb devices. A28 is for 2Gb devices only.

V IL

V IL

V IL

V IL

V IL

V IL

V IL

A28

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NAND01G-B2B, NAND02G-B2C

Bus operations

19/62

Table 7.

Address Insertion, x16 Devices

Bus Cycle (1)

1.Any additional address input cycles will be ignored.

I/O8-I/O15I/O7I/O6I/O5I/O4I/O3I/O2I/O1I/O01st X A7A6A5A4A3A2A1A02nd X V IL V IL V IL V IL V IL A10A9A83rd X A18A17A16A15A14A13A12A114th X A26A25A24A23A22A21A20A195th(2)

2.The fifth cycle is valid for 2Gb devices. A27 is for 2Gb devices only.

X

V IL

V IL

V IL

V IL

V IL

V IL

V IL

A27

Table 8.

Address Definitions, x8

Address Definition A0 - A11Column Address A12 - A17Page Address

A18 - A27Block Address 1Gb device A18 - A28

Block Address

2Gb device

Table 9.

Address Definitions, x16

Address Definition A0 - A10Column Address A11 - A16Page Address

A17 - A26Block Address 1Gb device A17 - A27

Block Address

2Gb device

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Command Set NAND01G-B2B, NAND02G-B2C

20/62

5 Command Set

All bus write operations to the device are interpreted by the Command Interface. The

Commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when the Command Latch Enable signal is high. Device operations are selected by writing specific commands to the Command Register. The two-step command sequences for program and erase operations are imposed to maximize data security.The Commands are summarized in Table 10: Commands .

Table 10.

Commands

Command

Bus Write Operations (1)

1.The bus cycles are only shown for issuing the codes. The cycles required to input the

addresses or input/output data are not 8dc0c28c83d049649b6658dfmands accepted during

busy

1st CYCLE

2nd CYCLE 3rd CYCLE 4th CYCLE

Read

00h 30h ––Random Data Output 05h E0h ––Cache Read 00h 31h ––Exit Cache Read 34h –––Y es (2)

2.Only during Cache Read busy.

Page Program

(Sequential Input default)80h 10h ––Random Data Input 85h –––Copy Back Program 00h 35h 85h 10h Cache Program 80h 15h ––Block Erase 60h D0h ––Reset

FFh –––Y es Read Electronic Signature 90h –––Read Status Register

70h

–

–

–

Y es 元器件交易网8dc0c28c83d049649b6658df

NAND01G-B2B, NAND02G-B2C Device operations 21/626 Device operations

The following section gives the details of the device operations.

6.1 Read Memory Array

At Power-Up the device defaults to Read mode. To enter Read mode from another mode the

Read command must be issued, see Table 10: Commands .

Once a Read command is issued two types of operations are available: Random Read and

Page Read.

6.1.1 Random Read

Each time the Read command is issued the first read is Random Read.

6.1.2 Page Read

After the first Random Read access, the page data (2112 Bytes or 1056 Words) is

transferred to the Page Buffer in a time of t WHBH (refer to T able 25 for value). Once the

transfer is complete the Ready/Busy signal goes High. The data can then be read out

sequentially (from selected column address to last column address) by pulsing the Read

Enable signal.

The device can output random data in a page, instead of the consecutive sequential data, by

issuing a Random Data Output command .

The Random Data Output command can be used to skip some data during a sequential

data output.

The sequential operation can be resumed by changing the column address of the next data

to be output, to the address which follows the Random Data Output command.

The Random Data Output command can be issued as many times as required within a

page.

The Random Data Output command is not accepted during Cache Read operations.

元器件交易网8dc0c28c83d049649b6658df

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