M95128-RDW6TPV中文资料

June 2006 Rev 71/41

M95128

M95128-W M95128-R

128 Kbit Serial SPI bus EEPROM

with high speed clock

Feature summary

■Compatible with SPI Bus Serial Interface

(Positive Clock SPI Modes)

■Single Supply Voltage:

– 4.5 to 5.5V for M95128

– 2.5 to 5.5V for M95128-W

– 1.8 to 5.5V for M95128-R

■High Speed

–5MHz Clock Rate, 5ms Write Time

■Status Register

■Hardware Protection of the Status Register

■BYTE and PAGE WRITE (up to 64 Bytes)

■Self-Timed Programming Cycle

■Adjustable Size Read-Only EEPROM Area

■Enhanced ESD Protection

■More than 100,000 Write Cycles

■More than 40-Year Data Retention

■

Packages

–ECOPACK? (RoHS compliant)

6b46a386cc22bcd126ff0cb0 元器件交易网6b46a386cc22bcd126ff0cb0

元器件交易网6b46a386cc22bcd126ff0cb0

Contents M95128, M95128-W, M95128-R

Contents

1Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.1Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.2Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.3Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.4Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.59

3.6Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.7Supply voltage (V CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.7.1Operating supply voltage V CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.7.2Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.7.3Internal device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.7.4Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.1Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.2Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.3Data Protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.1Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.2Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.3Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.3.1WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.3.2WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.3.3BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.3.4SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.4Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.5Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.6Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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M95128, M95128-W, M95128-R Contents

5.6.1ECC (Error Correction Code) and Write cycling . . . . . . . . . . . . . . . . . . 22

6Delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.1SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

8Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

9DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

10Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

11Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

12Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3/41

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List of tables M95128, M95128-W, M95128-R

List of tables

Table 1.Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 2.Write-Protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 3.Instruction set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 4.Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 5.Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 6.Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 7.Operating conditions (M95128) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 8.Operating conditions (M95128-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 9.Operating conditions (M95128-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 10.AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 11.Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 12.DC characteristics (M95128, Device Grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 13.DC characteristics (M95128-W, Device Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 14.DC characteristics (M95128-W, Device Grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 15.DC characteristics (M95128-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 16.AC characteristics (M95128, Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 17.AC characteristics (M95128-W, Device Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 18.AC characteristics (M95128-W, Device Grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 19.AC characteristics (M95128-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 20.SO8N – 8 lead Plastic Small Outline, 150 mils body width, package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 21.TSSOP8 – 8 lead Thin Shrink Small Outline, package mechanical data . . . . . . . . . . . . . . 37

Table 22.Ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 23.Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

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M95128, M95128-W, M95128-R List of figures

List of figures

Figure 1.Logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2.SO and TSSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3.Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4.Hold condition activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 5.Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 6.Write Disable (WRDI) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 7.Read Status Register (RDSR) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 8.Write Status Register (WRSR) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 9.Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 10.Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 11.Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 12.Bus master and memory devices on the SPI bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 13.SPI modes supported. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 14.AC measurement I/O waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 15.Serial input timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 16.Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 17.Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 18.SO8N – 8 lead Plastic Small Outline, 150 mils body width, package outline . . . . . . . . . . . 36

Figure 19.TSSOP8 – 8 lead Thin Shrink Small Outline, package outline. . . . . . . . . . . . . . . . . . . . . . 37

5/41

Summary description M95128, M95128-W, M95128-R

6/41

1 Summary description

These electrically erasable programmable memory (EEPROM) devices are accessed by a

high speed SPI-compatible bus. The memory array is organized as 16384 x 8 bits.The device is accessed by a simple serial interface that is SPI-compatible. The bus signals are C, D and Q, as shown in Table 1 and Figure 1.

The device is selected when Chip Select (S) is taken Low. Communications with the device can be interrupted using Hold (HOLD).

In order to meet environmental requirements, ST offers these devices in ECOPACK? packages. ECOPACK? packages are Lead-free and RoHS compliant.

ECOPACK is an ST trademark. ECOPACK specifications are available at: 6b46a386cc22bcd126ff0cb0 .

1.See Section 10: Package mechanical for package dimensions, and how to identify pin-1.

元器件交易网6b46a386cc22bcd126ff0cb0

M95128, M95128-W, M95128-R Summary description 7/41 Table 1.

Signal names C Serial Clock

D

Serial Data Input Q

Serial Data Output S Chip Select W Write

Protect HOLD Hold V CC

Supply Voltage V SS Ground

元器件交易网6b46a386cc22bcd126ff0cb0

Memory organization M95128, M95128-W, M95128-R

8/41

2 Memory organization

The memory is organized as shown in Figure 3.

元器件交易网6b46a386cc22bcd126ff0cb0

M95128, M95128-W, M95128-R Signal description 9/413 Signal description

See Figure 1: Logic diagram and Table 1: Signal names , for a brief overview of the signals

connected to this device.

3.1 Serial Data Output (Q)

This output signal is used to transfer data serially out of the device. Data is shifted out on the

falling edge of Serial Clock (C).

3.2 Serial Data Input (D)

This input signal is used to transfer data serially into the device. It receives instructions,

addresses, and the data to be written. Values are latched on the rising edge of Serial Clock

(C).

3.3 Serial Clock (C)

This input signal provides the timing of the serial interface. Instructions, addresses, or data

present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on

Serial Data Output (Q) changes after the falling edge of Serial Clock (C).

3.4 When this input signal is High, the device is deselected and Serial Data Output (Q) is at high

impedance. Unless an internal Write cycle is in progress, the device will be in the Standby Power mode. Driving Chip Select (S) Low selects the device, placing it in the Active Power

mode.After Power-up, a falling edge on Chip Select (S) is required prior to the start of any

instruction.

3.5 Hold (HOLD)deselecting the device.

During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data

Input (D) and Serial Clock (C) are Don’t Care.元器件交易网6b46a386cc22bcd126ff0cb0

Signal description M95128, M95128-W, M95128-R 10/41 3.6 The main purpose of this input signal is to freeze the size of the area of memory that is

protected against Write instructions (as specified by the values in the BP1 and BP0 bits of

the Status Register).

This pin must be driven either High or Low, and must be stable during all write instructions.

3.7

Supply voltage (V CC )3.7.1 Operating supply voltage V CC

Prior to selecting the memory and issuing instructions to it, a valid and stable V CC voltage

must be applied: this voltage must be a DC voltage within the specified [V CC (min),

V CC (max)] range, as defined in Table 7, Table 8 and Table 9. In order to secure a stable DC

supply voltage, it is recommended to decouple the V CC line with a suitable capacitor (usually

of the order of 10nF to 100nF) close to the V CC /V SS package pins.

The V CC voltage must remain stable and valid until the end of the transmission of the

instruction and, for a Write instruction, until the completion of the internal write cycle (t W ).

3.7.2 Power-up conditions

When the power supply is turned on, V CC rises from V SS to V CC . During this time, the Chip Select (S) signal is not allowed to float and must follow the V CC voltage. The S line should

therefore be connected to V CC via a suitable pull-up resistor.In addition, the Chip Select (S) input offers a built-in safety feature, as it is both edge

sensitive and level sensitive. Practically this means that after power-up, the device cannot become selected until a falling edge has first been detected on Chip Select (S). So the Chip

Select (S) signal must first have been High and then gone Low before the first operation can

be started.

3.7.3 Internal device reset

In order to prevent inadvertent Write operations during Power-up, a Power On Reset (POR)

circuit is included. At Power-up (continuous rise of V CC ), the device will not respond to any

instruction until the V CC has reached the Power On Reset threshold voltage (this threshold

is lower than the minimum V CC operating voltage defined in Section 9: DC and AC

parameters ).

When V CC has passed the POR threshold voltage, the device is reset and in the following

state:

●in Standby Power mode ●

instructions can be executed)●not in the Hold Condition Status Register state:

–

the Write Enable Latch (WEL) bit is reset to 0–the Write In Progress (WIP) bit is reset to 0.

The SRWD, BP1 and BP0 bits of the Status Register are at the same logic level as

when the device was last powered down (they are non-volatile bits).

元器件交易网6b46a386cc22bcd126ff0cb0

M95128, M95128-W, M95128-R Operating features

11/413.7.4 Power-down

At Power-down, the device must be deselected and in Standby Power mode (that is, there the voltage applied on V CC .

4 Operating features

4.1 Hold condition The Hold (HOLD) signal is used to pause any serial communications with the device without

resetting the clocking sequence.

During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data

Input (D) and Serial Clock (C) are Don’t Care.To enter the Hold condition, the device must be selected, with Chip Select (S) Low.

Normally, the device is kept selected, for the whole duration of the Hold condition.

Deselecting the device while it is in the Hold condition, has the effect of resetting the state of

the device, and this mechanism can be used if it is required to reset any processes that had

been in progress.The Hold condition starts when the Hold (HOLD) signal is driven Low at the same time as

Serial Clock (C) already being Low (as shown in Figure 4).The Hold condition ends when the Hold (HOLD) signal is driven High at the same time as

Serial Clock (C) already being Low.

Figure 4 also shows what happens if the rising and falling edges are not timed to coincide

with Serial Clock (C) being Low.

元器件交易网6b46a386cc22bcd126ff0cb0

Operating features M95128, M95128-W, M95128-R 12/41 4.2 Status Register

Figure 3 shows the position of the Status Register in the control logic of the device. The

Status Register contains a number of status and control bits that can be read or set (as

appropriate) by specific instructions. For a detailed description of the Status Register bits,

see Section 5.3: Read Status Register (RDSR).

4.3 Data Protection and protocol control

Non-volatile memory devices can be used in environments that are particularly noisy, and

within applications that could experience problems if memory bytes are corrupted.

Consequently, the device features the following data protection mechanisms:

●

Write and Write Status Register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution.●All instructions that modify data must be preceded by a Write Enable (WREN)

instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state

by the following events:

–

Power-up –

Write Disable (WRDI) instruction completion –

Write Status Register (WRSR) instruction completion –Write (WRITE) instruction completion

●

The Block Protect (BP1, BP0) bits allow part of the memory to be configured as read-only. This is the Software Protected Mode (SPM).●The Write Protect (W) signal allows the Block Protect (BP1, BP0) bits to be protected.

This is the Hardware Protected Mode (HPM).

For any instruction to be accepted, and executed, Chip Select (S) must be driven High after

the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising

edge of Serial Clock (C).

Two points need to be noted in the previous sentence:

●The ‘last bit of the instruction’ can be the eighth bit of the instruction code, or the eighth

bit of a data byte, depending on the instruction (except for Read Status Register

(RDSR) and Read (READ) instructions).

●The ‘next rising edge of Serial Clock (C)’ might (or might not) be the next bus

transaction for some other device on the SPI bus.

Table 2.Write-Protected block size

Status Register Bits Protected Block Array Addresses Protected

BP1 BP0 M95128, M95128-W, M95128-R

0 0 none none

0 1 Upper quarter 3000h - 3FFFh

1 0 Upper half 2000h - 3FFFh

1 1 Whole memory

0000h - 3FFFh 元器件交易网6b46a386cc22bcd126ff0cb0

M95128, M95128-W, M95128-R Instructions 13/415 Instructions

Each instruction starts with a single-byte code, as summarized in Table 3.

If an invalid instruction is sent (one not contained in Table 3), the device automatically

deselects itself.

5.1 Write Enable (WREN)

The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.

The only way to do this is to send a Write Enable instruction to the device.

As shown in Figure 5and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then High.

Table 3.Instruction set

Instruction Description Instruction Format

WREN Write Enable

0000 0110WRDI Write Disable

0000 0100RDSR

Read Status Register 0000 0101WRSR

Write Status Register 0000 0001READ

Read from Memory Array 0000 0011WRITE Write to Memory Array 0000 0010

元器件交易网6b46a386cc22bcd126ff0cb0

元器件交易网6b46a386cc22bcd126ff0cb0

Instructions M95128, M95128-W, M95128-R

5.2 Write Disable (WRDI)

One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction

to the device.

As shown in Figure6

and the bits of the instruction byte are shifted in, on Serial Data Input (D).

The device then enters a wait state. It waits for a the device to be deselected, by Chip Select

The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:

●Power-up

●WRDI instruction execution

●WRSR instruction completion

●WRITE instruction completion.

14/41

M95128, M95128-W, M95128-R Instructions

15/415.3 Read Status Register (RDSR)

The Read Status Register (RDSR) instruction allows the Status Register to be read. The

Status Register may be read at any time, even while a Write or Write Status Register cycle

is in progress. When one of these cycles is in progress, it is recommended to check the

Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible

to read the Status Register continuously, as shown in Figure 7.

The status and control bits of the Status Register are as follows:

5.3.1 WIP bit

The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write

Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such

cycle is in progress.

5.3.2 WEL bit

The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.

When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable

Latch is reset and no Write or Write Status Register instruction is accepted.

5.3.3 BP1, BP0 bits

The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be

software protected against Write instructions. These bits are written with the Write Status

Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to

1, the relevant memory area (as defined in Table 4) becomes protected against Write

(WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the

Hardware Protected mode has not been set.

5.3.4 SRWD bit

The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write signal allow the device to be put in the Hardware Protected mode (when the Status Register non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the

Write Status Register (WRSR) instruction is no longer accepted for execution.

Table 4.

Status Register format b7

b0SRWD 0 0 0 BP1 BP0 WEL WIP

Status Register Write Protect

Block Protect Bits

Write Enable Latch Bit

Write In Progress Bit

元器件交易网6b46a386cc22bcd126ff0cb0

Instructions M95128, M95128-W, M95128-R

16/41

元器件交易网6b46a386cc22bcd126ff0cb0

元器件交易网6b46a386cc22bcd126ff0cb0

M95128, M95128-W, M95128-R Instructions

5.4 Write Status Register (WRSR)

The Write Status Register (WRSR) instruction allows new values to be written to the Status

Register. Before it can be accepted, a Write Enable (WREN) instruction must previously

have been executed. After the Write Enable (WREN) instruction has been decoded and

executed, the device sets the Write Enable Latch (WEL).

followed by the instruction code and the data byte on Serial Data Input (D).

The instruction sequence is shown in Figure8.

The Write Status Register (WRSR) instruction has no effect on b6, b5, b4, b1 and b0 of the

Status Register. b6, b5 and b4 are always read as 0.

the eighth bit of the data byte, and before the next rising edge of Serial Clock (C). Otherwise,

driven High, the self-timed Write Status Register cycle (whose duration is t W) is initiated.

While the Write Status Register cycle is in progress, the Status Register may still be read to

check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1

during the self-timed Write Status Register cycle, and is 0 when it is completed. When the

cycle is completed, the Write Enable Latch (WEL) is reset.

The Write Status Register (WRSR) instruction allows the user to change the values of the

Block Protect (BP1, BP0) bits, to define the size of the area that is to be treated as read-

only, as defined in Table4.

The Write Status Register (WRSR) instruction also allows the user to set or reset the Status

be put in the Hardware Protected Mode (HPM). The Write Status Register (WRSR)

instruction is not executed once the Hardware Protected Mode (HPM) is entered.

The contents of the Status Register Write Disable (SRWD) and Block Protect (BP1, BP0)

bits are frozen at their current values from just before the start of the execution of Write

Status Register (WRSR) instruction. The new, updated, values take effect at the moment of

completion of the execution of Write Status Register (WRSR) instruction.

17/41

Instructions M95128, M95128-W, M95128-R

18/41The protection features of the device are summarized in Table2.

When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial delivery state), it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two

●If Write Protect (W) is driven High, it is possible to write to the Status Register provided

that the Write Enable Latch (WEL) bit has previously been set by a Write Enable

(WREN) instruction.

●not possible to write to the Status Register even

if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. (Attempts to write to the Status Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area that are

software protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register, are also hardware protected against data modification.

Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be entered:

●by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W)

Low

●

(SRWD) bit.

The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write never be activated, and only the Software Protected Mode (SPM), using the Block Protect (BP1, BP0) bits of the Status Register, can be used.

Table 5.Protection modes

W Signal

SRWD

Bit

Mode

Write Protection of the

Status Register

Memory Content

Protected Area(1)

1.As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table5.

Unprotected Area(1) 10

Software

Protected

(SPM)

Status Register is

Writable (if the WREN

instruction has set the

WEL bit)

The values in the BP1

and BP0 bits can be

changed

Write Protected

Ready to accept Write

instructions 00

11

01

Hardware

Protected

(HPM)

Status Register is

Hardware write

protected

The values in the BP1

and BP0 bits cannot be

changed

Write Protected

Ready to accept Write

instructions

元器件交易网6b46a386cc22bcd126ff0cb0

元器件交易网6b46a386cc22bcd126ff0cb0

M95128, M95128-W, M95128-R Instructions

19/41

元器件交易网6b46a386cc22bcd126ff0cb0

Instructions M95128, M95128-W, M95128-R

5.5 Read from Memory Array (READ)

As shown in Figure9

Low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data

Input (D). The address is loaded into an internal address register, and the byte of data at

that address is shifted out, on Serial Data Output (Q).

incremented, and the byte of data at the new address is shifted out.

When the highest address is reached, the address counter rolls over to zero, allowing the

Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a

single READ instruction.

The first byte addressed can be any byte within any page.

The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.

1.The most significant address bits (b15, b14) are Don’t Care.

20/41

元器件交易网6b46a386cc22bcd126ff0cb0

M95128, M95128-W, M95128-R Instructions

5.6 Write to Memory Array (WRITE)

As shown in Figure10

Low. The bits of the instruction byte, address byte, and at least one data byte are then

shifted in, on Serial Data Input (D).

data. In the case of Figure10, this occurs after the eighth bit of the data byte has been

latched in, indicating that the instruction is being used to write a single byte. The self-timed

Write cycle starts, and continues for a period t WC (as specified in Table16 to T able19), at

the end of which the Write in Progress (WIP) bit is reset to 0.

Figure11, the next byte of input data is shifted in, so that more than a single byte, starting from the given address

towards the end of the same page, can be written in a single internal Write cycle.

Each time a new data byte is shifted in, the least significant bits of the internal address

counter are incremented. If the number of data bytes sent to the device exceeds the page

boundary, the internal address counter rolls over to the beginning of the page, and the

previous data there are overwritten with the incoming data. (The page size of these devices

is 64 bytes).

The instruction is not accepted, and is not executed, under the following conditions:

●if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable

instruction just before)

●if a Write cycle is already in progress

●if the device has not been deselected, by Chip Select (S) being driven High, at a byte

boundary (after the eighth bit, b0, of the last data byte that has been latched in)

●if the addressed page is in the region protected by the Block Protect (BP1 and BP0)

bits.

1.The most significant address bits (b15, b14) are Don’t Care.

21/41

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