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GS8640V18/32/36T-300/250/200/167

100-Pin TQFPCommercial TempIndustrial TempFeatures

operation

Single Cycle Deselect (SCD) operation 1.8 V +10%/–10% core power supply 1.8 V I/O supply

Internal input resistors on mode pins allow floating mode pins Default to Interleaved Pipeline mode

Internal self-timed write cycle

Automatic power-down for portable applications JEDEC-standard 100-lead TQFP package Pb-Free 100-lead TQFP package available

4M x 18, 2M x 32, 2M x 3672Mb Sync Burst SRAMs300 MHz–167 MHz

1.8 V VDD1.8 V I/O

Burst mode, subsequent burst addresses are generated counter may be configured to count in either linear or

Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by pin low places the RAM in Flow Through mode, causing high places the RAM in Pipeline mode, activating the rising-edge-triggered Data Output Register.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable writing all bytes at one time, regardless of the Byte Write control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS8640V18/32/36T operates on a 1.8 V power supply. All input are 1.8 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 1.8 V compatible.

Functional Description

Applications

The GS8640V18/32/36T is a 75,497,472-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. Controls

and power down control (ZZ) are asynchronous inputs. Burst

Parameter Synopsis

KQtCycle(x18)Curr (x32/x36)

KQtCycle(x18)Curr (x32/x36)

-3003.34805.5330

-2504.04106.5280

-2005.03507.5250

-1676.03058.0240

UnitnsmAnsmA

Pipeline3-1-1-1

Flow Through2-1-1-1

GS8640V18/32/36T-300/250/200/167

GS8640V18 100-Pin TQFP Pinout (Package T)

NCNCNCVDDQVSS NCNCDQBDQBVSS VDDQ DQBDQBFTVDD NCVSS DQBDQBVDDQ VSS DQBDQBDQPB

NCVSS VDDQ NCNCNC

10099989796959493929190898887868584838281180279378477576675774873972

4M x 181071Top View1170

12691368146715661665176418631962206121602259235824572556265527542853295230513132333435363738394041424344454647484950

AAE1

E2 NCNCBB

BA

E3

VDD

VSS

CKGWBWGADSCADSPADVAA

ANCNCVDDQVSSNCDQPADQADQAVSSVDDQDQADQAVSSNCVDDZZDQADQAVDDQVSSDQADQANCNCVSSVDDQNCNCNC

LBOAAAAA1

A0

AAVSS

VDD

AA A A A A A A A

GS8640V18/32/36T-300/250/200/167

GS8640V32 100-Pin TQFP Pinout (Package T)

NCDQCDQCVDDQVSS DQCDQCDQCDQCVSS VDDQ DQCDQCFTVDD NCVSS DQDDQDVDDQ VSS DQDDQDDQDDQDVSS VDDQ DQDDQDNC

10099989796959493929190898887868584838281180279378477576675774873972

2M x 321071Top View1170

12691368146715661665176418631962206121602259235824572556265527542853295230513132333435363738394041424344454647484950

AAE1

E2 BD

BC

BB

BA

E3

VDD

VSS

CKGWBWGADSCADSPADVAA

NCDQBDQBVDDQVSSDQBDQBDQBDQBVSSVDDQDQBDQBVSSNCVDDZZDQADQAVDDQVSSDQADQADQADQAVSSVDDQDQADQANC

LBOAAAAA1

A0

AAVSS

VDD

A A A A A A A A A

GS8640V18/32/36T-300/250/200/167

GS8640V36 100-Pin TQFP Pinout (Package T)

DQPCDQCDQCVDDQVSS DQCDQCDQCDQC3VSS VDDQ DQCDQCVDD NCVSS DQDDQDVDDQ VSS DQDDQDDQDDQDVSS VDDQ DQDDQDDQPD

10099989796959493929190898887868584838281180279378477576675774873972

2M x 361071Top View1170

12691368146715661665176418631962206121602259235824572556265527542853295230513132333435363738394041424344454647484950

AAE1

E2 BD

BC

BB

BA

E3

VDD

VSS

CKGWBWGADSCADSPADVAA

DQPBDQBDQBVDDQVSSDQBDQBDQBDQBVSSVDDQDQBDQBVSSNCVDDZZDQADQAVDDQVSSDQADQADQADQAVSSVDDQDQADQADQPA

LBOAAAAA1

A0

AAVSS

VDD

A A A A A A A A A

GS8640V18/32/36T-300/250/200/167

TQFP Pin Description

Symbol

A0, A1ADQADQBDQCDQDNCBWBA, BBBC, BDCKGWE1, E3E2GADVADSP, ADSC

ZZFTLBOVDDVSSVDDQ

IIIIIIIIIIIIIIII

Type

III/O

Description

Address field LSBs and Address Counter preset Inputs

Address InputsData Input and Output pins

No Connect

ByteWrite—Writes all enabled bytes; active lowByte Write Enable for DQA, DQB Data I/Os; active lowByte Write Enable for DQC, DQD Data I/Os; active low

Clock Input Signal; active high

Global Write Enable—Writes all bytes; active low

Chip Enable; active low

Chip Enable; active highOutput Enable; active low

Burst address counter advance enable; active lowAddress Strobe (Processor, Cache Controller); active low

Sleep Mode control; active highFlow Through or Pipeline mode; active lowLinear Burst Order mode; active low

Core power supplyI/O and Core GroundOutput driver power supply

GS8640V18/32/36T-300/250/200/167

GS8640V18/32/36 Block Diagram

Register

A0–An

DQ

A0

D0

A1

Q0

D1Q1CounterLoad

A

LBOADVCKADSCADSPGWBWBA

Register

MemoryArray

Q

D

Q

D

Register

D

BB

Q

36

4

36

Register

D

BC

Q

Q

Register

D

Register

Q

Register

D

D

BD

Q

Register

DQ

E1E2E3

Register

DQ

Register

DQ

FTG

Power DownControl

DQx1–DQx9

ZZ

Note: Only x36 version shown for simplicity.

GS8640V18/32/36T-300/250/200/167

Mode Pin Functions

Mode Name

Burst Order ControlOutput Register ControlPower Down Control

Pin Name

LBOFTZZ

State

LHLH or NCL or NCH

Function

Linear BurstInterleaved BurstFlow ThroughPipelineActiveStandby, IDD = ISB

Note:

There is a pull-up device on the FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables.Burst Counter Sequences

Linear Burst Sequence

A[1:0]A[1:0]A[1:0]A[1:0]

1st address2nd address3rd address4th address

00011011

01101100

10110001

11000110

Interleaved Burst Sequence

A[1:0]A[1:0]A[1:0]A[1:0]

1st address2nd address3rd address4th address

00011011

01001110

10110001

11100100

Note:

The burst counter wraps to initial state on the 5th clock.Note:

The burst counter wraps to initial state on the 5th clock.

BPR 1999.05.18

GS8640V18/32/36T-300/250/200/167

Byte Write Truth Table

Function

ReadReadWrite byte aWrite byte bWrite byte cWrite byte dWriteallbytes

GW

HHHHHHH

BW

HLLLLLL

BA

XHLHHHL

BB

XHHLHHL

BC

XHHHLHL

BD

XHHHHLL

Notes

112, 32, 32, 3, 42, 3, 42,3,4

WriteallbytesLXXXXX 1.All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.

2.Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.3.All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.4.Bytes “C” and “D” are only available on the x32 and x36 versions.

GS8640V18/32/36T-300/250/200/167

Synchronous Truth Table

Operation

Deselect Cycle, Power DownDeselect Cycle, Power DownDeselect Cycle, Power DownRead Cycle, Begin BurstRead Cycle, Begin BurstWrite Cycle, Begin BurstRead Cycle, Continue BurstRead Cycle, Continue BurstWrite Cycle, Continue BurstWrite Cycle, Continue BurstRead Cycle, Suspend BurstRead Cycle, Suspend BurstWrite Cycle, Suspend Burst

Address Used

NoneNoneNoneExternalExternalExternalNextNextNextNextCurrentCurrentCurrent

StateDiagramKey5

XXXRRWCRCRCWCW

E1

HLLLLLXHXHXHX

E2

XFFTTTXXXXXXX

ADSPADSC

XLHLHHHXHXHXH

LXLXLLHHHHHHH

ADV

XXXXXXLLLLHHH

WXXXXFTFFTTFFT

DQ4

High-ZHigh-ZHigh-ZQQDQQDDQQD

Write Cycle, Suspend BurstCurrentHXXHHTD1.X = Don’t Care, H = High, L = Low

2.E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1

3.W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.

4.G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown

as “Q” in the Truth Table above).

5.All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish

basic synchronous or synchronous burst operations and may be avoided for simplicity.

6.Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.

7.Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.

GS8640V18/32/36T-300/250/200/167

Simplified State Diagram

X

DeselectW

R

W

Simple Synchronous Operation

R

XCW

First Write

RCR

First Read

CR

Simple Burst Synchronous Operation

W

R

Burst Write

CRCW

R

Burst Read

CR

Notes:

1.The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.

2.The upper portion of the diagram assumes active use of only the Enable (E1) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and

that ADSP is tied high and ADSC is tied low.

3.The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and

assumes ADSP is tied high and ADV is tied low.

GS8640V18/32/36T-300/250/200/167

Simplified State Diagram with G

X

DeselectW

R

W

X

WCW

R

First Write

RCR

First Read

CR

CW

X

RCR

WBurst Write

Burst Read

CWCR

Notes:

1.The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.

e of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing

through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.

3.Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet

Data Input Set Up Time.

GS8640V18/32/36T-300/250/200/167

Absolute Maximum Ratings

(All voltages reference to VSS)

Symbol

VDDVDDQVI/OVINIINIOUTPDTSTGTBIAS

Note:

Description

Voltage on VDD PinsVoltage in VDDQ PinsVoltage on I/O PinsVoltage on Other Input PinsInput Current on Any PinOutput Current on Any I/O PinPackage Power Dissipation Storage TemperatureTemperature Under Bias

Value

–0.5 to 3.6–0.5 to 3.6

–0.5 to VDDQ +0.5 (≤ 3.6 V max.)–0.5 to VDD +0.5 (≤ 3.6 V max.)

+/–20+/–201.5–55 to 125–55 to 125

Unit

VVVVmAmAW

oCoC

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.

Power Supply Voltage Ranges

Parameter

1.8 V Supply Voltage1.8 V VDDQ I/O Supply Voltage

Symbol

VDD1VDDQ1

Min.

1.61.6

Typ.

1.81.8

Max.

2.02.0

Unit

VV

Notes

Notes:

1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.

2.Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC.

GS8640V18/32/36T-300/250/200/167

Logic Levels

Parameter

VDD Input High VoltageVDD Input Low VoltageVDDQ I/O Input High VoltageVDDQ I/O Input Low Voltage

Symbol

VIHVILVIHQVILQ

Min.

0.6*VDD–0.30.6*VDD–0.3

Typ.

————

Max.

VDD + 0.30.3*VDDVDDQ + 0.30.3*VDD

Unit

VVVV

Notes

111,31,3

Notes:

1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.

2.Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC.3.VIHQ (max) is voltage on VDDQ pins plus 0.3 V.

Undershoot Measurement and Timing

VIH

VDD + 2.0 V

VSS50%VSS – 2.0 V

20% tKC

VIL50%VDD

Overshoot Measurement and Timing

20% tKC

Capacitance

(TA = 25oC, f = 1 MHZ, VDD = 2.5 V)

Parameter

Input CapacitanceInput/Output CapacitanceNote:

These parameters are sample tested.

Symbol

CINCI/O

Test conditions

VIN = 0 VVOUT = 0 V

Typ.

46

Max.

57

Unit

pFpF

GS8640V18/32/36T-300/250/200/167

AC Test Conditions

Parameter

Input high levelInput low levelInput slew rateInput reference levelOutput reference level

Output load

Conditions

VDD – 0.2 V0.2 V1 V/nsVDD/2VDDQ/2Fig. 1

1.Include scope and jig capacitance.

2.Test conditions as specified with output loading as shown in Fig. 1

unless otherwise noted.

3.Device is deselected as defined by the Truth Table.

Output Load 1

DQ

50 VDDQ/2

* Distributed Test Jig Capacitance

30pF*

DC Electrical Characteristics

Parameter

Input Leakage Current(except mode pins)ZZ Input CurrentFT Input CurrentOutput Leakage CurrentOutput High VoltageOutput Low Voltage

Symbol

IILIIN1IIN2IOLVOH1VOL1

Test Conditions

VIN = 0 to VDDVDD ≥ VIN ≥ VIH0 V ≤ VIN ≤ VIHVDD ≥ VIN ≥ VIL0 V ≤ VIN ≤ VIL

Output Disable, VOUT = 0 to VDDIOH = –4 mA, VDDQ = 1.6 VIOL = 4 mA, VDD = 1.6 V

Min

–1 uA–1 uA–1 uA–100 uA–1 uA–1 uAVDDQ – 0.4 V

—

Max

1 uA1 uA100 uA1 uA1 uA1 uA—0.4 V

GS8640V18/32/36T-300/250/200/167

Operating Currents

-300

Parameter

Test Conditions

Mode

Symbol

0to 70°C42060300303703027015100100150135

–40 to 85°C44060320303903029015120120165150

-2500to 70°C36050255253152523015100100140125

–40 to 85°C38050275253352525015120120155140

-2000to 70°C31040230202702020515100100130120

–40to 85°C33040250202902022515120120146135

-1670 to 70°C27035220202402019515100100125120

–40to 85°C29035240202602021515120120140135

Unit

OperatingCurrent

Device Selected; All other inputs ≥VIH or ≤ VILOutput open

(x32/x36)

PipelineFlow ThroughPipeline

DDIDDQIDDIDDQIDDIDDQIDDIDDQISBISBIDDIDD

mAmAmAmAmAmAmAmA

(x18)

Flow ThroughPipeline

StandbyCurrentDeselectCurrent

ZZ ≥ VDD – 0.2 VDevice Deselected; All other inputs ≥ VIH or ≤ VIL

—

Flow ThroughPipelineFlow Through

—

Notes:

1.IDD and IDDQ apply to any combination of VDD and VDDQ operation.2.All parameters listed are worst case scenario.

GS8640V18/32/36T-300/250/200/167

AC Electrical Characteristics

ParameterClock Cycle TimeClock to Output Valid

Pipeline

Clock to Output InvalidClock to Output in Low-Z

Setup timeHold timeClock Cycle TimeClock to Output Valid

Flow Through

Clock to Output InvalidClock to Output in Low-Z

Setup timeHold timeClock HIGH TimeClock LOW TimeClock to Output in

High-ZG to Output ValidG to output in Low-ZG to output in High-ZZZ setup timeZZ hold timeZZ recovery

SymboltKCtKQtKQXtLZ1tStHtKCtKQtKQXtLZ1tStHtKHtKLtHZ1tOEtOLZ1tOHZ1tZZS2tZZH2tZZR

-300Min3.3—1.51.51.10.15.5—3.03.01.50.51.01.2

Max—2.3—————5.5——————

4.0—1.51.51.20.26.5—3.03.01.50.51.31.5-250Min

Max—2.5—————6.5——————

5.0—1.51.51.40.47.5—3.03.01.50.51.31.5-200Min

Max—3.0—————7.5——————

6.0—1.51.51.50.58.0—3.03.01.50.51.31.51.5—0—5120-167Min

Max—3.5—————8.0——————3.03.5—3.0———

Unitnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns

—0—5120

2.3—2.3———

—0—5120

2.5—2.5———

—0—5120

3.0—3.0———

Notes:

1.These parameters are sampled and are not 100% tested.

2.ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold

times as specified above.

GS8640V18/32/36T-300/250/200/167

Pipeline Mode Timing (SCD)

BeginRead AContContDeselectWrite BtKLtKHtKC

Read CRead C+1Cont

Deselect

CKADSP

tS

tH

ADSC

tS

ADV

tS

tH

A0–An

A

B

C

tH

tS

GW

tS

BW

tH

tS

Ba–Bd

tS

tH

E1

tS

tH

E2

tS

tH

E3G

tS

tOE

DQa–DQd

tOHZ

Q(A)

D(B)

tH

tKQ

tH

Q(C)

Q(C+1)

Q(C+2)

GS8640V18/32/36T-300/250/200/167

Flow Through Mode Timing (SCD)

BeginRead ACont

tKLtKH

ConttKC

Write BRead CRead C+1Read CContDeselect

CKADSP

tStH

ADSC

tStH

ADV

tStH

A0–An

A

B

C

tStHtS

tH

GW

tStH

BW

tStH

Ba–Bd

tS

tH

E1

tStH

E2

tStH

E3G

tHtS

tOE

DQa–DQd

Q(A)

tKQtLZ

Q(C)

Q(C+1)

Q(C+2)

Q(C+3)

Q(C)

tHZ

GS8640V18/32/36T-300/250/200/167

Sleep Mode

During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after 2 cycles of wake up time.

Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode.

Sleep Mode Timing Diagram

tKH

tKC

CK

SetupHold

ADSPADSC

tZZR

tZZS

ZZ

tZZH

tKL

GS8640V18/32/36T-300/250/200/167

TQFP Package Drawing (Package T)

L

Description

StandoffBody ThicknessLead WidthLead ThicknessTerminal DimensionPackage BodyTerminal DimensionPackage BodyLead PitchFoot LengthLead LengthCoplanarityLead Angle

0°

—

c

Symbol

A1A2bcDD1EE1eLL1Yθ

Min.Nom.Max

0.051.350.200.0921.919.915.913.9—0.45—

0.101.400.30—22.020.016.014.00.650.601.00

0.151.450.400.2022.120.116.114.1—0.75—0.10

L1

eb

DD1

A1

E1E

7°

Notes:

1.All dimensions are in millimeters (mm).

2.Package width and length do not include mold protrusion.

GS8640V18/32/36T-300/250/200/167

Ordering Information for GSI Synchronous Burst RAMs Org

4M x 184M x 184M x 184M x 182M x 322M x 322M x 322M x 322M x 362M x 362M x 362M x 364M x 184M x 184M x 184M x 182M x 322M x 322M x 322M x 322M x 362M x 362M x 362M x 364M x 184M x 184M x 182M x 32

Part Number

1

Type

Pipeline/Flow ThroughPipeline/Flow ThroughPipeline/Flow ThroughPipeline/Flow ThroughPipeline/Flow ThroughPipeline/Flow ThroughPipeline/Flow ThroughPipeline/Flow ThroughPipeline/Flow ThroughPipeline/Flow ThroughPipeline/Flow ThroughPipeline/Flow ThroughPipeline/Flow ThroughPipeline/Flow ThroughPipeline/Flow ThroughPipeline/Flow ThroughPipeline/Flow ThroughPipeline/Flow ThroughPipeline/Flow ThroughPipeline/Flow ThroughPipeline/Flow ThroughPipeline/Flow ThroughPipeline/Flow ThroughPipeline/Flow ThroughPipeline/Flow ThroughPipeline/Flow ThroughPipeline/Flow ThroughPipeline/Flow Through

Package

TQFPTQFPTQFPTQFPTQFPTQFPTQFPTQFPTQFPTQFPTQFPTQFPTQFPTQFPTQFPTQFPTQFPTQFPTQFPTQFPTQFPTQFPTQFPTQFPPb-Free TQFPPb-Free TQFPPb-Free TQFPPb-Free TQFP

Speed2(MHz/ns)

300/5.5250/6.5200/7.5167/8300/5.5250/6.5200/7.5167/8300/5.5250/6.5200/7.5167/8300/5.5250/6.5200/7.5167/8300/5.5250/6.5200/7.5167/8300/5.5250/6.5200/7.5167/8250/6.5200/7.5167/8300/5.5

TA3

CCCCCCCCCCCCIIIIIIIIIIIICCCC

Status

GS8640V18T-300GS8640V18T-250GS8640V18T-200GS8640V18T-167GS8640V32T-300GS8640V32T-250GS8640V32T-200GS8640V32T-167GS8640V36T-300GS8640V36T-250GS8640V36T-200GS8640V36T-167GS8640V18T-300IGS8640V18T-250IGS8640V18T-200IGS8640V18T-167IGS8640V32T-300IGS8640V32T-250IGS8640V32T-200IGS8640V32T-167IGS8640V36T-300IGS8640V36T-250IGS8640V36T-200IGS8640V36T-167IGS8640V18GT-250GS8640V18GT-200GS8640V18GT-167GS8640V32GT-300

2M x 32GS8640V32GT-250Pipeline/Flow ThroughPb-Free TQFP250/6.5C1.Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8640V18T-300IT.2.The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each

device is Pipeline/Flow Through mode-selectable by the user.

3.TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are

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