INTEL CPU供电设计指南,V11规范,PCB设计参考

Voltage Regulator-Down (VRD) 11.1 Processor Power Delivery Design Guidelines

September 2009

Document Number: 322172-001

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2 Processor Power Delivery Design Guidelines

Contents

1VRD 11.1 Common Information (11)

1.1Applications (11)

1.2Terminology (12)

1.3Processor V CC Requirements (14)

1.3.1Voltage and Current (REQUIRED) (14)

1.3.2Loadline Definitions (REQUIRED) (14)

1.3.3VRD Output Filter (REQUIRED) (16)

1.3.4TOB — Voltage Tolerance Band (REQUIRED) (18)

1.3.5Stability (REQUIRED) (20)

1.3.6Dynamic Voltage Identification (REQUIRED) (20)

1.3.7Processor V CC Overshoot (REQUIRED) (25)

1.3.8Example: Socket V CC Overshoot Test (28)

1.4Power Sequencing (REQUIRED) (29)

1.4.1VR_ENABLE (29)

1.4.2Vboot Voltage Level (REQUIRED) (29)

1.4.3Under Voltage Lock Out (UVLO) (REQUIRED) (29)

1.4.4Soft Start (SS) (REQUIRED) (30)

1.4.5Power-off Timing Sequence (REQUIRED) (30)

1.5VRD Current Support (Required) (33)

1.5.1Phase Count Requirement (33)

1.6Control Inputs to VRD (34)

1.6.1Voltage Identification (VID [7:0]) (REQUIRED) (34)

1.6.2Differential Remote Sense Input (REQUIRED) (38)

1.6.3Power State Indicator (PSI#) (Required) (39)

1.7Input Voltage and Current (39)

1.7.1Input Voltages (EXPECTED) (39)

1.8Output Protection (41)

1.8.1Over-Voltage Protection (OVP) (PROPOSED) (41)

1.8.2Over-Current Protection (OCP) (PROPOSED) (41)

1.9Output Indicators (42)

1.9.1VR_READY — V CC Regulator Is ‘ON’ (REQUIRED) (42)

1.9.2Load Current Signal (Iout) (REQUIRED) (43)

1.9.3Thermal Monitoring (44)

2LGA1366 Information (47)

2.1Introduction (47)

2.1.1Applications (47)

2.2Processor V CC Requirements (47)

2.2.1Loadline Definitions (REQUIRED) (47)

2.3V TT Requirements (REQUIRED) (53)

2.3.1Electrical Specifications (53)

2.4LGA 1366 Specific Signals (56)

2.4.1Power-on Configuration (POC) Signals on VID (REQUIRED) (56)

2.5MB Power Plane Layout (REQUIRED) (57)

2.5.1Minimize Power Path DC Resistance (57)

2.5.2Minimize Power Delivery Inductance (57)

2.5.3Six-Layer Boards (57)

Processor Power Delivery Design Guidelines 3

2.5.4Resonance Suppression (64)

2.6Electrical Simulation (EXPECTED) (65)

2.7LGA1366 Voltage Regulator Configuration Parameters (76)

2.7.11366_VR_CONFIG_08B (76)

3LGA775 Information (77)

3.1Introduction (77)

3.2Processor V CC Requirements (77)

3.2.1Socket Loadline Definitions (REQUIRED) (77)

3.3PSI# Operation (90)

3.4V TT Requirements (REQUIRED) (91)

3.4.1Electrical Specifications (91)

3.5MB Power Plane Layout (REQUIRED) (92)

3.5.1Minimize Power Path DC Resistance (92)

3.5.2Minimize Power Delivery Inductance (92)

3.5.3Four-Layer Boards (92)

3.5.4Six-Layer Boards (96)

3.5.5Resonance Suppression (96)

3.6Electrical Simulation (EXPECTED) (97)

3.7LGA775 Voltage Regulator Configuration Parameters (106)

3.7.1775_VR_CONFIG_04A (106)

3.7.2775_VR_CONFIG_04B (107)

3.7.3775_VR_CONFIG_05A (107)

3.7.4775_VR_CONFIG_05B (108)

3.7.5775_VR_CONFIG_06 (108)

4LGA1156 Information (109)

4.1Introduction (109)

4.1.1Applications (109)

4.2Processor V CC Requirements (109)

4.2.1Loadline Definitions (REQUIRED) (109)

4.3LGA 1156 Specific Signals (114)

4.3.1Power-on Configuration (POC) Signals on VID (REQUIRED) (114)

4.4MB Power Plane Layout (REQUIRED) (114)

4.4.1Minimize Power Path DC Resistance (114)

4.4.2Minimize Power Delivery Inductance (115)

4.4.3Four-Layer Boards (115)

4.4.4Six-layer Boards (118)

4.4.5Resonance Suppression (118)

4.5Electrical Simulation (EXPECTED) (119)

4.6LGA1156 Voltage Regulator Configuration Parameters (127)

Appendix A Z(f) Impedance References (129)

Appendix B Audible Noise Reduction (131)

4 Processor Power Delivery Design Guidelines

Figures

Figure 1-1. Examples of High Volume Manufacturing Loadline Violations (16)

Figure 1-2. High Volume Manufacturing Compliant Loadline (16)

Figure 1-3. Processor D-VID Loadline Transition States (21)

Figure 1-4. VRD11.1 D-VID Transition Timing States (6.25 mV VID Resolution) (23)

Figure 1-5. Overshoot and Undershoot During Dynamic VID Validation (23)

Figure 1-6. VRD11 DVID Transition Timing States (12.5 mV VID Resolution) (24)

Figure 1-7 Overshoot and Undershoot during Dynamic VID Validation (25)

Figure 1-8. Graphical Representation of Overshoot Parameters (27)

Figure 1-9. Processor Overshoot in High Volume Manufacturing (27)

Figure 1-10. Example V CC Overshoot Waveform (28)

Figure 1-11. Start Up Sequence (Timing is not to scale, details in Table 1-7) (30)

Figure 1-12 Power-off timing sequence (Timing is not to scale, details in Table 1-7) . 31

Figure 1-13. TD7 Reference Levels (31)

Figure 1-14. Start Up Sequence Functional Block Diagram (32)

Figure 1-15. D-VID Bus Topology (34)

Figure 1-16. PROCHOT# Load External to Processor (45)

Figure 2-1. Loadline Window for 1366_VR_CONFIG_08B (49)

Figure 2-2. 200 Hz, 100 A Step Droop Waveform (51)

Figure 2-3. 250 kHz, 100 A Step Waveform (51)

Figure 2-4. Power Distribution Impedance versus Frequency (52)

Figure 2-5. Window for V TT Voltage on LGA1366 Platforms (54)

Figure 2-6. Reference Board Layer Stack-up (58)

Figure 2-7. Layer 1 V CC Shape for Intel? Reference Six-layer Motherboard (59)

Figure 2-8. Layer 2 V SS Routing for Intel? Reference Six-layer Motherboard (60)

Figure 2-9. Layer 3 V CC Routing for Intel? Reference Six-layer Motherboard (61)

Figure 2-10. Layer 4 V CC Shape for Intel? Reference Six-layer Motherboard (62)

Figure 2-11. Layer 5 V SS Shape for Intel? Reference Six-layer Motherboard (63)

Figure 2-12. Layer 6 V CC Shape for Intel? Reference Six-layer Motherboard (64)

Figure 2-13. Simplified Reference Block Diagram (65)

Figure 2-14. Example Voltage Droop Observed At Node ‘Sense’ (67)

Figure 2-15. Current Step Observed Through I_PWL (68)

Figure 2-16. Schematic Diagram for the Six-Layer Intel? Reference Motherboard (69)

Figure 2-17. Node Location for the Schematic of Figure 2-16 (70)

Figure 2-18. Schematic Representation of Bulk Decoupling Capacitors (71)

Figure 2-19. Schematic Representation of Mid-frequency Decoupling Capacitors (72)

Figure 2-20. Schematic Representation of Socket Model (74)

Figure 2-21. Current Load Step Profile for I_PWL (75)

Figure 3-1. Socket Loadline Window for 775_VR_CONFIG_04A (79)

Figure 3-2. Piece-wise Linear Socket Loadline (80)

Figure 3-3. Socket Loadline Window for 775_VR_CONFIG_04B, 05A, 05B

(0–100 kHz loadstep rate) (81)

Figure 3-4. Socket Loadline Window for 775_VR_CONFIG_04B, 05A, 05B

(>100 kHz–1 MHz loadstep Rate) (82)

Figure 3-5. Socket Loadline Window for Design Configurations 775_VR_CONFIG_06 (0–100 kHz Loadstep Rate) (83)

Figure 3-6. Socket Loadline Window for Design Configurations 775_VR_CONFIG_06 (>100 kHz-1 MHz Loadstep Rate) (84)

Figure 3-7. VRD Phase Orientation (85)

Processor Power Delivery Design Guidelines 5

Figure 3-8. Examples of High Volume Manufacturing Loadline Violations (86)

Figure 3-9. High Volume Manufacturing Compliant Loadline (87)

Figure 3-10. 200 Hz, 100 A Step Droop Waveform (88)

Figure 3-11. 250 kHz, 100 A Step Waveform (88)

Figure 3-12. Power Distribution Impedance versus Frequency (89)

Figure 3-13. Reference Board Layer Stack-up (93)

Figure 3-14. Layer 1 V CC Shape for Intel? Reference Four-layer Motherboard (94)

Figure 3-15. Layer 2 V SS Routing for Intel? Reference Four-layer Motherboard (95)

Figure 3-16. Layer 3 V SS Routing for Intel? Reference Four-layer Motherboard (95)

Figure 3-17. Layer 4 V CC Shape for Intel? Reference Four-layer Motherboard (96)

Figure 3-18. Simplified Reference Block Diagram (97)

Figure 3-19. Example Voltage Droop Observed At Node ‘N2’ (99)

Figure 3-20. Current Step Observed Through I_PWL (100)

Figure 3-21. Schematic Diagram for the Four-layer Intel? Reference Motherboard .. 101

Figure 3-22. Node Location for the Schematic of Figure 3-21 (102)

Figure 3-23. Schematic Representation of Decoupling Capacitors (103)

Figure 3-24. Schematic Representation of Decoupling Capacitors (104)

Figure 3-25. Current Load Step Profile for I_PWL (105)

Figure 4-1. Loadline Window for 1156_VR_CONFIG_09B (110)

Figure 4-2. Power Distribution Impedance versus Frequency (113)

Figure 4-3. Reference Board Layer Stack-up (115)

Figure 4-4. Layer 1 V CC Shape for Intel? Reference Four-layer Motherboard (116)

Figure 4-5. Layer 2 V SS Routing for Intel? Reference Four-layer Motherboard (117)

Figure 4-6. Layer 3 V SS Routing for Intel? Reference Four-layer Motherboard (117)

Figure 4-7. Layer 4 V CC Shape for Intel? Reference Four-layer Motherboard (118)

Figure 4-8. Simplified Reference Block Diagram (119)

Figure 4-9. Example Voltage Droop Observed At Node ‘Sense’ (121)

Figure 4-10. Current Step Observed Through I_PWL (121)

Figure 4-11. Schematic Diagram for the Four-layer Intel? Reference Motherboard .. 122

Figure 4-12. Node Location for the Schematic of Figure 4-11 (123)

Figure 4-13. Schematic Representation of Mid-frequency Decoupling Capacitors (123)

Figure 4-14. Schematic Representation of VR Test Tool Model (125)

Figure 4-15. Current Load Step Profile for I_PWL (126)

Figure 4-16. Effect of Output Change on Input Currents (132)

Figure 4-17 Input Voltage Drop Caused by di/dt Event at the Output (132)

6 Processor Power Delivery Design Guidelines

Tables

Table 1-1. Feature Support Terminology (12)

Table 1-2. Glossary (12)

Table 1-3. Loadline Equations (15)

Table 1-4. V CC Overshoot Terminology Table (25)

Table 1-5. V CC Overshoot Specifications (25)

Table 1-6. Intel? Processor Current Release Values For Overshoot Testing (26)

Table 1-7. Start Up Sequence Timing (32)

Table 1-8. Interface Signal Parameters (35)

Table 1-9. VR11.1 VID Table (Same as VR11.0 VID Table) (36)

Table 1-10. 1366_VR Efficiency Guidelines (40)

Table 1-11. LGA1156_VR Efficiency Guidelines (40)

Table 1-12. LGA775_VR Efficiency Guidelines (40)

Table 1-13. VR_Ready output signal Specifications (42)

Table 1-14. Iout Analog Output Requirements (43)

Table 1-15. Iout Gain and POC Settings (43)

Table 1-16. Iout Accuracy Requirements (44)

Table 1-17. Thermal Monitor Specifications (45)

Table 2-1. Loadline Equations (48)

Table 2-2. V CC Regulator Design Parameters (48)

Table 2-3. Loadline Window for 1366_VR_CONFIG_08B (49)

Table 2-4. Loadline Reference Lands for the LGA1366 Socket (50)

Table 2-5. Intel? Processor Current Step Values for Transient Loadline Testing (50)

Table 2-6. Impedance Measurement Parameters (53)

Table 2-7. Window for V TT Voltage on LGA1366 Platforms (54)

Table 2-8 V TT Parameters (55)

Table 2-9. V TT Measurement Lands (55)

Table 2-10. V TT VID Lands (55)

Table 2-11. V TT VID Voltage (56)

Table 2-12. Reference Board Layer Thickness (Prepreg 1080) (58)

Table 2-13. Parameter Values for the Schematic of Figure 2-16 (69)

Table 2-14. Recommended Parameter Values for the Capacitors Models (73)

Table 2-15. Recommended Parameter Values for the Socket Model in Figure 2-20 (74)

Table 2-16. I_PWL Current Parameters for Figure 2-21 (75)

Table 2-17. 1366_VR_CONFIG_08B Specification Input Parameters (76)

Table 3-1. Socket Loadline Equations (77)

Table 3-2. V CC Regulator Design Parameters (78)

Table 3-3. Socket Loadline Window for 775_VR_CONFIG_04A (79)

Table 3-4. Socket Loadline Window for 775_VR_CONFIG_04B, 05A, 05B

(0–100 kHz loadstep rate) (81)

Table 3-5. Socket Loadline Window for 775_VR_CONFIG_04B, 05A, 05B

(>100 kHz-1 MHz loadstep Rate) (82)

Table 3-6. Socket Loadline Window for 775_VR_CONFIG_06

(0–100 kHz Loadstep Rate) (83)

Table 3-7. Socket Loadline Window for 775_VR_CONFIG_06

(>100 kHz–1 MHz Loadstep Rate) (84)

Table 3-8. Socket Loadline Reference Lands (85)

Table 3-9. Intel? Processor Current Step Values for Transient Socket loadline

Testing (85)

Processor Power Delivery Design Guidelines7

Table 3-10. Impedance Measurement Parameters (90)

Table 3-11. V TT Specifications (91)

Table 3-12. V TT Measurement Lands (91)

Table 3-13. Reference Board Layer Thickness (Prepreg 1080) (93)

Table 3-14. Parameter Values for the Schematic of Figure 3-21 (101)

Table 3-15. Recommended Parameter Values for the Capacitors Models

in Figure 3-23 (103)

Table 3-16 Recommended Parameter Values for the Capacitor Models

in Figure 3-23 (104)

Table 3-17. I_PWL Current Parameters for Figure 3-25 (105)

Table 3-18. 775_VR_CONFIG_04A Specification Input Parameters (106)

Table 3-19. 775_VR_CONFIG_04B Specification Input Parameters (107)

Table 3-20. 775_VR_CONFIG_05A Specification Input Parameters (107)

Table 3-21. 775_VR_CONFIG_05B Specification Input Parameters (108)

Table 3-22. 775_VR_CONFIG_06 Specification Input Parameters (108)

Table 4-1. Loadline Equations (109)

Table 4-2. V CC Regulator Design Parameters (110)

Table 4-3. Loadline Window for 1156_VR_CONFIG_09B (111)

Table 4-4. Loadline Reference Lands for the LGA1156 Socket (111)

Table 4-5. Intel? Processor Current Step Values for Transient Loadline Testing (111)

Table 4-6. Impedance Measurement Parameters (113)

Table 4-7. Reference Board Layer Thickness (Prepreg 1080) (116)

Table 4-8. Parameter Values for the Schematic of Figure 4-11 (122)

Table 4-9. Recommended Parameter Values for the Capacitors Models (124)

Table 4-10. Recommended Parameter Values for the Socket Model in Figure 4-14 .. 125

Table 4-11. I_PWL Current Parameters for Figure 4-15 (126)

Table 4-12. 1156_VR_CONFIG_09A Specification Input Parameters (127)

Table 4-13. 1156_VR_CONFIG_09B Specification Input Parameters (127)

8 Processor Power Delivery Design Guidelines

Revision History

§

Processor Power Delivery Design Guidelines9

10 Processor Power Delivery Design Guidelines

VRD 11.1 Common Information

Processor Power Delivery Design Guidelines 11 1 VRD 11.1 Common Information

This chapter contains information common to all platforms implementing VRD 11.1.

Chapters 2 and beyond contain VRD11.1 information unique to a given platform. Refer

to both chapters 1 and the appropriate follow-on chapter relevant to the platform

under design.

1.1 Applications

This document defines the power delivery feature set necessary to support Intel

processor V CC power delivery requirements for desktop and UP server/workstation

computer systems using the LGA1366, LGA1156, and LGA775 sockets. This includes

design recommendations for DC to DC regulators, which convert the input supply

voltage to a processor consumable V CC voltage along with specific feature set

implementation such as thermal monitoring and dynamic voltage identification.

Hardware solutions for the V CC regulator are dependent upon the processors to be

supported by a specific motherboard. V CC regulator design on a specific board must

meet the specifications of all processors supported by that board. The voltage

regulator configuration for a given processor is defined in that processor datasheet. In

some instances, this data is not published and the proper mapping of processor to

VRD configuration can be found from an authorized Intel representative.

The voltage regulator-down (VRD) designation of this document refers to a regulator

with all components mounted directly on the motherboard for intent of supporting a

single processor.

VR11.1 incorporates all of the VR11 functions with the following changes:

? Iout feature to support LGA1366, and LGA1156 processors.

? Power on configuration (POC), market segment identification (MSID) functions multiplexed onto VID lines during start up.

? VID_SELECT, VR_FAN and VR10 VID support are removed.

? A Power State Indicator (PSI#) input has been added.

? Single step D-VID added for processor C-state entry and exit.

VRD 11.1 Common Information

12 Processor Power Delivery Design Guidelines 1.2 Terminology

Table 1-1. Feature Support Terminology

Table 1-2. Glossary

VRD 11.1 Common Information

Processor Power Delivery Design Guidelines13

VRD 11.1 Common Information 14 Processor Power Delivery Design Guidelines

1.3

Processor V CC Requirements 1.3.1 Voltage and Current (REQUIRED)

An 8-bit VID code supplied by the processor to the VRD determines a reference output voltage as described in Section 1.6.1. The loadlines described in subsequent parts of this document show the relationship between V CC and I CC for the processor.

Intel performs testing against multiple software applications and software test vectors to identify valid processor V CC operating ranges. Failure to satisfy the loadline, loadline tolerance band, and overshoot voltage specifications may invalidate Intel warranties and lead to premature processor failure, intermittent system lock-up, and/or data corruption.

1.3.2 Loadline Definitions (REQUIRED)

To maintain processor reliability and performance, platform DC voltage regulation and transient-droop noise levels must always be contained within the Vccmin and Vccmax loadline boundaries (known as the loadline window). Loadline compliance must be ensured across component manufacturing tolerances, thermal variation, and age

degradation. Loadline boundaries are defined by the following equations in conjunction with the V CC regulator design parameter values defined in the subsequent sections of this document. Loadline voltage tolerance is defined in Section 1.3.4. In these equations, VID, R LL , and TOB are known. Plotting V CC while varying I CC from 0 A to Iccmax establishes the Vccmax and Vccmin loadlines. Vccmax establishes the

maximum DC loadline boundary. Vccmin establishes the minimum AC and DC voltage

VRD 11.1 Common Information

Processor Power Delivery Design Guidelines 15 boundary. Short transient bursts above the Vccmax loadline are permitted; this condition is defined in Section 1.3.7.

Table

1-3. Loadline Equations

Loadline recommendations are established to provide guidance for satisfying

processor loadline specifications, which are defined in processor datasheets. Loadline requirements must be satisfied at all times and may require adjustment in the loadline value. The processor loadlines are defined in the applicable processor datasheet. VRD designs must be loadline compliant across the full tolerance band window to avoid data corruption, system lock-up, and reduced performance. When validating a system’s loadline, a single measurement is statistically insignificant and cannot

represent the response variation seen across the entire high volume manufacturing population of VRD designs. A typical loadline may fit in the specification window;

however, designs residing elsewhere in the tolerance band distribution may violate the specifications. Figure 1-1 Example A shows a loadline that is contained in the

specification window and, this single instance, complies with Vccmin and Vccmax

specifications. The positioning of this loadline will shift up and down as the tolerance drifts from typical to the design limits. Figure 1-1 Example B shows that Vccmax limits will be violated as the component tolerances shift the loadline to the upper tolerance

band limits. Figure

1-1 Example C shows that the Vccmin limits will be violated as the component tolerances shift the loadline to the lower tolerance band limits.

To satisfy specifications across high volume manufacturing variation, a typical loadline must be centered in the loadline window and have a slope equal to the value specified in the subsequent sections of this document that apply to the processor being used. Figure 1-2 Example A shows a loadline that meets this condition. Under full 3-σ tolerance band variation, the loadline slope will intercept the Vccmax loadline (Figure 1-2 Example B) or Vccmin loadline (Figure 1-2 Example C) limits.

VRD 11.1 Common Information 16 Processor Power Delivery Design Guidelines Figure 1-1. Examples of High Volume Manufacturing Loadline Violations

Figure 1-2. High Volume Manufacturing Compliant Loadline

1.3.3 VRD Output Filter (REQUIRED)

Desktop processor voltage regulators include an output filter consisting of large bulk decoupling capacitors to compensate for large transient voltage swings and small value ceramic capacitors to provide mid-frequency decoupling. This filter must be designed to stay within loadline specifications across tolerances due to age

degradation, manufacturing variation, and temperature drift.

The VRD output filter needs to be designed for the VR controller that is used. Different controllers can have different filter requirements for meeting the loadline

requirements.

VRD 11.1 Common Information

Processor Power Delivery Design Guidelines 17 1.3.3.1 Bulk Decoupling

Bulk decoupling is necessary to maintain V CC within loadline limits prior to the VRD

controller response. Design analysis shows that bulk decoupling requirements will vary with the number of VRD phases and the FET switching frequency.

The D-VID mode of operation is directly impacted by the choice of bulk capacitors and output inductor value in the VRD output filter. It is necessary to minimize V CC settling time during D-VID operation to hasten the speed of core power reduction. The speed of recovery is directly related to the RCL time constant of the output filter. To ensure an adequate thermal recovery time, it is recommended to design the output filter with a minimal output inductor value and a minimal amount of bulk capacitance with

minimum ESR, while providing a sufficient amount of decoupling to maintain loadline and ripple requirements. At this time, high-density aluminum poly capacitors with 5 m ? average ESR have been identified as the preferred solution. Failure to satisfy the V CC settling time requirements defined in Section 1.3.6 may invalidate processor thermal modes.

1.3.3.2 Mid-frequency Decoupling

The output filter includes mid-frequency decoupling to ensure ripple and package

noise is suppressed to specified levels. Ripple limits are defined in Section 1.3.4.4 and package noise limits are defined in appropriate processor datasheets in the form of a processor loadline.

High Mid-frequency noise and ripple suppression are best minimized by 10 μF, 22 μF, or 47 μF multi-layer ceramic capacitors (MLCCs). It is recommended to maximize the MLCC count in the socket cavity to help suppress transients induced by processor packaging hardware. Remaining MLCCs should be first placed adjacent to the socket edge in the region between the socket cavity and the voltage regulator.

Intel recommends a mid-frequency filter consisting of MLCCs distributed uniformly through the socket cavity region. The cavity-capacitor ESL value needs to be low enough to ensure the VR filter impedance is at or below the loadline target up to F break frequency as described in subsequent sections of this document relating to the processor the VR is being designed for. To ensure functionality with all Intel

processors, adoption of the reference solution accompanied by full processor loadline validation is strongly recommended.

Noise is directly dependent upon the processor core frequency, so the filter must ensure adequate decoupling to support all frequencies the board is to support. Impedance measurements as described in subsequent sections of this document relating to the processor the VR is being designed for will help the designer analyze the MLCC decoupling solution.

VRD 11.1 Common Information 18 Processor Power Delivery Design Guidelines 1.3.4

TOB — Voltage Tolerance Band (REQUIRED) Processor loadline specifications must be ensured across component process variation, system temperature extremes, and age degradation limits. The VRD topology and component selection must maintain a 3-σ tolerance of the VRD Tolerance Band around the typical loadline. The critical parameters include voltage ripple, VRD controller tolerance, and current sense tolerance under both static and transient conditions. Inpidual tolerance components will vary among designs; the processor requires only that the total error stack-up stay within the defined VR configuration tolerance band under the conditions defined in the subsequent sections of this document relating to the processor the VR is being designed for. 1.3.4.1

PWM Controller Requirements To ensure designers can satisfy the required VRD tolerance band across all modes of operation, PWM controller vendors must publish data and collateral that is critical for satisfying design requirements. This includes support of the following: ? The PWM vendor is to define equations for calculating the VRD TOB with Inductor DCR sensing and resistor sensing. The equation is to include all parameter dependencies such as AVP tolerance, age degradation, thermal drift, sense element DC and AC accuracy, etc under 3-σ variation. These equations are to be published in the PWM controller data sheet. The vendor is to distribute and support a tolerance band calculator that communicates the VRD TOB for each valid VID under each VID table. ? Total PWM controller DC set point accuracy is typically <0.5% over temperature, component age, and lot to lot variation over the 1.0–1.6 V VID range. DAC error may be larger for voltages below 1 V under the assumption that the required Vmin TOB requirements are always satisfied. Typical low voltage accuracy is ± 5 mV for 0.8 V – 1.0 V VID and ± 8 mV for 0.5–0.8 V VID. Each vendor is to publish PWM controller DAC accuracy by VID value in the component data sheet. ? The PWM controller must support voltage amplitudes read across sense elements with a DCR of 0.1–2.0 m ?. PWM controller vendors must define the minimum sense signal voltage necessary to satisfy PWM signal to noise ratio requirements. These requirements are to be published by the vendor in their PWM controller datasheet. 1.3.4.2

Loadline Thermal Compensation (REQUIRED) Thermal compensation allows the voltage regulator to respond to temperature drift in VRD electrical parameters. It is required to ensure that regulators using inductor current sensing maintain a stable voltage over the full range of load current and system temperatures. If thermal compensation is not included, the output voltage of the regulator will droop as the resistance of the sense element increases with temperature. With the increased resistance, the regulator falsely detects an increase in load current and regulates to a lower voltage. Thermal compensation prevents this thermally induced voltage droop by adjusting the feedback path based on the temperature of the regulator. This is accomplished by placing a thermistor in the feedback network, tuned with a resistor network to negate the effects of the increased resistance of the sense element.

VRD 11.1 Common Information

Processor Power Delivery Design Guidelines 19 The thermal compensation circuit is to be validated by running the regulator at the

Voltage Regulator Thermal Design Current (VRTDC) and minimum required air flow for 30 to 45 minutes. This is to ensure the board is thermally stable and system

temperatures have reached a maximum steady state condition. If the thermal compensation has been properly implemented, the output voltage will only drift

1–2 mV from its coolest temperature condition. If the thermal compensation has not been properly implemented, the voltage can droop in the tens of mV range.

1.3.4.3 Dynamic Voltage Identification (D-VID) TOB

During the D-VID (see Section 1.3.6) mode of operation, VRD tolerance band

requirements must be satisfied. Minimum voltage cannot fall below the values predicted by Equation 3 assuming any possible VID setting along with the R LL a TOB values defined in the V CC Regulator Design Parameters Tables in the appropriate subsequent sections of this document. Current values to be used for assessing TOB during dynamic VID should be linearly scaled with voltage. For example, if a 90 A of current is defined at a VID of 1.1 V and the functional VID value is 0.6 V, then the TOB should be calculated assuming (0.6 V/1.1 V) x 90 A = 49 A.

Vccmax VRD TOB can be relaxed during dynamic VID. Positive tolerance variation is permitted and is to be bounded by the voltages predicted by Equation 1, where VID is the standard VID value in regulation when not in the D-VID mode.

1.3.4.4 Ripple Voltage (Required)

To meet tolerance band specifications, high and low frequency ripple is to be limited to 10 mV peak to peak. Measurements must be taken carefully to ensure that

superposition of high frequency with low frequency oscillations do not sum to a value greater than 10 mV peak to peak. Measurements are to be taken with a 20 MHz band limited oscilloscope. Ripple testing is to be performed at 5 A minimum loading and at VR TDC. When PSI# is asserted and the VR is operating in the PSI# mode, the ripple voltage can be 20 mV peak to peak.

1.3.4.5 Sense Topology Requirements

VRD designers must construct a sense topology that ensures compliance to tolerance band specifications under standard operation and under the D-VID mode of operation. This includes selection of sense elements and supporting components that satisfy tolerance requirements with the chosen PWM controller and ripple amplitude.

Inductor DCR or resistor sensing topologies are required to satisfy tolerance band requirements. Current sensing across MOSFET Rds-on is not suitable for loadline AVP functions due to the large variation in this parameter. Evaluation of this sense method has shown that the TOB requirements cannot be satisfied unless expensive, <10% tolerance MOSFETs are chosen.

1.3.4.6 Error Amplifier Specification (EXPECTED)

The PWM error amplifier should be designed with a sufficient gain bandwidth product to ensure duty cycle saturation does not occur with large signal current transients. Typical target closed loop VR bandwidths of 30–200 kHz (20% of switching frequency target) are expected in VR11.1 system designs. The output of the error amplifier should also have high slew rates to avoid duty cycle saturation. Performance

limitations must be included in the VRD TOB equations.

VRD 11.1 Common Information 20 Processor Power Delivery Design Guidelines 1.3.4.7

PWM Operating Frequency (EXPECTED) VR11.1 PWM must be designed to work across a wide range of switching frequencies. For the desktop and UP server/workstation market, this can range from 200 kHz up to 1 MHz and corresponding loop bandwidths of 30 kHz to 250 kHz respectively. The tolerance of the PWM oscillator should be <10%. Performance limitations must be included in the VRD TOB equations. 1.3.5

Stability (REQUIRED) The VRD must be unconditionally stable under all DC and transient conditions across the voltage and current ranges defined in the V CC Regulator Design Parameters Tables in the appropriate subsequent sections of this document. The VRD must also operate in a no-load condition. 1.3.6

Dynamic Voltage Identification (REQUIRED) 1.3.6.1

Dynamic-Voltage Identification Functionality VRD11.1 architecture includes the Dynamic Voltage Identification (D-VID) feature set, which enables the processor to reduce power consumption and processor temperature. Reference VID codes are dynamically updated by the processor to the VRD controller using the VID bus when a low power state is initiated. VID codes are updated sequentially in either 12.5 mV or 6.25 mV steps. The 6.25 mV steps can be transmitted every 1.25 μs and 12.5 mV steps can be transmitted every 2.5 μs until the final voltage code is encountered. The VR should settle within 5 mV of the final value within 15 μs for a D-VID event over 50 mV and within 5 μs for events less than 50 mV in magnitude. LGA775 processors that will use VR11.1 based PWM controllers will have single step upward DVID jumps on the order of 100s of mV up to a maximum of 250 mV . Downward DVID jumps should decay with the processor load current, the VR is not required to pull down the output voltage. If the PWM receives a single step upward DVID jump, it should regulate to the new output voltage target with a minimum slew rate of 10 mV/us. The PWM should not false trip the OCP or OVP monitors during walking or single step DVID events. The output voltage shall settle to within 5 mV of the target voltage in less than 8 us. For the 250 mV step, the VR must complete the transition in 25 us (transition time) + 8 us (settling time) = 33 us total time. During a D-VID event, the processor load may not be capable of absorbing output capacitor energy when the VID reference is lowered. As a result, reverse current may flow into the AC-DC regulator’s input filter, potentially charging the input filter to a voltage above the over voltage value. Upon detection of this condition, the AC-DC regulator will react by shutting down the AC-DC regulator supply voltage. The VRD and AC-DC filter must be designed to ensure this condition does not occur. In addition, reverse current into the AC-DC regulator must not impair the operation of the VRD, the AC-DC supply, or any other part of the system. Under all functional conditions, including D-VID, the V CC supply must satisfy loadline and overshoot constraints to avoid data corruption, system lock-up events, or system blue-screen failures.

VRD 11.1 Common Information

Processor Power Delivery Design Guidelines 21 Figure 1-3. Processor D-VID Loadline Transition States

1.3.6.2 D-VID Validation

Intel processors are capable of generating numerous D-VID states and the VRD must be designed to properly transition to and function at each possible VID voltage. However, exhaustive validation of each state is unnecessary and impractical.

Validation can be simplified by verifying the VRD conforms to socket loadline

requirements, tolerance band specifications, and D-VID timing requirements. Then, by default, each processor D-VID state will be valid. The key variables for V CC under D-VID conditions are processor loading, starting VID, ending VID, and V CC slew rate. The V CC slew rate is defined by VRD bulk decoupling, the output inductors, the switching FET resistance and the processor load. This indicates that the V CC slewing will have an exponential behavior, where the response to code ‘n+1’ takes longer to settle than code ‘n’. As a result, a test from maximum to minimum and from minimum to

maximum will be sufficient to ensure slew rate requirements and VID code regulation. To ensure support for any valid VID reference, testing should be performed from the maximum table entry of 1.6 V to the minimum VID table value. For VR11.1, use 0.5 V for the minimum value. The VRD must ensure that the full table transition occurs within 15 microseconds of the final VID code transmission. Slew rate timing is

referenced from 0.4 V on the rising edge of the initial VID code to the time the final voltage is settled within 5 mV of the final V CC value. Intel testing has noted a 10% change to the V CC slew rate between VRD no load (5 A) and full load (VR TDC) conditions. For this reason, the V CC slewing must be tested under both loading conditions.

During the D-VID test defined in the previous paragraph, V CC droop and undershoot amplitudes must be limited to avoid processor damage and performance failures. If the processor experiences a voltage undershoot due to D-VID transitions, an

application initiated di/dt droop can superimpose with this event and potentially

violate minimum voltage specifications. Droop during this D-VID test must be limited to 5 mV. This value was derived by calculating VRD tolerance band improvements at the low D-VID current and voltage values.

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