Mixed-Mode Cellular Array Processor Realization for Analyzin

Helsinki University of Technology,Electronic Circuit Design Laboratory

Report38,Espoo2003

Mixed-Mode Cellular Array Processor

Realization for Analyzing Brain

Electrical Activity in Epilepsy

Mika Laiho

Dissertation for the degree of Doctor of Science in Technology to be presented with due permis-sion of the Department of Electrical and Communications Engineering for public examination and debate in Auditorium S4at Helsinki University of Technology(Espoo,Finland)on the28th of June,2003,at12o’clock.

Helsinki University of Technology

Department of Electrical and Communications Engineering

Electronic Circuit Design Laboratory

Teknillinen korkeakoulu

S?hk?-ja tietoliikennetekniikan osasto

Piiritekniikan laboratorio

Distribution:

Helsinki University of Technology

Department of Electrical and Communications Engineering Electronic Circuit Design Laboratory

P.O.Box3000

FIN-02015HUT

Finland

Tel.+35894512271

Fax:+35894512269

ISBN951-22-6597-4

ISSN1455-8440

Otamedia Oy

Espoo2003

Abstract

This thesis deals with the realization of hardware that is capable of computing algo-rithms that can be described using the theory of polynomial cellular neural/nonlinear networks(CNNs).The goal is to meet the requirements of an algorithm for predict-ing the onset of an epileptic seizure.The analysis associated with this application requires extensive computation of data that consists of segments of brain electrical activity.Different types of computer architectures are overviewed.Since the algo-rithm requires operations in which data is manipulated locally,special emphasis is put on assessing different parallel architectures.An array computer is potentially able to perform local computational tasks effectively and rapidly.

Based on the requirements of the algorithm,a mixed-mode CNN is proposed.A mixed-mode CNN combines analog and digital processing so that the couplings and the polynomial terms are implemented with analog blocks,whereas the integrator is digital.A/D and D/A converters are used to interface between the analog blocks and the integrator.Based on the mixed-mode CNN architecture a cellular array proces-sor is realized.In the realized array processor the processing units are coupled with programmable polynomial(linear,quadratic and cubic)?rst neighborhood feedback terms.A10mm2,1.027million transistor cellular array processor,with272pro-cessing units and36layers of memory in each is manufactured using a0.25μm digital CMOS process.The array processor can perform gray-scale Heun’s integration of spa-tial convolutions with linear,quadratic and cubic activation functions for7272data while keeping all I/O operations during processing local.One complete Heun’s itera-tion round takes166.4μs,while the power consumption during processing is192mW. Experimental results of statistical variations in the multipliers and polynomial circuits are shown.Descriptions regarding improvements in the design are also explained. The results of this thesis can be used to assess the suitability of the mixed-mode ap-proach for implementing an implantable system for predicting epileptic seizures.The results can also be used to assess the suitability of the approach for implementing other

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Preface

This thesis is the result of work that was carried out in the Electronic Circuit Design Laboratory(ECDL)of Helsinki University of Technology between1999and2003. The inspiring and relaxed university atmosphere has been a source of continuous chal-lenges and learning opportunities.I want to thank professors Kari Halonen and Veikko Porra for recruiting me to the ECDL and for giving me an interesting research topic.

I have been privileged to work with very competent people and have received ex-pert guidance at the course of the thesis work.I want to thank Prof.Halonen for his efforts as the supervisor of my thesis.The contribution of Prof.Ari Paasio in guiding this work with his versatile expertise has been invaluable.His devotion towards guid-ing the thesis persisted even after he started as a professor in the University of Turku. It has been a pleasure working with him.In addition to Prof.Paasio,teamwork with the rest of the“CNN team”,namely Asko Kananen,Lauri Koskinen,Mikko Talonen and Jacek Flak has been both fruitful and fun.Furthermore,the whole crew of the ECDL deserves recognition due to their enthusiasm and fellowship.Speci?cally,ad-vice from Dr.Mikko Waltari and Dr.Teemu Salo in various matters of circuit design has been valuable.Our secretary,Helena Yll?,has done excellent work in taking care of the practical matters.For their devoted and prompt work as pre-examiners of this thesis,I want to thank Prof.Peter Kinget(Columbia University,NY,USA)and Dr. Ricardo Carmona(Centro Nacional de Microelectronica,Sevilla,Spain).I also want to acknowledge the fruitful discussions with Prof.Ronald Tetzlaff and Dr.Roland Kunz from the Johann Wolfgang Goethe-University,Frankfurt,Germany.

This thesis was funded by the Academy of Finland(projects“Integrated Parallel Processors for Future Multimedia,Medical Imaging and Communication Systems”and“Integrated Parallel Processors for Future Data Processing and Analyzing Sys-tems”)and the Graduate School in Electronics,Telecommunications,and Automa-tion(GETA).The work was also supported by the Nokia Foundation,the Foundation of Technology(Tekniikan edist?miss??ti?),the Instrumentarium Science Foundation

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Contents

Abstract i

Preface iii Contents v Symbols and Abbreviations xi

1Introduction1

1.1Motivation (1)

1.2Research Contribution (2)

1.3Organization of the Thesis (3)

2Towards Parallel Architectures7

2.1Computing Speed of General Purpose Processors (8)

2.1.1Computing Speed due to Development of Technology (8)

2.1.2Parallel Operation in General Purpose Processors (8)

2.1.3Network on Chip (9)

2.1.3.1Motivation (9)

2.1.3.2Network on Chip Platforms (9)

2.2Bit-Serial Processing (10)

2.2.1Computational RAM (10)

2.2.2Near Sensor Bit-Serial Image Processing (11)

2.3Content Addressable Memory (12)

2.4Arti?cial Neural Networks (12)

2.5Analog/Mixed-Signal Array Processing (13)

2.5.1SIMD Array Composed of Analog Microprocessors (13)

2.5.2Analog Multiple Instruction Multiple Data Processing (14)

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vii

viii

ix

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Symbols and Abbreviations

ii c j j c kk data unit in kk th block of ii th c row and j j th c column in data parti-tioned by chopping

ii f j j f kk data unit in kk th block of ii th f row and j j th f column in data parti-tioned by folding

?ΣDelta-Sigma

?x i j n time-discretized rate of change of state in a DTCNN

A space-independent convolution mask,feedback template

A1space-independent linear feedback template in a polynomial CNN A2space-independent quadratic feedback template in a polynomial CNN

A3space-independent cubic feedback template in a polynomial CNN

A i j space-dependent convolution mask,feedback template

B space-independent feedback template

B1space-independent linear feedforward template in a polynomial CNN

B2space-independent quadratic feedforward template in a polynomial CNN

ΦF bulk Fermi potential

τ?xed delay in the method of delays

τ1a delay in linear feedback path

τ2a delay in second order polynomial feedback path

τ3a delay in third order polynomial feedback path

a L SRAM address signals that determine which layer is being ac-

cessed,L136

xii Symbols and Abbreviations

Symbols and Abbreviations xiii

xiv Symbols and Abbreviations

Symbols and Abbreviations xv

xvi Symbols and Abbreviations

Symbols and Abbreviations xvii

xviii Symbols and Abbreviations

Chapter1

Introduction

1.1Motivation

The minimum feature sizes of advanced silicon processes have decreased in a pre-dictable way for decades.According to the ITRS,this development is predicted to continue for several years.For example,it is estimated that the printed gate length in microprocessor-unit(MPU)products will be35nm in2007[1].This scaling down affects the design of digital processors in several ways:the number of transistors that can be?tted into a die increases,the maximum clock rate increases,and the dynamic power consumption decreases.Another way of improving processor performance is by moving towards parallel architectures.Due to architectural improvements in serial data processors,several instructions can be processed during one clock cycle.

In some applications,the algorithm is either inherently(for example image pro-cessing tasks),or can be converted into a form that is suitable for computation in an array processor.In an array processor,the processing units and memory are distributed in a regular parallel formation and local computation is performed.The regularity of the array makes the prediction of delays easier and reduces memory access times. This allows the full potential of advanced silicon processes to be utilized more easily. Array processors can be realized using digital or analog computational blocks or by combining both.The parallel computing power of an array processor may act as an enabling technology for new applications.

Cellular neural/nonlinear network(CNN)theory can readily describe convolution-based local operations;it also proposes an architecture for realizing a parallel com-puting device.The state of a cell in a CNN is updated by using initial data,con-trol terms and continuous-time spatio-temporal convolutions that are controlled by a

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