L1 Cache and TLB Enhancements to the RAMpage Memory Hierarchy

Abstract. The RAMpage hierarchy moves main memory up a level to replace the lowest-level cache by an equivalent-sized SRAM main memory, with a TLB caching page translations for that main memory. This paper illustrates how more aggressive components higher

L1CacheandTLBEnhancementstothe

RAMpageMemoryHierarchy

PhilipMachanick1andZunaidPatel2

SchoolofITEE,UniversityofQueensland

Brisbane,Qld4072,Australia

philip@itee.uq.edu.au

SchoolofComputerScience,UniversityoftheWitwatersrand,

Johannesburg,PrivateBag3,2050Wits,SouthAfrica

zunaid@cs.wits.ac.za12

Abstract.TheRAMpagehierarchymovesmainmemoryupaleveltoreplacethelowest-levelcachebyanequivalent-sizedSRAMmainmem-ory,withaTLBcachingpagetranslationsforthatmainmemory.ThispaperillustrateshowmoreaggressivecomponentshigherinthehierarchyincreasethefractionoftotalexecutiontimespentwaitingforDRAM.Foraninstructionissuerateof1GHz,thesimulatedstandardhierarchywaitedforDRAM10%ofthetime,increasingto40%ataninstructionissuerateof8GHz.ForalargerL1cache,thefractionoftimewaitingforDRAMwasevenhigher.RAMpagewithcontextswitchesonmisseswasabletohidealmostallDRAMlatency.AlargerTLBwasshowntoincreasetheviablerangeofRAMpageSRAMpagesizes.

1Introduction

TheRAMpagememoryhierarchymovesmainmemoryupaleveltoreplacethelowest-levelcachewithanSRAMmainmemory,whileDRAMbecomesa rst-levelpagingdevice.PreviousworkhasshownthatRAMpagerepresentsanalternative,viabledesignintermsofhardware-softwaretrade-o s[22]andthatitscalesbetterastheCPU-DRAMspeedgapgrows,particularlybyvirtueofbeingabletotakecontextswitchesonmisses[21].

Inpreviouswork,itwashypothesizedthatRAMpagewouldbemorecom-petitiveacrossawiderrangeofSRAMpagesizes(equivalenttolinesizeofthelowest-levelcache)withamoreaggressiveTLB.Secondly,itwashypothesizedthatamoreaggressiveL1cachewouldemphasizedi erencesinlowerlevelsofthehierarchy.Inthispaper,wereportoninvestigationofbothhypothesesasseparateissues.ImprovingtheTLBandL1hasdi erente ectsonperformance.TheintentinpresentingbothinthesamepaperistoaddseveraldatapointstoourcaseforRAMpage.

Insomestudies,TLBmisseshaveaccountedforasmuchas40%ofruntime

[13],with guresintheregionof20–30%common[6,23].RAMpagehasthepotentialtoreducethesigni canceoftheTLBonperformancefortworeasons.Firstly,unlessthereferencewhichcausesaTLBmisswouldalsomissinthe

Abstract. The RAMpage hierarchy moves main memory up a level to replace the lowest-level cache by an equivalent-sized SRAM main memory, with a TLB caching page translations for that main memory. This paper illustrates how more aggressive components higher

SRAMmainmemory,noreferencetoupdatetheTLBneedsgotoDRAM,withthepagetableorganizationusedforRAMpage.Secondly,thereisnomismatchbetweenthesizeofpagemappedbytheTLBandthe“linesize”ofthe“lowest-levelcache”,aswouldbethecasewithaconventionalhierarchy.Consequently,theTLBcanmoreeasilybedesignedtomapaspeci cfractionoftheSRAMmainmemory,thanisthecaseforaconventionalcache.

Theroleofincreasinglyaggressiveon-chipcachesalsoneedstobeevaluated,againsttheviewthatsuchcachesaddressthememorywallproblem.Quadruplingthesizeofacachemayhalvethenumberofmisses[28],butsuchexpansionmaynotalwaysbepractical.Increasingthesizeofcachesinanycasemakesithardertoscaleuptheirspeed[11].

TheapproachinthispaperistocompareRAMpagewithaconventional2-levelcachehierarchyasthesizeoftheTLBscalesup,acrossdi erentSRAMmainmemorypagesizes,aswellasavarietyofL1cachesizes,inseparateexperiments.ThesimulatedL2cacheof4Mbytesrunsatathirdoftheissuerateexcludingmisses.Theintentistoemphasizethatevenaveryfast,largeon-chipcacheresultsinalargefractionofrun-timebeingspentwaitingforDRAM.Evenso,giventhatDRAMreferencesarethedominante ectbeingmeasured,afastcacheshouldnotinvalidatethegeneraltrendsbeingstudied.

TLBmeasurementsshowthatbothmodelsseeareductioninTLBmissratesastheTLBsizeincreases,butRAMpagebecomesmoreviablewithsmallerSRAMmainmemorypagesizes.CachemeasurementsshowthatasL1sizeincreases,thefractionoftimespentwaitingforDRAMincreases(evenifoverallruntimedecreases),whichmakestheoptionintheRAMpagehierarchyoftakingacontextswitchonamissmoreattractive.

Theremainderofthispaperisstructuredasfollows.Section2presentsmoredetailoftheRAMpagehierarchyandrelatedresearch.Section3explainstheexperimentalapproach,whileSection4presentsexperimentalresults.Inconclu-sion,Section5,summarizesthe ndingsandoutlinesfuturework.

2Background

TheRAMpagemodelwasproposed[20]inresponsetothememorywall[30,16].ThekeyideaoftheRAMpagemodelistominimizehardwarecomplexity,whilemovingmoreofthememorymanagementintelligenceintosoftware.ARAMpagemachinethereforelooksverylikeaconventionalmodel,exceptthelowest-levelcacheisreplacedbyaconventionally-addressedphysicalmemory,thoughimplementedinSRAMratherthanDRAM.

Anumberofotherapproachestoaddressingthememorywallhavebeenpro-posed.Thissectionsummarizesthememorywallissue,followedbymoredetailofRAMpage.Afterpresentingotheralternatives,theoptionsarediscussed.

2.1MemoryWall

Thememorywallisthesituationwherethee ectofCPUimprovementsbecomesinsigni cantasthespeedimprovementofDRAMbecomesalimitingfactor.Since

Abstract. The RAMpage hierarchy moves main memory up a level to replace the lowest-level cache by an equivalent-sized SRAM main memory, with a TLB caching page translations for that main memory. This paper illustrates how more aggressive components higher

themid-1980s,CPUspeedshaveimprovedatarateof50-100%peryear,whileDRAMlatencyhasonlyimprovedataround7%peryear[12].Ifpredictionsofthememorywall[30]arecorrect,DRAMlatencywillbecomeaseriouslimitingfactorinperformanceimprovement.Attemptsatworkingaroundthememorywallarebecomingincreasinglycommon[9],butthefundamentalunderlyingDRAMandCPUlatencytrendscontinue[27].

2.2TheRAMpageApproach

RAMpageisbasedonthenotionthatDRAM,whilestillordersofmagnitudefasterthandisk,isincreasinglystartingtodisplayoneattributeofaperipheral:thereistimetodootherworkwhilewaitingforit[24],particularlyifrelativelylargeunitsaremovedbetweenDRAMandSRAMlevel.InRAMpage,thelowest-levelcacheismanagedasthemainmemory(i.e.,asapagedvirtually-addressedmemory),withdiskasecondarypagingdevice.TheRAMpagemainmemorypagetableisinverted,tominimizeitssize.Aninvertedpagetablehasanotherbene t:noTLBmisscanresultinaDRAMreference,unlessthereferencecausingtheTLBlookupisnotinanyoftheSRAMlayers[22].

RAMpageisintendedtohavethefollowingadvantages:

–fasthits–ahitphysicallyaddressesanSRAMmemory

–fullassociativity–fullassociativitythroughpagingavoidstheslowerhitsofhardwarefullassociativity

–software-managedpaging–replacementcanbeassophisticatedasneeded–TLBmissesstoDRAMminimized–asexplainedabove

–pinninginSRAM–criticalOSdataandcodecanbepinnedinSRAM–hardwaresimplicity–thecomplexityofacachecontrollerisremovedfromthelowestlevelofSRAM

–contextswitchesonmissestoDRAM–theCPUcanbekeptbusy

Theseadvantagescomeatthecostofslowermissesbecauseofsoftwaremiss-handling,andtheneedtomakeoperatingsystemchanges.However,thelatterproblemcouldbeavoidedbyaddinghardwaresupportforthemodel.

TheRAMpageapproachhasinthepastbeenshowntoscalewellinthefaceofthegrownCPU-DRAMspeedgap,particularlywithcontextswitchesonmisses.Thee ectofcontextswitchesonmissesisthat,providedthereisworkavailablefortheCPU,waitingforDRAMcane ectivelybeeliminated[21].Contextswitchesonmisseshavethemostsigni cante ect.

2.3Alternatives

Approachestoaddressingthememorywallcanloosely(withsomeoverlaps)begroupedintolatencytoleranceandmissreduction.Someapproachestola-tencytoleranceincludeprefetch,criticalword rst,memorycompression,writebu ering,non-blockingcaches,andsimultaneousmultithreading(SMT).

Abstract. The RAMpage hierarchy moves main memory up a level to replace the lowest-level cache by an equivalent-sized SRAM main memory, with a TLB caching page translations for that main memory. This paper illustrates how more aggressive components higher

Prefetchrequiresloadingacacheblockbeforeitisrequested,eitherbyhard-ware[5]orwithcompilersupport[25];predictiveprefetchattemptstoimproveaccuracyofprefetchforrelativelyvariedmemoryaccesspatterns[1].Incriticalword rst,thewordcontainingthereferencewhichcausedthemissisfetched rst,followedbytherestoftheblock[11].Memorycompressionine ectreduceslatencybecauseasmalleramountofinformationmustbemovedonamiss.Theoverheadmustbelessthanthetimesaved[18].Therearemanyvariationsonwritemissstrategy,butthemoste ectivegenerallyincludewritebu ering[17].Anon-blockingcache(lockup-free)cachecanallowanaggressivepipelinetocontinuewithotherinstructionswhilewaitingforamiss[4].

SMTisaimedatmaskingDRAMlatencyaswellasothercausesofpipelinestalls,byhardwaresupportformorethanoneactivethread[19].SMTaimstosolveawiderrangeofCPUperformanceproblemsthanRAMpage.

Theseideashavecosts(e.g.,prefetchingcandisplaceneededcontent,causingunnecessarymisses).ThebiggestproblemisthatmostoftheseapproachesdonotscalewiththegrowingCPU-DRAMspeedgap.Criticalword rstislesshelpfulaslatencyforonereferencegrowsinrelationtototaltimeforabigDRAMtransaction.Prefetch,memorycompressionandnonblockingcacheshavelimitsastohowmuchtheycanreducee ectivelatency.Writebu eringcanscaleprovidedbu ersizecanbescaled,andreferencestobu eredwritescanbehandledbeforetheyarewrittenback.SMTcouldmaskmuchofthetimespentwaitingforDRAM,butatthecostofamorecomplexCPU.

Reducingmisseshasbeenaddressedbyincreasingcachesize,associativity,orboth.Therearelimitsonhowlargeacachecanbeatagivenspeed,sothenumberoflevelshasincreased.Fullassociativitycanbeachievedinhardwarewithlessoverheadforhitsthanaconventionalfully-associativecache,inanindirectindexcache(IIC),bywhatamountstoahardwareimplementationofRAMpage’spagetablelookup[10].AdrawbackofIICisthatallreferencesincuroverheadofanextralevelofindirection.Earlierworkonsoftware-basedcachemanagementhasnotfocusedonreplacementpolicy[7,14].

TheadvantagesofRAMpageoverSMTandotherhardware-basedmulti-threadingapproachesarethattheCPUcanbekeptsimple,andsoftwareim-plementationofsupportformultipleprocessesismore exible(thebalancebe-tweenmultitaskingandmultithreadingcanbedynamicallyadjusted,accordingtoworkload).AnadvantageofIICisthattheOSneednotbeinvokedtohandletheequivalentofaTLBmissinRAMpage.AscomparedwithRAMpage,anIIChasmoreoverheadforahit,andlessforamiss.

2.4Summary

RAMpagemaskstimewhichwouldotherwisebespentwaitingforDRAMbytakingcontextswitchesonmisses.OtherapproachseitherdonotaimtomasktimespentwaitingforDRAM,buttoreduceit,orrequiremorecomplexhard-ware.RAMpagecanpotentiallybecombinedwithsomeoftheotherapproaches(suchasSMT),soitisnotnecessarilyincon ictwithotherideas.

Abstract. The RAMpage hierarchy moves main memory up a level to replace the lowest-level cache by an equivalent-sized SRAM main memory, with a TLB caching page translations for that main memory. This paper illustrates how more aggressive components higher

3ExperimentalApproach

Thissectionoutlinestheapproachtothereportedexperiments.Thesimula-tionstrategyisexplained,followedbysomedetailofsimulationparameters;inconclusion,expected ndingsarediscussed.

3.1SimulationStrategy

Arangeofvariationsonastandard2-levelhierarchyiscomparedtosimilarvariationsonRAMpage,withandwithoutcontextswitchesonmisses.RAMpagewithoutcontextswitchesonmissestoconveysthee ectsofaddingassociativity(withanoperatingsystem-stylereplacementstrategy).AddingcontextswitchesonmissesshowsthevalueofalternativeworkonamisstoDRAM.Simulationsaretrace-driven,anddonotmodelthepipeline.ProcessorspeedisinGHz,representinginstructionissueratewithoutmisses,notclockspeed.

Ignoringthepipelinelevelneglectse ectslikebranchesandthepotentialforotherimprovementslikenon-blockingcaches.However,theresultsbeinglookedforherearerelativelylargeimprovements,soinaccuraciesofthiskindareunlikelytobesigni cant.Whatisimportantisthee ectastheCPU-DRAMspeedgapincreases,andthesimulationisofsu cientaccuracytocapturesuche ects,ashasbeendemonstratedinpreviouswork.

3.2SimulationParameters

Parametersaresimilartopreviouspublishedworktomakeresultscomparable.ThefollowingparametersarecommonacrossRAMpageandtheconventionalhierarchy.ThisrepresentsthebaselinebeforenewL1andTLBvariations:–L1cache–16Kbyteseachofdataandinstructioncache,physicallytaggedandindexed,direct-mapped,32-byteblocksize,1-cyclereadhit,12-cyclepenaltyformissestoL2(orRAMpageSRAMmainmemory);fordatacache:perfectwritebu ering(zeroe ectivehittime),writeback(12-cyclepenalty;9cyclesforRAMpage:noL2tagtoupdate),writeallocateonmiss–TLB–64entries,fullyassociative,randomreplacement

–DRAMlevel–DirectRambus[8]withoutpipelining:50nsbefore rstrefer-encestarted,thereafter2bytesevery1.25ns–pagingofDRAM–invertedpagetable:sameorganizationasRAMpagemainmemoryforsimplicity,in niteDRAMwithnomissestodisk–TLBandL1datahitsfullypipelined–onlytimeforL1dorTLBreplace-mentsormaintaininginclusioncostedas“hits”

Thesamememorytimingisusedasinearliersimulations.AlthoughfasterDRAMhassincebecomeavailable,thetimingcanbeseenasrelativetoapar-ticularCPU-DRAMspeedgap,andthe gurescanaccordinglyberescaled.Contextswitchesaremodelledbyinterleavingatraceoftext-bookcode.Acontextswitchistakenevery500,000references,thoughRAMpagewithcontextswitchesonmissesalsotakesacontextswitchonamisstoDRAM.TLBmissesarehandledbyatraceofpagetablelookupcode,withvariationsontimeforalookupbasedonprobablevariationsinprobesintoaninvertedpagetable[22].

Abstract. The RAMpage hierarchy moves main memory up a level to replace the lowest-level cache by an equivalent-sized SRAM main memory, with a TLB caching page translations for that main memory. This paper illustrates how more aggressive components higher

speci ctoconventionalhierarchy

The“conventional”systemhasa2-wayassociative4MbyteL2.TheL2cacheanditsbustotheCPUtheareclockedatonethirdoftheCPUissuerate(thecycletimeisintendedtorepresentasuperscalarissuerate).TheL2cache-CPUbusis128bitswideandrunsHitsontheL2cachetake4cyclesincludingthetagcheckandtransfertoL1.InclusionbetweenL1andL2ismaintained[12].TheTLBcachesvirtualpagetranslationstoDRAMphysicalframes.speci ctoRAMpagehierarchy

InRAMpagesimulations,mostparametersremainthesame,exceptthattheTLBmapstheSRAMmainmemory,andfullassociativityisimplementedinsoftware,throughasoftwaremisshandler.TheOSkeeps6pagespinnedintheSRAMmainmemorywhensimulatinga4Kbyte-SRAMpage,i.e.,24Kbytes,whichincreasestoto5336pagesfora128byteblocksize,atotalof667Kbytes.inputsandvariations

TracesarefromtheTracebasetracearchiveatNewMexicoStateUniversity1.

1.1-billionreferencesareused,withtracesinterleavedtocreatethee ectofamultiprogrammingworkload.

TomeasurevariationsonL1caches,thesizeofeachoftheinstructionanddatacacheswasvariedfromtheoriginalsizeof16KBto32KB,64KB,128KBand256KB.Toexploremoreofthedesignspace,L1blocksizewasmeasuredatsizesof32,64and128bytes.WedidnotvaryL2blocksizeswhenvaryingL1:anoptimumsizewasdeterminedinpreviouswork[21,22].However,whilevaryingtheTLB,wedidvaryL2blocksizeintheconventionalhiearchy,forcomparisonwithvaryingtheRAMpageSRAMmainmemorypagesize.Tomeasurethee ectofincreasingtheTLBsize,wevarieditfromtheoriginal64entriesto128,256and512.EvenlargerTLBsexist(e.g.,Power4hasa1024-entryTLB[29]),butthisrangeissu cienttocapturevariationsofinterest.

3.3ExpectedFindings

AsL1becomeslarger,RAMpagewithoutcontextswitchesonmissesshouldseelessofagain.WhileimprovingL1shouldnota ecttimespentinDRAM,RAMpage’sextraoverheadsinmanagingDRAMmayhaveamoresigni cante ectonoverallruntime.However,asthefractionofreferencesinupperlevelsincreaseswithoutadecreaseinreferencestoDRAM,contextswitchesonmissesshouldbecomemorefavourable.

AstheTLBsizeincreases,weexpecttoseesmallerSRAMpagesizesbecomeviable.IftheTLBhas64entriesandthepagesizeis4KBwitha4MBSRAM

Abstract. The RAMpage hierarchy moves main memory up a level to replace the lowest-level cache by an equivalent-sized SRAM main memory, with a TLB caching page translations for that main memory. This paper illustrates how more aggressive components higher

mainmemory,6.25%ofthememoryismappedbytheTLB.IftheTLBhas512entries,theTLBmaps50%ofthememory.Bycomparison,witha128Bpage,a64-entryTLBonlymapsabout0.2%ofthememory,andabigincreaseinthesizeoftheTLBislikelytohaveasigni cante ect.

Thee ectonaconventionalarchitectureofincreasingTLBsizeisnotassigni cantbecauseitmapsDRAMpages( xedat4KB),notSRAMpages.Further,variationacrossL2blocksizesshouldnotberelatedtoTLBsize.4Results

Thissectionpresentsresultsofsimulations,withsomediscussion.Themainfocusisondi erencesintroducedbychangesoverprevioussimulations,butsomeadvantagesofRAMpage,aspreviouslydescribed,shouldbeevidentagainfromthesenewresults.Presentationofresultsisbrokendownintoe ectsofincreasingL1cachesize,ande ectsofincreasingTLBsize,sincetheseimprovementshaveverydi erente ectsonthehierarchiesmodelled.Resultsarepresentedfor3cases:theconventional2-levelcachewithaDRAMmainmemory,andRAMpagewithandwithoutcontextswitchesonmisses.

Theremainderofthissectionpresentsthee ectsofL1changes,thenthee ectsofTLBchanges,followedbyasummary.

4.1IncreasingL1Size

Fig.1showshowmissratesoftheL1instructionanddatacachesvaryastheirsizeincreasesforbothRAMpagewithcontextswitchesonmissesandthestan-dardhierarchy.(RAMpagewithoutswitchesonmissesfollowsthesametrendasthestandardhierarchy.)Ascachesizesincrease,themissratedecreases,initiallyfairlyrapidly.Thetrendissimilarforallmodels.

Executiontimesareplottedin g.2,normalisedtothebestexecutiontimeateachCPUspeed.Asexpected,largercachesdecreaseexecutiontimesbyre-ducingcapacitymisses,asevidentfromthereducedmissrates–withlimitstothebene tsasL1scalesup.Thebestoveralle ectisfromthecombina-tionofRAMpagewithcontextswitchesonmissesandincreasingthesizeofL1.Theexecutiontimeofthefastestvariationspeedsup10.7overtheslowestcon guration,paringagivenhi-erarchy’sslowest(1GHz,32KBL1)andfastestcase(8GHz,256KBtotalL1)resultsinaspeedupof6.12fortheconventionalhierarchy,6.5forRAMpagewithoutswitchesonmissesand9.9forswitchesonmisses.ForslowestCPUandsmallestL1,RAMpagewithswitchesonmisseshasaspeedupof1.08overtheconventionalhierarchy,risingto1.74withthefastestCPUandbiggestL1.ForRAMpagewithoutswitchesonmisses,thescalingupofimprovementovertheconventionalhierarchyisnotasstrong:fortheslowestCPUwithleastaggressiveL1,RAMpagehasaspeedupof1.03,asopposedto1.11forthefastestCPUwithlargestL1.So,whetherbycomparisonwithaconventionalarchitectureorby

Abstract. The RAMpage hierarchy moves main memory up a level to replace the lowest-level cache by an equivalent-sized SRAM main memory, with a TLB caching page translations for that main memory. This paper illustrates how more aggressive components higher

sizesmore

Abstract. The RAMpage hierarchy moves main memory up a level to replace the lowest-level cache by an equivalent-sized SRAM main memory, with a TLB caching page translations for that main memory. This paper illustrates how more aggressive components higher

Fraction of time at each level32K64K128KTotal L1 size (KB)256K512K(a)Issuerate1GHz(Std)

Fig.3showsrelativetimeseachvariationoftheslowestandfastestCPUspendwaitingforeachlevelofthevarioushierarchies,asL1sizeincreases.The8GHzissueratefortheconventionalhierarchyspendsover40%oftotalexecu-tiontimewaitingforDRAMforthelargestL1cache–inlinewithmeasurementsofthePentium4,whichspends35%ofitstimewaitingforDRAMrunningSPECint2konaverageat2GHz[28].ThisPentium4con gurationcorrespondsroughlytoa6GHzissuerateinthispaper.ThesimilarityofthetimewaitingforDRAMlendssomecredibilitytoourviewthatourresultsarereasonablyinlinewithrealsystems.

Abstract. The RAMpage hierarchy moves main memory up a level to replace the lowest-level cache by an equivalent-sized SRAM main memory, with a TLB caching page translations for that main memory. This paper illustrates how more aggressive components higher

Miss Rate(a)Whilecachesizeincreasesboostperformancesigni cantly,asCPUspeedincreases,alargeL1cannotsaveaconventionalhierarchyfromthehighpenaltyofwaitingforDRAM.In g.3(d),itcanbeseenthatRAMpageonlyimprovesthesituationmarginallywithoutcontextswitchesonmisses.

WithRAMpagewithcontextswitchesonmisses,timewaitingforDRAMremainsnegligibleastheCPU-DRAMspeedgapincreasesbyafactorof8( g.3(f)).ThelargestL1(combinedL1iandL1dsize512KB)resultsinonlyabout10%ofexecutiontimebeingspentwaitingforSRAMmainmemory,whileDRAMwaittimeremainsnegligible.Bycontrast,theotherhierarchies,whileseeingasigni cantreductionintimewaitingforL2(orSRAMmainmemory),donotseeasimilarreductionintimewaitingforDRAMasL1sizeincreases.

4.2TLBVariations

AllTLBvariationsaremeasuredwiththeL1parameters xedattheoriginalRAMpagemeasurements–16KBeachofinstructionanddatacache.

TheTLBmissrate( g.4),evenwithincreasedTLBsizes,issigni cantlyhigherinallRAMpagecasesthanforthestandardhierarchy,exceptfora4KBRAMpagepagesize.AsSRAMmainmemorypagesizeincreases,TLBmissratesdrop,asexpected.Further,asTLBsizeincreases,smallerpages’missratesdecrease.Inthecaseofcontextswitchesonmisses,thenumberofcontext

Abstract. The RAMpage hierarchy moves main memory up a level to replace the lowest-level cache by an equivalent-sized SRAM main memory, with a TLB caching page translations for that main memory. This paper illustrates how more aggressive components higher

Page Size (B)01020

Overhead (%)

3040

Abstract. The RAMpage hierarchy moves main memory up a level to replace the lowest-level cache by an equivalent-sized SRAM main memory, with a TLB caching page translations for that main memory. This paper illustrates how more aggressive components higher

ofthestandardhierarchy.RAMpageTLBmissesdonotresultinreferencestoDRAM,unlessthereisapagefault,sotheadditionalreferencesshouldnotresultinasimilarlysubstantialperformancehit.

Fig.6illustratesexecutiontimesforthehierarchiesat1and8GHz,thespeedgapwhichshowso di erencesmostclearly.Therearetwocompetinge ects:asL2block(SRAMpagesize)increases,misspenaltytoDRAMincreases.InRAMpage,reducedTLBmissescompensateforthehigherDRAMmisspenalty,buttheperformanceofthestandardhierarchybecomesworseasblocksizein-creases.TLBsizevariationmakeslittledi erencetoperformanceofthestandardhierarchywiththesimulatedworkload.PerformanceofRAMpagewithswitchesonmissesdoesnotvarymuchforpagesof512BandgreaterevenwithTLBvariations,whileRAMpagewithoutswitchesisbestwith1024Bpages.

Theperformance-optimalTLBandpagesizecombinationforRAMpagewithoutcontextswitchesonmisses,witha512entryTLB,isa1024Bpageforallissuerates.Inpreviouswork,witha64-entryTLB,theoptimalpagesizeat1GHzwas2048B,whileotherissueratesperformedbestwith1024Bpages.Thus,alargerTLBresultsinasmallerpagesizebeingoptimalforthe1GHzspeed.Whileotherpagesizesarestillslowerthanthe1024Bpagesize,forallcaseswithpagesof512BandgreaterRAMpagewithoutcontextswitchesonmissesisfasterthanthestandardhierarchy.

ForRAMpagewithcontextswitchesonmisses,theperformance-optimalpagesizehasshiftedto1024BwithalargerTLB.Previouslythebestpagesizewas4096Bfor1,2and4GHzand2048Bfor8GHz.ATLBof256oreven128entriescombinedwiththe1024Bpagewillyieldoptimumoralmostoptimumperformance.Witha1024Bpageand256entries,atotalof256KB,or6.25%oftheRAMpagemainmemoryismappedbytheTLB,whichappearstobesu cientforthisworkload(a4KBpagewitha512-entryTLBmapshalftheSRAMmainmemory,overkillforanyworkloadwithreasonablelocalityofrefer-ence).Nonetheless,TLBperformanceishighlydependentonapplicationcode,soresultspresentedhereneedtobeconsideredinthatlight.

Contrastingthe1Ghzand8GHzcasesin g.6makesitclearagainhowthedi erencesbetweenRAMpageandaconventionalhierarchyscaleastheCPU-DRAMspeedgapincreases.At1GHz,allvariationsarereasonablycomparableacrossarangeofparameters.At8GHz,RAMpageisclearlybetterinallvaria-tions,butevenmoresowithcontextswitchesonmisses.AlargerTLBbroadenstherangeofusefulRAMpagecon gurations,withoutsigni cantlyalteringthestandardhierarchy’scompetitiveness.

4.3Summary

Insummary,theRAMpagemodelwithcontextswitchesonmissesgainsmostfromL1cacheimprovements,thoughtheotherhierarchiesalsoreduceexecutiontime.However,withouttakingcontextswitchesonmisses,increasingthesizeofL1hasthee ectofincreasingthefractionoftimespentwaitingforDRAM,sincethenumberofDRAMreferencesisnotreduced,noristheirlatencyhidden.AswasshownbyscalinguptheCPU-DRAMspeedgap,onlyRAMpagewith

Abstract. The RAMpage hierarchy moves main memory up a level to replace the lowest-level cache by an equivalent-sized SRAM main memory, with a TLB caching page translations for that main memory. This paper illustrates how more aggressive components higher

contextswitchesonmisses,ofthevariationspresentedhere,isabletohidetheincreasinge ectivelatencyofDRAM.IncreasingthesizeoftheTLB,aspredicted,increasedtherangeofSRAMmainmemorypagesizesoverwhichRAMpageisviable,wideningtherangeofchoicesforadesigner.

5Conclusion

ThispaperhasexaminedenhancementstoRAMpage,whichmeasureitspoten-tialforfurtherimprovement,asopposedtosimilarimprovementstoaconven-tionalhierarchy.Asinpreviouswork,RAMpagehasbeenshowntoscalebetterastheCPU-DRAMspeedgapgrows.Inaddition,ithasbeenshownthatcon-textswitchesonmissescantakeadvantageofamoreaggressivecoreincludingabiggerL1cache,andabiggerTLB.Theremainderofthissectionsummarizesresults,outlinesfutureworkandsumsupoverall ndings.

5.1SummaryofResults

Introducingsigni cantlylargerL1caches–evenifthiscouldbedonewith-outproblemswithmeetingclockcycletargets–haslimitedbene ts.Scalingtheclockspeedupbyafactorof8achievesonlyabout77%ofthisspeedupinacon-ventionalhierarchymeasuredhere.RAMpagewithcontextswitchesonmissesisabletomakee ectiveuseofalargerL1cache,andachievessuperlinearspeedupwithrespecttoaslowerclockspeedandsmallerL1cache.Whilethise ectcanonlybeexpectedinRAMpagewithanunrealisticallylargeL1,thisresultshowsthatincreasinglyaggressiveL1cachesarenotasimportantasolutiontothememorywallproblemas ndingalternativeworkonamisstoDRAM.

ThatresultsforRAMpagewithoutcontextswitchesonmissesareanim-provementbutnotassigni cantasresultswithcontextswitchesonmissessug-geststhatattemptsatimprovingassociativityandreplacementstrategywillnotbesu cienttobridgethegrowingCPU-DRAMspeedgap.

LargerTLBs,asexpected,increasetherangeofusefulRAMpageSRAMmainmemorypagesizes,thoughtheperformancebene tontheworkloadmeasuredwasnotsigni cantversuslargerpagesizesandamoremodest-sizedTLB.

5.2FutureWork

ItwouldbeinterestingtomatchRAMpagewithmodelsforsupportingmorethanoneinstructionstream.SMT,whileaddinghardwarecomplexity,isanestablishedapproach[19],withexistingimplementations[3].Anotherthingtoexploreisalternativeinterconnectarchitectures,somultiplerequestsforDRAMcouldbeoverlapped[24].HyperTransport[2]isacandidate.Amoredetailedsimulationmodellingoperatingsysteme ectsaccuratelywouldbeuseful.SimOS

[26],forexample,couldbeused.Furthervariationstoexploreincludevirtually-addressedL1andhardwareTLBmisshandling.Finally,itwouldbeinterestingtobuildaRAMpagemachine.

Abstract. The RAMpage hierarchy moves main memory up a level to replace the lowest-level cache by an equivalent-sized SRAM main memory, with a TLB caching page translations for that main memory. This paper illustrates how more aggressive components higher

5.3OverallConclusion

RAMpagehasbeensimulatedinavarietyofforms.Inthislateststudy,en-hancingL1andtheTLBhaveshownthatitgainssigni cantlymorefromsuchimprovementsthanaconventionalarchitectureinsomecases.Themostimpor-tant ndinggenerallyfromRAMpageworkisthat ndingotherworkonamisstoDRAMisbecomingincreasinglyviable.WhileRAMpageisnottheonlyap-proachto ndingsuchalternativework,itisapotentialsolution.Ascomparedwithhardwaremultithreadingapproaches,itsmainadvantageisthe exibilityofasoftwaresolution,thoughthisneedstobecomparedtohardwaresolutionstoestablishtheperformancecostofextra exibility.

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Acknowledgements

FinancialsupportforthisworkhasbeenreceivedfromUniversitiesofQueens-landandWitwatersrand,andSouthAfricanNationalResearchFoundation.Wewouldliketothanktherefereesforhelpfulsuggestions.

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