LM3S5R31-IBZ80-C3T系列 规格书,Datasheet 资料

Stellaris ?

LM3S5R31Microcontroller

DATA SHEET Copyright ?2007-2012

Texas Instruments Incorporated

DS-LM3S5R31-11425TEXAS INSTRUMENTS-PRODUCTION DATA

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Copyright

Copyright?2007-2012Texas Instruments Incorporated All rights reserved.Stellaris and StellarisWare?are registered trademarks of Texas Instruments Incorporated.ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited.Other names and brands may be claimed as the property of others.

PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instruments standard warranty.Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Texas Instruments Incorporated

108Wild Basin,Suite350

Austin,TX78746

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Table of Contents

Revision History (36)

About This Document (47)

Audience (47)

About This Manual (47)

Related Documents (47)

Documentation Conventions (48)

1Architectural Overview (50)

1.1Overview (50)

1.2Target Applications (52)

1.3Features (52)

1.3.1ARM Cortex-M3Processor Core (52)

1.3.2On-Chip Memory (54)

1.3.3External Peripheral Interface (55)

1.3.4Serial Communications Peripherals (57)

1.3.5System Integration (62)

1.3.6Advanced Motion Control (67)

1.3.7Analog (69)

1.3.8JTAG and ARM Serial Wire Debug (71)

1.3.9Packaging and Temperature (71)

1.4Hardware Details (72)

2The Cortex-M3Processor (73)

2.1Block Diagram (74)

2.2Overview (75)

2.2.1System-Level Interface (75)

2.2.2Integrated Configurable Debug (75)

2.2.3Trace Port Interface Unit(TPIU) (76)

2.2.4Cortex-M3System Component Details (76)

2.3Programming Model (77)

2.3.1Processor Mode and Privilege Levels for Software Execution (77)

2.3.2Stacks (77)

2.3.3Register Map (78)

2.3.4Register Descriptions (79)

2.3.5Exceptions and Interrupts (92)

2.3.6Data Types (92)

2.4Memory Model (92)

2.4.1Memory Regions,Types and Attributes (94)

2.4.2Memory System Ordering of Memory Accesses (95)

2.4.3Behavior of Memory Accesses (95)

2.4.4Software Ordering of Memory Accesses (96)

2.4.5Bit-Banding (97)

2.4.6Data Storage (99)

2.4.7Synchronization Primitives (100)

2.5Exception Model (101)

2.5.1Exception States (102)

2.5.2Exception Types (102)

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2.5.3Exception Handlers (105)

2.5.4Vector Table (105)

2.5.5Exception Priorities (106)

2.5.6Interrupt Priority Grouping (107)

2.5.7Exception Entry and Return (107)

2.6Fault Handling (109)

2.6.1Fault Types (109)

2.6.2Fault Escalation and Hard Faults (110)

2.6.3Fault Status Registers and Fault Address Registers (111)

2.6.4Lockup (111)

2.7Power Management (111)

2.7.1Entering Sleep Modes (111)

2.7.2Wake Up from Sleep Mode (112)

2.8Instruction Set Summary (113)

3Cortex-M3Peripherals (116)

3.1Functional Description (116)

3.1.1System Timer(SysTick) (116)

3.1.2Nested Vectored Interrupt Controller(NVIC) (117)

3.1.3System Control Block(SCB) (119)

3.1.4Memory Protection Unit(MPU) (119)

3.2Register Map (124)

3.3System Timer(SysTick)Register Descriptions (126)

3.4NVIC Register Descriptions (130)

3.5System Control Block(SCB)Register Descriptions (143)

3.6Memory Protection Unit(MPU)Register Descriptions (172)

4JTAG Interface (182)

4.1Block Diagram (183)

4.2Signal Description (183)

4.3Functional Description (184)

4.3.1JTAG Interface Pins (184)

4.3.2JTAG TAP Controller (186)

4.3.3Shift Registers (186)

4.3.4Operational Considerations (187)

4.4Initialization and Configuration (189)

4.5Register Descriptions (190)

4.5.1Instruction Register(IR) (190)

4.5.2Data Registers (192)

5System Control (194)

5.1Signal Description (194)

5.2Functional Description (194)

5.2.1Device Identification (195)

5.2.2Reset Control (195)

5.2.3Non-Maskable Interrupt (200)

5.2.4Power Control (200)

5.2.5Clock Control (201)

5.2.6System Control (209)

5.3Initialization and Configuration (210)

5.4Register Map (211)

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5.5Register Descriptions (212)

6Hibernation Module (301)

6.1Block Diagram (302)

6.2Signal Description (302)

6.3Functional Description (303)

6.3.1Register Access Timing (303)

6.3.2Hibernation Clock Source (304)

6.3.3System Implementation (305)

6.3.4Battery Management (306)

6.3.5Real-Time Clock (306)

6.3.6Battery-Backed Memory (307)

6.3.7Power Control Using HIB (307)

6.3.8Power Control Using VDD3ON Mode (307)

6.3.9Initiating Hibernate (307)

6.3.10Waking from Hibernate (307)

6.3.11Interrupts and Status (308)

6.4Initialization and Configuration (308)

6.4.1Initialization (308)

6.4.2RTC Match Functionality(No Hibernation) (309)

6.4.3RTC Match/Wake-Up from Hibernation (309)

6.4.4External Wake-Up from Hibernation (310)

6.4.5RTC or External Wake-Up from Hibernation (310)

6.5Register Map (310)

6.6Register Descriptions (311)

7Internal Memory (328)

7.1Block Diagram (328)

7.2Functional Description (328)

7.2.1SRAM (329)

7.2.2ROM (329)

7.2.3Flash Memory (331)

7.3Register Map (336)

7.4Flash Memory Register Descriptions(Flash Control Offset) (337)

7.5Memory Register Descriptions(System Control Offset) (349)

8Micro Direct Memory Access(μDMA) (365)

8.1Block Diagram (366)

8.2Functional Description (366)

8.2.1Channel Assignments (367)

8.2.2Priority (368)

8.2.3Arbitration Size (368)

8.2.4Request Types (368)

8.2.5Channel Configuration (369)

8.2.6Transfer Modes (371)

8.2.7Transfer Size and Increment (379)

8.2.8Peripheral Interface (379)

8.2.9Software Request (379)

8.2.10Interrupts and Errors (380)

8.3Initialization and Configuration (380)

8.3.1Module Initialization (380)

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8.3.2Configuring a Memory-to-Memory Transfer (380)

8.3.3Configuring a Peripheral for Simple Transmit (382)

8.3.4Configuring a Peripheral for Ping-Pong Receive (383)

8.3.5Configuring Channel Assignments (386)

8.4Register Map (386)

8.5μDMA Channel Control Structure (387)

8.6μDMA Register Descriptions (394)

9General-Purpose Input/Outputs(GPIOs) (423)

9.1Signal Description (423)

9.2Functional Description (428)

9.2.1Data Control (429)

9.2.2Interrupt Control (430)

9.2.3Mode Control (431)

9.2.4Commit Control (431)

9.2.5Pad Control (432)

9.2.6Identification (432)

9.3Initialization and Configuration (432)

9.4Register Map (433)

9.5Register Descriptions (436)

10External Peripheral Interface(EPI) (479)

10.1EPI Block Diagram (480)

10.2Signal Description (481)

10.3Functional Description (483)

10.3.1Non-Blocking Reads (484)

10.3.2DMA Operation (485)

10.4Initialization and Configuration (485)

10.4.1SDRAM Mode (486)

10.4.2Host Bus Mode (490)

10.4.3General-Purpose Mode (501)

10.5Register Map (509)

10.6Register Descriptions (510)

11General-Purpose Timers (552)

11.1Block Diagram (553)

11.2Signal Description (553)

11.3Functional Description (556)

11.3.1GPTM Reset Conditions (557)

11.3.2Timer Modes (557)

11.3.3DMA Operation (563)

11.3.4Accessing Concatenated Register Values (564)

11.4Initialization and Configuration (564)

11.4.1One-Shot/Periodic Timer Mode (564)

11.4.2Real-Time Clock(RTC)Mode (565)

11.4.3Input Edge-Count Mode (565)

11.4.4Input Edge Timing Mode (566)

11.4.5PWM Mode (567)

11.5Register Map (567)

11.6Register Descriptions (568)

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12.1Block Diagram (600)

12.2Functional Description (600)

12.2.1Register Access Timing (601)

12.3Initialization and Configuration (601)

12.4Register Map (601)

12.5Register Descriptions (602)

13Analog-to-Digital Converter(ADC) (624)

13.1Block Diagram (625)

13.2Signal Description (626)

13.3Functional Description (628)

13.3.1Sample Sequencers (628)

13.3.2Module Control (629)

13.3.3Hardware Sample Averaging Circuit (631)

13.3.4Analog-to-Digital Converter (632)

13.3.5Differential Sampling (635)

13.3.6Internal Temperature Sensor (638)

13.3.7Digital Comparator Unit (638)

13.4Initialization and Configuration (643)

13.4.1Module Initialization (643)

13.4.2Sample Sequencer Configuration (644)

13.5Register Map (644)

13.6Register Descriptions (646)

14Universal Asynchronous Receivers/Transmitters(UARTs) (704)

14.1Block Diagram (705)

14.2Signal Description (705)

14.3Functional Description (707)

14.3.1Transmit/Receive Logic (707)

14.3.2Baud-Rate Generation (708)

14.3.3Data Transmission (709)

14.3.4Serial IR(SIR) (709)

14.3.5ISO7816Support (710)

14.3.6Modem Handshake Support (710)

14.3.7LIN Support (712)

14.3.8FIFO Operation (713)

14.3.9Interrupts (714)

14.3.10Loopback Operation (715)

14.3.11DMA Operation (715)

14.4Initialization and Configuration (715)

14.5Register Map (716)

14.6Register Descriptions (718)

15Synchronous Serial Interface(SSI) (768)

15.1Block Diagram (769)

15.2Signal Description (769)

15.3Functional Description (770)

15.3.1Bit Rate Generation (771)

15.3.2FIFO Operation (771)

15.3.3Interrupts (771)

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15.3.4Frame Formats (772)

15.3.5DMA Operation (779)

15.4Initialization and Configuration (780)

15.5Register Map (781)

15.6Register Descriptions (782)

16Inter-Integrated Circuit(I2C)Interface (810)

16.1Block Diagram (811)

16.2Signal Description (811)

16.3Functional Description (812)

16.3.1I2C Bus Functional Overview (812)

16.3.2Available Speed Modes (814)

16.3.3Interrupts (815)

16.3.4Loopback Operation (816)

16.3.5Command Sequence Flow Charts (817)

16.4Initialization and Configuration (824)

16.5Register Map (825)

16.6Register Descriptions(I2C Master) (826)

16.7Register Descriptions(I2C Slave) (839)

17Inter-Integrated Circuit Sound(I2S)Interface (848)

17.1Block Diagram (849)

17.2Signal Description (849)

17.3Functional Description (851)

17.3.1Transmit (852)

17.3.2Receive (856)

17.4Initialization and Configuration (858)

17.5Register Map (859)

17.6Register Descriptions (860)

18Controller Area Network(CAN)Module (885)

18.1Block Diagram (886)

18.2Signal Description (886)

18.3Functional Description (887)

18.3.1Initialization (888)

18.3.2Operation (889)

18.3.3Transmitting Message Objects (890)

18.3.4Configuring a Transmit Message Object (890)

18.3.5Updating a Transmit Message Object (891)

18.3.6Accepting Received Message Objects (892)

18.3.7Receiving a Data Frame (892)

18.3.8Receiving a Remote Frame (892)

18.3.9Receive/Transmit Priority (893)

18.3.10Configuring a Receive Message Object (893)

18.3.11Handling of Received Message Objects (894)

18.3.12Handling of Interrupts (896)

18.3.13Test Mode (897)

18.3.14Bit Timing Configuration Error Considerations (899)

18.3.15Bit Time and Bit Rate (899)

18.3.16Calculating the Bit Timing Parameters (901)

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18.4Register Map (904)

18.5CAN Register Descriptions (905)

19Universal Serial Bus(USB)Controller (935)

19.1Block Diagram (935)

19.2Signal Description (936)

19.3Functional Description (936)

19.3.1Operation (936)

19.3.2DMA Operation (941)

19.4Initialization and Configuration (942)

19.4.1Endpoint Configuration (943)

19.5Register Map (943)

19.6Register Descriptions (948)

20Analog Comparators (1004)

20.1Block Diagram (1004)

20.2Signal Description (1005)

20.3Functional Description (1006)

20.3.1Internal Reference Programming (1006)

20.4Initialization and Configuration (1008)

20.5Register Map (1009)

20.6Register Descriptions (1009)

21Pulse Width Modulator(PWM) (1017)

21.1Block Diagram (1018)

21.2Signal Description (1019)

21.3Functional Description (1022)

21.3.1PWM Timer (1022)

21.3.2PWM Comparators (1023)

21.3.3PWM Signal Generator (1024)

21.3.4Dead-Band Generator (1025)

21.3.5Interrupt/ADC-Trigger Selector (1025)

21.3.6Synchronization Methods (1026)

21.3.7Fault Conditions (1027)

21.3.8Output Control Block (1027)

21.4Initialization and Configuration (1028)

21.5Register Map (1029)

21.6Register Descriptions (1032)

22Quadrature Encoder Interface(QEI) (1095)

22.1Block Diagram (1095)

22.2Signal Description (1096)

22.3Functional Description (1097)

22.4Initialization and Configuration (1100)

22.5Register Map (1100)

22.6Register Descriptions (1101)

23Pin Diagram (1118)

24Signal Tables (1120)

24.1100-Pin LQFP Package Pin Tables (1121)

24.2108-Ball BGA Package Pin Tables (1157)

24.3Connections for Unused Signals (1193)

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25Operating Characteristics (1195)

26Electrical Characteristics (1196)

26.1Maximum Ratings (1196)

26.2Recommended Operating Conditions (1196)

26.3Load Conditions (1197)

26.4JTAG and Boundary Scan (1197)

26.5Power and Brown-Out (1199)

26.6Reset (1200)

26.7On-Chip Low Drop-Out(LDO)Regulator (1201)

26.8Clocks (1201)

26.8.1PLL Specifications (1201)

26.8.2PIOSC Specifications (1202)

26.8.3Internal30-kHz Oscillator Specifications (1202)

26.8.4Hibernation Clock Source Specifications (1203)

26.8.5Main Oscillator Specifications (1203)

26.8.6System Clock Specification with ADC Operation (1204)

26.8.7System Clock Specification with USB Operation (1204)

26.9Sleep Modes (1204)

26.10Hibernation Module (1205)

26.11Flash Memory (1206)

26.12Input/Output Characteristics (1206)

26.13External Peripheral Interface(EPI) (1207)

26.14Analog-to-Digital Converter(ADC) (1213)

26.15Synchronous Serial Interface(SSI) (1214)

26.16Inter-Integrated Circuit(I2C)Interface (1216)

26.17Inter-Integrated Circuit Sound(I2S)Interface (1217)

26.18Universal Serial Bus(USB)Controller (1218)

26.19Analog Comparator (1219)

26.20Current Consumption (1219)

26.20.1Nominal Power Consumption (1219)

26.20.2Maximum Current Consumption (1220)

A Register Quick Reference (1222)

B Ordering and Contact Information (1264)

B.1Ordering Information (1264)

B.2Part Markings (1264)

B.3Kits (1265)

B.4Support Information (1265)

C Package Information (1266)

C.1100-Pin LQFP Package (1266)

C.1.1Package Dimensions (1266)

C.1.2Tray Dimensions (1268)

C.1.3Tape and Reel Dimensions (1268)

C.2108-Ball BGA Package (1270)

C.2.1Package Dimensions (1270)

C.2.2Tray Dimensions (1272)

C.2.3Tape and Reel Dimensions (1273)

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List of Figures

Figure1-1.Stellaris LM3S5R31Microcontroller High-Level Block Diagram (51)

Figure2-1.CPU Block Diagram (75)

Figure2-2.TPIU Block Diagram (76)

Figure2-3.Cortex-M3Register Set (78)

Figure2-4.Bit-Band Mapping (99)

Figure2-5.Data Storage (100)

Figure2-6.Vector Table (106)

Figure2-7.Exception Stack Frame (108)

Figure3-1.SRD Use Example (122)

Figure4-1.JTAG Module Block Diagram (183)

Figure4-2.Test Access Port State Machine (186)

Figure4-3.IDCODE Register Format (192)

Figure4-4.BYPASS Register Format (192)

Figure4-5.Boundary Scan Register Format (193)

Figure5-1.Basic RST Configuration (197)

Figure5-2.External Circuitry to Extend Power-On Reset (197)

Figure5-3.Reset Circuit Controlled by Switch (198)

Figure5-4.Power Architecture (201)

Figure5-5.Main Clock Tree (204)

Figure6-1.Hibernation Module Block Diagram (302)

a070875f2b160b4e767fcf44ing a Crystal as the Hibernation Clock Source (305)

a070875f2b160b4e767fcf44ing a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON

Mode (305)

Figure7-1.Internal Memory Block Diagram (328)

Figure8-1.μDMA Block Diagram (366)

Figure8-2.Example of Ping-PongμDMA Transaction (372)

Figure8-3.Memory Scatter-Gather,Setup and Configuration (374)

Figure8-4.Memory Scatter-Gather,μDMA Copy Sequence (375)

Figure8-5.Peripheral Scatter-Gather,Setup and Configuration (377)

Figure8-6.Peripheral Scatter-Gather,μDMA Copy Sequence (378)

Figure9-1.Digital I/O Pads (428)

Figure9-2.Analog/Digital I/O Pads (429)

Figure9-3.GPIODATA Write Example (430)

Figure9-4.GPIODATA Read Example (430)

Figure10-1.EPI Block Diagram (481)

Figure10-2.SDRAM Non-Blocking Read Cycle (489)

Figure10-3.SDRAM Normal Read Cycle (489)

Figure10-4.SDRAM Write Cycle (490)

Figure10-5.Example Schematic for Muxed Host-Bus16Mode (496)

Figure10-6.Host-Bus Read Cycle,MODE=0x1,WRHIGH=0,RDHIGH=0 (498)

Figure10-7.Host-Bus Write Cycle,MODE=0x1,WRHIGH=0,RDHIGH=0 (499)

Figure10-8.Host-Bus Write Cycle with Multiplexed Address and Data,MODE=0x0,WRHIGH

=0,RDHIGH=0 (499)

Figure10-9.Host-Bus Write Cycle with Multiplexed Address and Data and ALE with Dual

CSn (500)

Figure10-10.Continuous Read Mode Accesses (500)

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Figure10-11.Write Followed by Read to External FIFO (501)

Figure10-12.Two-Entry FIFO (501)

Figure10-13.Single-Cycle Write Access,FRM50=0,FRMCNT=0,WRCYC=0 (505)

Figure10-14.Two-Cycle Read,Write Accesses,FRM50=0,FRMCNT=0,RDCYC=1,

WRCYC=1 (505)

Figure10-15.Read Accesses,FRM50=0,FRMCNT=0,RDCYC=1 (506)

Figure10-16.FRAME Signal Operation,FRM50=0and FRMCNT=0 (506)

Figure10-17.FRAME Signal Operation,FRM50=0and FRMCNT=1 (506)

Figure10-18.FRAME Signal Operation,FRM50=0and FRMCNT=2 (507)

Figure10-19.FRAME Signal Operation,FRM50=1and FRMCNT=0 (507)

Figure10-20.FRAME Signal Operation,FRM50=1and FRMCNT=1 (507)

Figure10-21.FRAME Signal Operation,FRM50=1and FRMCNT=2 (507)

Figure10-22.iRDY Signal Operation,FRM50=0,FRMCNT=0,and RD2CYC=1 (508)

Figure10-23.EPI Clock Operation,CLKGATE=1,WR2CYC=0 (509)

Figure10-24.EPI Clock Operation,CLKGATE=1,WR2CYC=1 (509)

Figure11-1.GPTM Module Block Diagram (553)

Figure11-2.Timer Daisy Chain (559)

Figure11-3.Input Edge-Count Mode Example (561)

Figure11-4.16-Bit Input Edge-Time Mode Example (562)

Figure11-5.16-Bit PWM Mode Example (563)

Figure12-1.WDT Module Block Diagram (600)

Figure13-1.Implementation of Two ADC Blocks (625)

Figure13-2.ADC Module Block Diagram (626)

Figure13-3.ADC Sample Phases (630)

Figure13-4.Doubling the ADC Sample Rate (631)

Figure13-5.Skewed Sampling (631)

Figure13-6.Sample Averaging Example (632)

Figure13-7.ADC Input Equivalency Diagram (633)

Figure13-8.Internal Voltage Conversion Result (634)

Figure13-9.External Voltage Conversion Result (635)

Figure13-10.Differential Sampling Range,V IN_ODD=1.5V (636)

Figure13-11.Differential Sampling Range,V IN_ODD=0.75V (637)

Figure13-12.Differential Sampling Range,V IN_ODD=2.25V (637)

Figure13-13.Internal Temperature Sensor Characteristic (638)

Figure13-14.Low-Band Operation(CIC=0x0and/or CTC=0x0) (641)

Figure13-15.Mid-Band Operation(CIC=0x1and/or CTC=0x1) (642)

Figure13-16.High-Band Operation(CIC=0x3and/or CTC=0x3) (643)

Figure14-1.UART Module Block Diagram (705)

Figure14-2.UART Character Frame (708)

Figure14-3.IrDA Data Modulation (710)

Figure14-4.LIN Message (712)

Figure14-5.LIN Synchronization Field (713)

Figure15-1.SSI Module Block Diagram (769)

Figure15-2.TI Synchronous Serial Frame Format(Single Transfer) (773)

Figure15-3.TI Synchronous Serial Frame Format(Continuous Transfer) (773)

Figure15-4.Freescale SPI Format(Single Transfer)with SPO=0and SPH=0 (774)

Figure15-5.Freescale SPI Format(Continuous Transfer)with SPO=0and SPH=0 (774)

Figure15-6.Freescale SPI Frame Format with SPO=0and SPH=1 (775)

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Stellaris?LM3S5R31Microcontroller Figure15-7.Freescale SPI Frame Format(Single Transfer)with SPO=1and SPH=0 (776)

Figure15-8.Freescale SPI Frame Format(Continuous Transfer)with SPO=1and SPH=0 (776)

Figure15-9.Freescale SPI Frame Format with SPO=1and SPH=1 (777)

Figure15-10.MICROWIRE Frame Format(Single Frame) (778)

Figure15-11.MICROWIRE Frame Format(Continuous Transfer) (779)

Figure15-12.MICROWIRE Frame Format,SSIFss Input Setup and Hold Requirements (779)

Figure16-1.I2C Block Diagram (811)

Figure16-2.I2C Bus Configuration (812)

Figure16-3.START and STOP Conditions (813)

a070875f2b160b4e767fcf44plete Data Transfer with a7-Bit Address (813)

Figure16-5.R/S Bit in First Byte (814)

Figure16-6.Data Validity During Bit Transfer on the I2C Bus (814)

Figure16-7.Master Single TRANSMIT (818)

Figure16-8.Master Single RECEIVE (819)

Figure16-9.Master TRANSMIT with Repeated START (820)

Figure16-10.Master RECEIVE with Repeated START (821)

Figure16-11.Master RECEIVE with Repeated START after TRANSMIT with Repeated

START (822)

Figure16-12.Master TRANSMIT with Repeated START after RECEIVE with Repeated

START (823)

Figure16-13.Slave Command Sequence (824)

Figure17-1.I2S Block Diagram (849)

Figure17-2.I2S Data Transfer (852)

Figure17-3.Left-Justified Data Transfer (852)

Figure17-4.Right-Justified Data Transfer (852)

Figure18-1.CAN Controller Block Diagram (886)

Figure18-2.CAN Data/Remote Frame (888)

Figure18-3.Message Objects in a FIFO Buffer (896)

Figure18-4.CAN Bit Time (900)

a070875f2b160b4e767fcf44B Module Block Diagram (935)

Figure20-1.Analog Comparator Module Block Diagram (1004)

Figure20-2.Structure of Comparator Unit (1006)

a070875f2b160b4e767fcf44parator Internal Reference Structure (1007)

Figure21-1.PWM Module Diagram (1019)

Figure21-2.PWM Generator Block Diagram (1019)

Figure21-3.PWM Count-Down Mode (1024)

Figure21-4.PWM Count-Up/Down Mode (1024)

Figure21-5.PWM Generation Example In Count-Up/Down Mode (1025)

Figure21-6.PWM Dead-Band Generator (1025)

Figure22-1.QEI Block Diagram (1096)

Figure22-2.Quadrature Encoder and Velocity Prepider Operation (1099)

Figure23-1.100-Pin LQFP Package Pin Diagram (1118)

Figure23-2.108-Ball BGA Package Pin Diagram(Top View) (1119)

Figure26-1.Load Conditions (1197)

Figure26-2.JTAG Test Clock Input Timing (1198)

Figure26-3.JTAG Test Access Port(TAP)Timing (1198)

Figure26-4.Power-On Reset Timing (1199)

Figure26-5.Brown-Out Reset Timing (1199)

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Figure26-6.Power-On Reset and Voltage Parameters (1200)

Figure26-7.External Reset Timing(RST) (1200)

Figure26-8.Software Reset Timing (1200)

Figure26-9.Watchdog Reset Timing (1201)

Figure26-10.MOSC Failure Reset Timing (1201)

Figure26-11.Hibernation Module Timing with Internal Oscillator Running in Hibernation (1206)

Figure26-12.Hibernation Module Timing with Internal Oscillator Stopped in Hibernation (1206)

Figure26-13.SDRAM Initialization and Load Mode Register Timing (1208)

Figure26-14.SDRAM Read Timing (1208)

Figure26-15.SDRAM Write Timing (1209)

Figure26-16.Host-Bus8/16Mode Read Timing (1210)

Figure26-17.Host-Bus8/16Mode Write Timing (1210)

Figure26-18.Host-Bus8/16Mode Muxed Read Timing (1211)

Figure26-19.Host-Bus8/16Mode Muxed Write Timing (1211)

Figure26-20.General-Purpose Mode Read and Write Timing (1212)

Figure26-21.General-Purpose Mode iRDY Timing (1212)

Figure26-22.ADC Input Equivalency Diagram (1214)

Figure26-23.SSI Timing for TI Frame Format(FRF=01),Single Transfer Timing

Measurement (1215)

Figure26-24.SSI Timing for MICROWIRE Frame Format(FRF=10),Single Transfer (1215)

Figure26-25.SSI Timing for SPI Frame Format(FRF=00),with SPH=1 (1216)

Figure26-26.I2C Timing (1217)

Figure26-27.I2S Master Mode Transmit Timing (1217)

Figure26-28.I2S Master Mode Receive Timing (1218)

Figure26-29.I2S Slave Mode Transmit Timing (1218)

Figure26-30.I2S Slave Mode Receive Timing (1218)

Figure C-1.Stellaris LM3S5R31100-Pin LQFP Package Dimensions (1266)

Figure C-2.100-Pin LQFP Tray Dimensions (1268)

Figure C-3.100-Pin LQFP Tape and Reel Dimensions (1269)

Figure C-4.Stellaris LM3S5R31108-Ball BGA Package Dimensions (1270)

Figure C-5.108-Ball BGA Tray Dimensions (1272)

Figure C-6.108-Ball BGA Tape and Reel Dimensions (1273)

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Stellaris?LM3S5R31Microcontroller

List of Tables

Table1.Revision History (36)

Table2.Documentation Conventions (48)

Table2-1.Summary of Processor Mode,Privilege Level,and Stack Use (78)

Table2-2.Processor Register Map (79)

Table2-3.PSR Register Combinations (84)

Table2-4.Memory Map (92)

Table2-5.Memory Access Behavior (95)

Table2-6.SRAM Memory Bit-Banding Regions (97)

Table2-7.Peripheral Memory Bit-Banding Regions (97)

Table2-8.Exception Types (103)

Table2-9.Interrupts (104)

Table2-10.Exception Return Behavior (109)

Table2-11.Faults (109)

Table2-12.Fault Status and Fault Address Registers (111)

Table2-13.Cortex-M3Instruction Summary (113)

Table3-1.Core Peripheral Register Regions (116)

Table3-2.Memory Attributes Summary (119)

Table3-3.TEX,S,C,and B Bit Field Encoding (122)

Table3-4.Cache Policy for Memory Attribute Encoding (123)

Table3-5.AP Bit Field Encoding (123)

Table3-6.Memory Region Attributes for Stellaris Microcontrollers (123)

Table3-7.Peripherals Register Map (124)

Table3-8.Interrupt Priority Levels (151)

Table3-9.Example SIZE Field Values (179)

Table4-1.JTAG_SWD_SWO Signals(100LQFP) (183)

Table4-2.JTAG_SWD_SWO Signals(108BGA) (184)

Table4-3.JTAG Port Pins State after Power-On Reset or RST assertion (185)

Table4-4.JTAG Instruction Register Commands (190)

Table5-1.System Control&Clocks Signals(100LQFP) (194)

Table5-2.System Control&Clocks Signals(108BGA) (194)

Table5-3.Reset Sources (195)

Table5-4.Clock Source Options (202)

Table5-5.Possible System Clock Frequencies Using the SYSDIV Field (205)

Table5-6.Examples of Possible System Clock Frequencies Using the SYSDIV2Field (205)

Table5-7.Examples of Possible System Clock Frequencies with DIV400=1 (206)

Table5-8.System Control Register Map (211)

Table5-9.RCC2Fields that Override RCC Fields (232)

Table6-1.Hibernate Signals(100LQFP) (302)

Table6-2.Hibernate Signals(108BGA) (303)

Table6-3.Hibernation Module Clock Operation (309)

Table6-4.Hibernation Module Register Map (311)

Table7-1.Flash Memory Protection Policy Combinations (332)

a070875f2b160b4e767fcf44er-Programmable Flash Memory Resident Registers (336)

Table7-3.Flash Register Map (336)

Table8-1.μDMA Channel Assignments (367)

Table8-2.Request Type Support (369)

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Table8-3.Control Structure Memory Map (370)

Table8-4.Channel Control Structure (370)

Table8-5.μDMA Read Example:8-Bit Peripheral (379)

Table8-6.μDMA Interrupt Assignments (380)

Table8-7.Channel Control Structure Offsets for Channel30 (381)

Table8-8.Channel Control Word Configuration for Memory Transfer Example (381)

Table8-9.Channel Control Structure Offsets for Channel7 (382)

Table8-10.Channel Control Word Configuration for Peripheral Transmit Example (383)

Table8-11.Primary and Alternate Channel Control Structure Offsets for Channel8 (384)

Table8-12.Channel Control Word Configuration for Peripheral Ping-Pong Receive

Example (385)

Table8-13.μDMA Register Map (386)

Table9-1.GPIO Pins With Non-Zero Reset Values (424)

Table9-2.GPIO Pins and Alternate Functions(100LQFP) (424)

Table9-3.GPIO Pins and Alternate Functions(108BGA) (426)

Table9-4.GPIO Pad Configuration Examples (432)

Table9-5.GPIO Interrupt Configuration Example (433)

Table9-6.GPIO Pins With Non-Zero Reset Values (434)

Table9-7.GPIO Register Map (434)

Table9-8.GPIO Pins With Non-Zero Reset Values (447)

Table9-9.GPIO Pins With Non-Zero Reset Values (453)

Table9-10.GPIO Pins With Non-Zero Reset Values (455)

Table9-11.GPIO Pins With Non-Zero Reset Values (458)

Table9-12.GPIO Pins With Non-Zero Reset Values (465)

Table10-1.External Peripheral Interface Signals(100LQFP) (481)

Table10-2.External Peripheral Interface Signals(108BGA) (482)

Table10-3.EPI SDRAM Signal Connections (487)

Table10-4.Capabilities of Host Bus8and Host Bus16Modes (491)

Table10-5.EPI Host-Bus8Signal Connections (492)

Table10-6.EPI Host-Bus16Signal Connections (494)

Table10-7.EPI General Purpose Signal Connections (503)

Table10-8.External Peripheral Interface(EPI)Register Map (509)

Table11-1.Available CCP Pins (553)

Table11-2.General-Purpose Timers Signals(100LQFP) (554)

Table11-3.General-Purpose Timers Signals(108BGA) (555)

Table11-4.General-Purpose Timer Capabilities (556)

Table11-5.Counter Values When the Timer is Enabled in Periodic or One-Shot Modes (557)

Table11-6.16-Bit Timer With Prescaler Configurations (558)

Table11-7.Counter Values When the Timer is Enabled in RTC Mode (559)

Table11-8.Counter Values When the Timer is Enabled in Input Edge-Count Mode (560)

Table11-9.Counter Values When the Timer is Enabled in Input Event-Count Mode (561)

Table11-10.Counter Values When the Timer is Enabled in PWM Mode (562)

Table11-11.Timers Register Map (567)

Table12-1.Watchdog Timers Register Map (602)

Table13-1.ADC Signals(100LQFP) (626)

Table13-2.ADC Signals(108BGA) (627)

Table13-3.Samples and FIFO Depth of Sequencers (628)

Table13-4.Differential Sampling Pairs (635)

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Stellaris?LM3S5R31Microcontroller Table13-5.ADC Register Map (644)

Table14-1.UART Signals(100LQFP) (706)

Table14-2.UART Signals(108BGA) (706)

Table14-3.Flow Control Mode (711)

Table14-4.UART Register Map (717)

Table15-1.SSI Signals(100LQFP) (770)

Table15-2.SSI Signals(108BGA) (770)

Table15-3.SSI Register Map (781)

Table16-1.I2C Signals(100LQFP) (811)

Table16-2.I2C Signals(108BGA) (811)

Table16-3.Examples of I2C Master Timer Period versus Speed Mode (815)

Table16-4.Inter-Integrated Circuit(I2C)Interface Register Map (825)

Table16-5.Write Field Decoding for I2CMCS[3:0]Field (831)

Table17-1.I2S Signals(100LQFP) (850)

Table17-2.I2S Signals(108BGA) (850)

Table17-3.I2S Transmit FIFO Interface (853)

Table17-4.Crystal Frequency(Values from3.5795MHz to5MHz) (854)

Table17-5.Crystal Frequency(Values from5.12MHz to8.192MHz) (854)

Table17-6.Crystal Frequency(Values from10MHz to14.3181MHz) (855)

Table17-7.Crystal Frequency(Values from16MHz to16.384MHz) (855)

Table17-8.I2S Receive FIFO Interface (857)

Table17-9.Audio Formats Configuration (859)

Table17-10.Inter-Integrated Circuit Sound(I2S)Interface Register Map (860)

Table18-1.Controller Area Network Signals(100LQFP) (887)

Table18-2.Controller Area Network Signals(108BGA) (887)

Table18-3.Message Object Configurations (893)

Table18-4.CAN Protocol Ranges (900)

Table18-5.CANBIT Register Values (900)

Table18-6.CAN Register Map (904)

a070875f2b160b4e767fcf44B Signals(100LQFP) (936)

a070875f2b160b4e767fcf44B Signals(108BGA) (936)

Table19-3.Remainder(MAXLOAD/4) (942)

Table19-4.Actual Bytes Read (942)

Table19-5.Packet Sizes That Clear RXRDY (942)

Table19-6.Universal Serial Bus(USB)Controller Register Map (943)

Table20-1.Analog Comparators Signals(100LQFP) (1005)

Table20-2.Analog Comparators Signals(108BGA) (1005)

Table20-3.Internal Reference Voltage and ACREFCTL Field Values (1007)

Table20-4.Analog Comparators Register Map (1009)

Table21-1.PWM Signals(100LQFP) (1020)

Table21-2.PWM Signals(108BGA) (1021)

Table21-3.PWM Register Map (1029)

Table22-1.QEI Signals(100LQFP) (1096)

Table22-2.QEI Signals(108BGA) (1097)

Table22-3.QEI Register Map (1101)

Table24-1.GPIO Pins With Default Alternate Functions (1120)

Table24-2.Signals by Pin Number (1121)

Table24-3.Signals by Signal Name (1132)

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Table24-4.Signals by Function,Except for GPIO (1142)

Table24-5.GPIO Pins and Alternate Functions (1151)

Table24-6.Possible Pin Assignments for Alternate Functions (1154)

Table24-7.Signals by Pin Number (1157)

Table24-8.Signals by Signal Name (1169)

Table24-9.Signals by Function,Except for GPIO (1179)

Table24-10.GPIO Pins and Alternate Functions (1187)

Table24-11.Possible Pin Assignments for Alternate Functions (1190)

Table24-12.Connections for Unused Signals(100-Pin LQFP) (1193)

Table24-13.Connections for Unused Signals(108-Ball BGA) (1193)

Table25-1.Temperature Characteristics (1195)

Table25-2.Thermal Characteristics (1195)

Table25-3.ESD Absolute Maximum Ratings (1195)

Table26-1.Maximum Ratings (1196)

Table26-2.Recommended DC Operating Conditions (1196)

Table26-3.JTAG Characteristics (1197)

Table26-4.Power Characteristics (1199)

Table26-5.Reset Characteristics (1200)

Table26-6.LDO Regulator Characteristics (1201)

Table26-7.Phase Locked Loop(PLL)Characteristics (1201)

Table26-8.Actual PLL Frequency (1202)

Table26-9.PIOSC Clock Characteristics (1202)

Table26-10.30-kHz Clock Characteristics (1202)

Table26-11.Hibernation Clock Characteristics (1203)

Table26-12.HIB Oscillator Input Characteristics (1203)

Table26-13.Main Oscillator Clock Characteristics (1203)

Table26-14.Supported MOSC Crystal Frequencies (1203)

Table26-15.System Clock Characteristics with ADC Operation (1204)

Table26-16.System Clock Characteristics with USB Operation (1204)

Table26-17.Sleep Modes AC Characteristics (1204)

Table26-18.Hibernation Module Battery Characteristics (1205)

Table26-19.Hibernation Module AC Characteristics (1205)

Table26-20.Flash Memory Characteristics (1206)

Table26-21.GPIO Module Characteristics (1206)

Table26-22.EPI SDRAM Characteristics (1207)

Table26-23.EPI SDRAM Interface Characteristics (1207)

Table26-24.EPI Host-Bus8and Host-Bus16Interface Characteristics (1209)

Table26-25.EPI General-Purpose Interface Characteristics (1211)

Table26-26.ADC Characteristics (1213)

Table26-27.ADC Module External Reference Characteristics (1214)

Table26-28.ADC Module Internal Reference Characteristics (1214)

Table26-29.SSI Characteristics (1214)

Table26-30.I2C Characteristics (1216)

Table26-31.I2S Master Clock(Receive and Transmit) (1217)

Table26-32.I2S Slave Clock(Receive and Transmit) (1217)

Table26-33.I2S Master Mode (1217)

Table26-34.I2S Slave Mode (1218)

a070875f2b160b4e767fcf44B Controller Characteristics (1219)

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Stellaris?LM3S5R31Microcontroller Table26-36.Analog Comparator Characteristics (1219)

Table26-37.Analog Comparator Voltage Reference Characteristics (1219)

Table26-38.Nominal Power Consumption (1219)

Table26-39.Detailed Current Specifications (1220)

Table26-40.Hibernation Detailed Current Specifications (1221)

Table B-1.Part Ordering Information (1264)

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Table of Contents

List of Registers

The Cortex-M3Processor (73)

Register1:Cortex General-Purpose Register0(R0) (80)

Register2:Cortex General-Purpose Register1(R1) (80)

Register3:Cortex General-Purpose Register2(R2) (80)

Register4:Cortex General-Purpose Register3(R3) (80)

Register5:Cortex General-Purpose Register4(R4) (80)

Register6:Cortex General-Purpose Register5(R5) (80)

Register7:Cortex General-Purpose Register6(R6) (80)

Register8:Cortex General-Purpose Register7(R7) (80)

Register9:Cortex General-Purpose Register8(R8) (80)

Register10:Cortex General-Purpose Register9(R9) (80)

Register11:Cortex General-Purpose Register10(R10) (80)

Register12:Cortex General-Purpose Register11(R11) (80)

Register13:Cortex General-Purpose Register12(R12) (80)

Register14:Stack Pointer(SP) (81)

Register15:Link Register(LR) (82)

Register16:Program Counter(PC) (83)

Register17:Program Status Register(PSR) (84)

Register18:Priority Mask Register(PRIMASK) (88)

Register19:Fault Mask Register(FAULTMASK) (89)

Register20:Base Priority Mask Register(BASEPRI) (90)

Register21:Control Register(CONTROL) (91)

Cortex-M3Peripherals (116)

Register1:SysTick Control and Status Register(STCTRL),offset0x010 (127)

Register2:SysTick Reload Value Register(STRELOAD),offset0x014 (129)

Register3:SysTick Current Value Register(STCURRENT),offset0x018 (130)

Register4:Interrupt0-31Set Enable(EN0),offset0x100 (131)

Register5:Interrupt32-54Set Enable(EN1),offset0x104 (132)

Register6:Interrupt0-31Clear Enable(DIS0),offset0x180 (133)

Register7:Interrupt32-54Clear Enable(DIS1),offset0x184 (134)

Register8:Interrupt0-31Set Pending(PEND0),offset0x200 (135)

Register9:Interrupt32-54Set Pending(PEND1),offset0x204 (136)

Register10:Interrupt0-31Clear Pending(UNPEND0),offset0x280 (137)

Register11:Interrupt32-54Clear Pending(UNPEND1),offset0x284 (138)

Register12:Interrupt0-31Active Bit(ACTIVE0),offset0x300 (139)

Register13:Interrupt32-54Active Bit(ACTIVE1),offset0x304 (140)

Register14:Interrupt0-3Priority(PRI0),offset0x400 (141)

Register15:Interrupt4-7Priority(PRI1),offset0x404 (141)

Register16:Interrupt8-11Priority(PRI2),offset0x408 (141)

Register17:Interrupt12-15Priority(PRI3),offset0x40C (141)

Register18:Interrupt16-19Priority(PRI4),offset0x410 (141)

Register19:Interrupt20-23Priority(PRI5),offset0x414 (141)

Register20:Interrupt24-27Priority(PRI6),offset0x418 (141)

Register21:Interrupt28-31Priority(PRI7),offset0x41C (141)

Register22:Interrupt32-35Priority(PRI8),offset0x420 (141)

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Stellaris?LM3S5R31Microcontroller Register23:Interrupt36-39Priority(PRI9),offset0x424 (141)

Register24:Interrupt40-43Priority(PRI10),offset0x428 (141)

Register25:Interrupt44-47Priority(PRI11),offset0x42C (141)

Register26:Interrupt48-51Priority(PRI12),offset0x430 (141)

Register27:Interrupt52-54Priority(PRI13),offset0x434 (141)

Register28:Software Trigger Interrupt(SWTRIG),offset0xF00 (143)

Register29:Auxiliary Control(ACTLR),offset0x008 (144)

Register30:CPU ID Base(CPUID),offset0xD00 (146)

Register31:Interrupt Control and State(INTCTRL),offset0xD04 (147)

Register32:Vector Table Offset(VTABLE),offset0xD08 (150)

Register33:Application Interrupt and Reset Control(APINT),offset0xD0C (151)

Register34:System Control(SYSCTRL),offset0xD10 (153)

Register35:Configuration and Control(CFGCTRL),offset0xD14 (155)

Register36:System Handler Priority1(SYSPRI1),offset0xD18 (157)

Register37:System Handler Priority2(SYSPRI2),offset0xD1C (158)

Register38:System Handler Priority3(SYSPRI3),offset0xD20 (159)

Register39:System Handler Control and State(SYSHNDCTRL),offset0xD24 (160)

Register40:Configurable Fault Status(FAULTSTAT),offset0xD28 (164)

Register41:Hard Fault Status(HFAULTSTAT),offset0xD2C (170)

Register42:Memory Management Fault Address(MMADDR),offset0xD34 (171)

Register43:Bus Fault Address(FAULTADDR),offset0xD38 (172)

Register44:MPU Type(MPUTYPE),offset0xD90 (173)

Register45:MPU Control(MPUCTRL),offset0xD94 (174)

Register46:MPU Region Number(MPUNUMBER),offset0xD98 (176)

Register47:MPU Region Base Address(MPUBASE),offset0xD9C (177)

Register48:MPU Region Base Address Alias1(MPUBASE1),offset0xDA4 (177)

Register49:MPU Region Base Address Alias2(MPUBASE2),offset0xDAC (177)

Register50:MPU Region Base Address Alias3(MPUBASE3),offset0xDB4 (177)

Register51:MPU Region Attribute and Size(MPUATTR),offset0xDA0 (179)

Register52:MPU Region Attribute and Size Alias1(MPUATTR1),offset0xDA8 (179)

Register53:MPU Region Attribute and Size Alias2(MPUATTR2),offset0xDB0 (179)

Register54:MPU Region Attribute and Size Alias3(MPUATTR3),offset0xDB8 (179)

System Control (194)

Register1:Device Identification0(DID0),offset0x000 (213)

Register2:Brown-Out Reset Control(PBORCTL),offset0x030 (215)

Register3:Raw Interrupt Status(RIS),offset0x050 (216)

Register4:Interrupt Mask Control(IMC),offset0x054 (218)

Register5:Masked Interrupt Status and Clear(MISC),offset0x058 (220)

Register6:Reset Cause(RESC),offset0x05C (222)

Register7:Run-Mode Clock Configuration(RCC),offset0x060 (224)

Register8:XTAL to PLL Translation(PLLCFG),offset0x064 (229)

Register9:GPIO High-Performance Bus Control(GPIOHBCTL),offset0x06C (230)

Register10:Run-Mode Clock Configuration2(RCC2),offset0x070 (232)

Register11:Main Oscillator Control(MOSCCTL),offset0x07C (235)

Register12:Deep Sleep Clock Configuration(DSLPCLKCFG),offset0x144 (236)

Register13:Precision Internal Oscillator Calibration(PIOSCCAL),offset0x150 (238)

Register14:Precision Internal Oscillator Statistics(PIOSCSTAT),offset0x154 (240)

Register15:I2S MCLK Configuration(I2SMCLKCFG),offset0x170 (241)

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