微电子工艺习题参考解答

CRYSTAL GROWTH AND EXPITAXY

1．画出一50cm长的单晶硅锭距离籽晶10cm、20cm、30cm、40cm、45cm时砷的掺杂分布。（单晶硅锭从融体中拉出时，初始的掺杂浓度为1017cm-3） 2．硅的晶格常数为5.43?．假设为一硬球模型： (a)计算硅原子的半径。

(b)确定硅原子的浓度为多少(单位为cm-3)?

(c)利用阿伏伽德罗(Avogadro)常数求出硅的密度。

3．假设有一l0kg的纯硅融体，当硼掺杂的单晶硅锭生长到一半时，希望得到0.01 Ω·cm的电阻率，则需要加总量是多少的硼去掺杂?

4．一直径200mm、厚1mm的硅晶片，含有5.41mg的硼均匀分布在替代位置上，求： (a)硼的浓度为多少?

(b)硼原子间的平均距离。

5．用于柴可拉斯基法的籽晶，通常先拉成一小直径(5.5mm)的狭窄颈以作为无位错生长的开始。如果硅的临界屈服强度为2×106g/cm2，试计算此籽晶可以支撑的200mm直径单晶硅锭的最大长度。

6．在利用柴可拉斯基法所生长的晶体中掺入硼原子，为何在尾端的硼原子浓度会比籽晶端的浓度高?

7．为何晶片中心的杂质浓度会比晶片周围的大?

8．对柴可拉斯基技术，在k0=0.05时，画出Cs/C0值的曲线。 9．利用悬浮区熔工艺来提纯一含有镓且浓度为5×1016cm-3的单晶硅锭。一次悬浮区熔通过，熔融带长度为2cm，则在离多远处镓的浓度会低于5×1015cm-3？

10．从式Cs/C0?1?(1?k)e?kx/L，假设ke=0.3，求在x/L=1和2时，Cs/C0的值。 11．如果用如右图所示的硅材料制造p+-n突变结二极管，试求用传统的方法掺杂和用中子辐照硅的击穿电压改变的百分比。

12．由图10.10，若Cm=20％，在Tb时，还剩下多少比例的液体?

13．用图10.11解释为何砷化镓液体总会变成含镓比较多?

14．空隙ns的平衡浓度为

Nexp[-Es/(kT)]，N为半导体原子的浓度，而Es为形成能量。计算硅在27℃、900℃和1 200℃的ns (假设Es=2.3eV)． 15．假设弗兰克尔缺陷的形成能量(Ef)

为1.1eV，计算在27℃、900℃时的缺陷密度．弗兰克尔缺陷的平衡密度是错误！未找到

错误！未找到引用源。

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引用源。，其中N为硅原子的浓度(cm-3)，N’为可用的间隙位置浓度(cm-3)，可表示为N’=1×1027错误！未找到引用源。cm-3．

16．在直径为300mm的晶片上，可以放多少面积为400mm2的芯片？解释你对芯片形 状和在周围有多少闲置面积的假设．

17．求在300K时，空气分子的平均速率(空气相对分子质量为29)．

图 10.10. Phase diagram for the gallium- 图 10.11. Partial pressure of gallium and arsenic arsenic system. over gallium arsenide as a function of temperature.

Also shown is the partial pressure of silicon. 18．淀积腔中蒸发源和晶片的距离为15cm，估算当此距离为蒸发源分子的平均自由程的10％时系统的气压为多少?

19．求在紧密堆积下(即每个原子和其他六个邻近原子相接)，形成单原子层所需的每单位面积原子数Ns．假设原子直径d为4.68?．

20．假设一喷射炉几何尺寸为A=5cm2及L=12cm．

(a)计算在970℃下装满砷化镓的喷射炉中，镓的到达速率和MBE的生长速率； (b)利用同样形状大小且工作在700℃，用锡做的喷射炉来生长，试计算锡在如前述砷化镓生长速率下的掺杂浓度(假设锡会完全进入前述速率生长的砷化镓中，锡的摩尔质量为118.69；在700℃时，锡的压强为2.66×10-6Pa)．

21．求铟原子的最大比例，即生长在砷化镓衬底上而且并无任何错配的位错的GaxIn1-xAs薄膜的x值，假定薄膜的厚度是10nm．

22．薄膜晶格的错配f定义为，f=[a0(s)-a0(f)]/a0(f)≡△a0/a0。a0(s)和a0(f)分别为衬底和薄膜在未形变时的晶格常数，求出InAs-GaAs和Ge-Si系统的f值． Solution

错误！未找到引用源。

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1. C0 = 1017 cm-3 k0(As in Si) = 0.3

CS= k0C0(1 - M/M0)k0-1

= 0.3?1017(1- x)-0.7 = 3?1016/(1 - l/50)0.7

x l (cm) CS (cm-3) 0 0 3?1016 0.2 10 3.5?1016 161412108642000.4 0.6 0.8 20 30 40 16164.28?10 5.68?10 1.07?1017 0.9 45 1.5?1017 ND (1016 cm-3)1020304050l (cm)

2. (a) The radius of a silicon atom can be expressed as

r?3a8

3?5.43?1.175?8(b) The numbers of Si atom in its diamond structure are 8. So the density of silicon atoms is

88223 n?3??5.0?10 atoms/cm3a(5.43?)so r?(c) The density of Si is

??M/6.02?10231/n?28.09?5?10226.02?1023 g / cm3 = 2.33 g / cm3.

3. k0 = 0.8 for boron in silicon

M / M0 = 0.5

The density of Si is 2.33 g / cm3.

The acceptor concentration for ? = 0.01 ?–cm is 9?1018 cm-3. The doping concentration CS is given by

Mk0?1Cs?k0C0(1?)

M0Therefore

错误！未找到引用源。 3

Cs9?1018C0??Mk0?10.8(1?0.5)?0.2k0(1?)M0

?9.8?1018cm?3The amount of boron required for a 10 kg charge is

10,000?9.8?1018?4.2?1022 boron atoms 2.338So that

4.2?1022atoms10.8g/mole??0.75g boron. 236.02?10atoms/mole4. (a) The molecular weight of boron is 10.81.

The boron concentration can be given as

nb?number of boron atomsvolume of silicon wafer5.41?10?3g/10.81g?6.02?1023 ? 210.0?3.14?0.13 ?9.78?1018atoms/cm

(b) The average occupied volume of everyone boron atoms in the wafer is

113 V??cm18nb9.78?10 We assume the volume is a sphere, so the radius of the sphere ( r ) is the average distance between two boron atoms. Then

3V?2.9?10?7cm. 4?5. The cross-sectional area of the seed is

r??0.55?2????0.24 cm ?2?The maximum weight that can be supported by the seed equals the product of the critical yield strength and the seed’s cross-sectional area: (2?106)?0.24?4.8?105g?480 kg The corresponding weight of a 200-mm-diameter ingot with length l is

22

?20.0?(2.33g/cm3)?? g?l?480000 2?? ? l?656 cm?6.56 m.6. The segregation coefficient of boron in silicon is 0.72. It is smaller than unity, so the solubility

错误！未找到引用源。

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of B in Si under solid phase is smaller than that of the melt. Therefore, the excess B atoms will be thrown-off into the melt, then the concentration of B in the melt will be increased. The tail-end of the crystal is the last to solidify. Therefore, the concentration of B in the tail-end of grown crystal will be higher than that of seed-end. 7. The reason is that the solubility in the melt is proportional to the temperature, and the temperature is higher in the center part than at the perimeter. Therefore, the solubility is higher in the center part, causing a higher impurity concentration there. 8. We have ?M?Cs/C0?k0??1?M??0??Fractional 0 0.2 solidified

k0?1 0.4 0.6 0.8 1.0 Cs/C0 0.05 0.06 0.08 0.12 0.23 ? Cs/Co0.210.110.0100.20.40.60.81Fraction Solidified9. The segregation coefficient of Ga in Si is 8 ?10-3

From Eq. 18

Cs/C0?1?(1?k)e?kx/L

We have

L?1?kx? ln?k??1?Cs/C0

????? ????21?8?10?3 ? ln?-3?1?5?1015/5?10168?10? ?250 ln(1.102) ?24 cm.10. We have from Eq.18

Cs?C0[1?(1?ke)exp(?kex/L)]

错误！未找到引用源。

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So the ratio Cs/C0?[1?(1?ke)exp(?kex/L)]

= 1?(1?0.3)?exp(?0.3?1)?0.52 at x/L?1 = 0.38 at x/L = 2.

11. For the conventionally-doped silicon, the resistivity varies from 120 ?-cm to 155 ?-cm. The

corresponding doping concentration varies from 2.5?1013 to 4?1013 cm-3. Therefore the range of breakdown voltages of p+ - n junctions is given by

VB??sEc22q(NB)?11.05?10?12?(3?105)2?117?(N)?2.9?10/NB?7250 to 11600 VB?192?1.6?10?VB?11600?7250?4350 V

??V???B?/7250??30% ?2?For the neutron irradiated silicon, ? = 148 ? 1.5 ?-cm. The doping concentration is 3?1013 (?1%). The range of breakdown voltage is

VB?1.3?1017/NB?2.9?1017/3?1013(?1%)?9570 to 9762 V .?VB?9762?9570?192 V

??V???B?/9570??1%. ?2?Msweight of GaAs at TbCm?Cls??? Mlweight of liquid at TbCs?Cml12. We have

Therefore, the fraction of liquid remained f can be obtained as following

Mll30 f????0.65.

Ms?Mls?l16?3013. From the Fig.11, we find the vapor pressure of As is much higher than that of the Ga.

Therefore, the As content will be lost when the temperature is increased. Thus the composition of liquid GaAs always becomes gallium rich. 14. ns?Nexp(?Es/kT)?5?1022exp(2.3 eV/kT)?5?1022exp???88.8?? (T/300)?? = 1.23?10?16cm?3?0 at 270C ?300 K

at 9000C ?1173 K = 6.7?1012cm?3 错误！未找到引用源。

6

at 12000C ?1473 K. = 6.7?1014cm?3

15. nf?NN`exp(?Ef/2kT)

=5?1022?1?1027e?3.8eV/kT?e?1.1eV/2kT?7.07?1024?e?94.7/(T/300) =5.27?10?17 at 27oC = 300 K

=2.14?1014 at 900oC = 1173 K. 16. 37 ? 4 = 148 chips

In terms of litho-stepper considerations,

there are 500 ?m space tolerance between the mask boundary of two dice. We divide the wafer into four symmetrical parts for convenient dicing, and discard the perimeter parts of the wafer. Usually the quality of the perimeter parts is the worst due to the edge effects. 17. ?av??? ? 0 ? 0vfvdvfvdv?8kT ?M3/24?M?Where f????2kT????M?2?exp???2kT?2??? ?

M: Molecular mass

k: Boltzmann constant = 1.38?10-23 J/k T: The absolute temperature

?: Speed of molecular So that

?av?2?2?1.38?10?23?3004?468 m/sec?4.68?10cm/sec. ?2729?1.67?1018. ??

0.66cm

P( in Pa)0.66?0.66?4.4?10?3 Pa. 150?19. For close-packing arrange, there are 3 pie shaped sections

in the equilateral triangle. Each section corresponds to

错误！未找到引用源。

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?P?d 1/6 of an atom. Therefore

1number of atoms contained in the triangle6 Ns??area of the triangle13d?d223?

=

23d2?23(4.68?10)?82

2 =5.27?1014 atoms/cm.

20. (a) The pressure at 970?C (=1243K) is 2.9?10-1 Pa for Ga and 13 Pa for As2. The

arrival rate is given by the product of the impringement rate and A/?L2 :

?P??A?Arrival rate = 2.64?1020???2?

?MT???L?

??5? = 2.64?10???????122?

??69.72?1243??20?2.9?10?1 = 2.9?1015 Ga molecules/cm2 –s

The growth rate is determined by the Ga arrival rate and is given by

(2.9?1015)?2.8/(6?1014) = 13.5 ?/s = 810 ?/min .

(b) The pressure at 700oC for tin is 2.66?10-6 Pa. The molecular weight is 118.69.

Therefore the arrival rate is

?2.66?10?6??52.64?10??118.69?973?????122???20?102??2.28?10 molecular/cm?s ? If Sn atoms are fully incorporated and active in the Ga sublattice of GaAs, we have an electron concentration of

?2.28?1010 ??2.9?1015???4.42?1022????2???17-3??1.74?10 cm . ??

21. The x value is about 0.25, which is obtained from Fig. 26.

22. The lattice constants for InAs, GaAs, Si and Ge are

6.05, 5.65,5.43, and 5.65 ?, respectively (Appendix F). Therefore, the f value for InAs-GaAs system is

错误！未找到引用源。

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f?(5.65?6.05)6.05??0.066 And for Ge-Si system is

f?(5.43?5.65)5.65??0.39 .

错误！未找到引用源。 9

THERMAL OXIDATION AND FILM DEPOSITION

1．一p型掺杂、方向为<100>的硅晶片，其电阻率为10Ω·cm，置于湿法氧化的系统中，其生长厚度为0.45μm，温度为1 050℃．试决定氧化的时间． 2．习题1中第一次氧化后，在氧化膜上定义一个区域生长栅极氧化膜，其生长条件为1000℃，20 min．试计算栅极氧化膜的厚度及场氧化膜的总厚度． 3．试推导方程式(11)．当时间较长时，可化简为x2=Bt；时间较短时·可化简为x=错误！未找到引用源。．

4．试计算在方向为<100>的硅晶片上，温度980℃及latm下进行干法氧化的扩散系数D．

5．(a)在等离子体式淀积氮化硅的系统中，有20％的氢气，且硅与氮的比值为1.2，试计算淀积SiNxHy，中的x及y．

(b)假设淀积薄膜的电阻率随5×1028exp(-33.3γ)而改变(当2>γ>0·8)，其中γ为与氮的比值．试计算(a)中薄膜的电阻率．

6．SiO2、Si3N4及Ta2O5的介电常数约为3.9、7.6及25．试计算以Ta2O5与SiO2：Si3N4：SiO2作为介质的电容的比值．其中介质厚度均相等，且SiO2：Si3N4：SiO2的比例亦为1：1：1．

7．续习题6，若选择介电常数为500的BST来取代Ta2O5。试计算欲维持相等的电容值，面积所减少的比例．假设两薄膜厚度相等．

8．续习题6，试以SiO2的厚度来计算Ta2O5的等效厚度．假设两者有相同的电容值。

9．在硅烷与氧气的环境下，淀积未掺杂的氧化膜．当温度为425℃时，淀积速率为15nm/min．在多少温度时，淀积速率可提高一倍?

10．磷硅玻璃回流的工艺需高与1000℃．在ULSI中，当器件的尺寸缩小时，必须降低工艺温度．试建议一些方法，可在温度小于900℃的情形下，淀积表面平坦的二氧化硅绝缘层来作为金属层间介质．

11．为何在淀积多晶硅时，通常以硅烷为气体源，而不以硅氯化物为气体源? 12．解释为何一般淀积多晶硅薄膜的温度普遍较低，大约在600℃～650℃之间。 13．一电子束蒸发系统淀积铝以完成MOS电容的制作．若电容的平带电压因电子束辐射而变动0.5V，试计算有多少固定氧化电荷(氧化膜厚度为50nm)?试问如何将这些电荷去除?

14．一金属线长20μm，宽0.25μm，薄层电阻值为

错误！未找到引用源。

10

．请计算此线的电阻值．

15．计算TiSi2与CoSi2的厚度，其中Ti与Co的初始厚度为30nm． 16．比较TiSi2与CoSi2在自对准金属硅化物应用方面的优、缺点．

17．一介质置于两平行金属线间．其长度L=lcm，宽度W=0.28μm，厚度T=0.3μm．两金属间距s为0.36μm.

(a)计算RC时间延迟。假设金属材料为铝，其电阻率为2.67μΩ·cm，介质为氧化膜，其介电常数为3.9．

(b)计算RC时间延迟。假设金属材料为铜，其电阻率为1.7μΩ·cm，介质为有机聚合物，其介电常数为2.8．

(c)比较(a)、(b)中结果，我们可以减少多少RC时间延迟?

18．重复计算习题17(a)及(b)．假设电容的边缘因子(fringing factor)为3，边缘因子是由于电场线分布超出金属线的长度与宽度的区域．

19．为避免电迁移的问题，最大铝导线的电流密度不得超过5×105 A/cm2．假设导线长为2mm,宽为1μm，最小厚度为1μm，此外有20％的线在台阶上，该处厚度为0.5μm．试计算此线的电阻值．假设电阻率为3×10-6Ω·cm．并计算铝线两端可承受的最大电压．

20．在布局金属线时若要使用铜，必须克服以下几点困难：①铜通过二氧化硅层而扩散；②铜与二氧化硅层的附着性；③铜的腐蚀性．有一种解决的方法是使用具有包覆性、附着性的薄膜来保护铜导线．考虑一被包覆的铜导线，其横截面积为0.5μm×0.5μm．与相同尺寸大小的TiN/Al/TiN导线相比(其中上层TiN厚度为40 nm，下层为60 nm)，其最大包覆层的厚度为多少?(假设被包覆的铜线与TiN/A1/TiN线的电阻相等) 1. From Eq. 11 (with τ=0)

x2+Ax = Bt

From Figs. 6 and 7, we obtain B/A =1.5 μm /hr, B=0.47 μm 2/hr, therefore A= 0.31

μm. The time required to grow 0.45μm oxide is

t?121(x?Ax)?(0.452?0.31?0.45)?0.72 hr?44 min. B0.47

2. After a window is opened in the oxide for a second oxidation, the rate constants are

B = 0.01 μm 2/hr, A= 0.116 μm (B/A = 6 ×10-2 μm /hr).

If the initial oxide thickness is 20 nm = 0.02 μm for dry oxidation, the value ofτcan be obtained as followed: (0.02)2 + 0.166(0.02) = 0.01 (0 +τ) or τ= 0.372 hr.

错误！未找到引用源。

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For an oxidation time of 20 min (=1/3 hr), the oxide thickness in the window area is or

x2+ 0.166x = 0.01(0.333+0.372) = 0.007

x = 0.0350 μm = 35 nm (gate oxide).

121(x?Ax)?(0.452?0.166?0.45)?27.72 hr. B0.01For the field oxide with an original thickness 0.45 μm, the effectiveτis given by

τ=

x2+ 0.166x = 0.01(0.333+27.72) = 0.28053

or x = 0.4530 μm (an increase of 0.003μm only for the field oxide). 3. x2 + Ax = B(t??)

A2A2?B(t??) (x?)?24

?A2?A2 (x?)?B ??(t??)?

2?4B?

A2when t >> ?, t >> ,

4B

then, x2 = Bt similarly,

A2when t >> ?, t >> ,

4B then, x =

B(t??) A4. At 980℃(=1253K) and 1 atm, B = 8.5×10-3 μm 2/hr, B/A = 4×10-2 μm /hr (from Figs. 6

and 7). Since A ≡2D/k , B/A = kC0/C1, C0 = 5.2×1016 molecules/cm3 and C1 = 2.2×1022 cm-3 , the diffusion coefficient is given by

D?AkA?BC1????22?AC0?B?C1????2??C?? ??0?

8.5?10?32.2?1022 ? ?m2/hr 1625.2?10 ? 1.79?103?m2/hr ? 4.79?10-9cm2/s.

5. (a) For SiNxHy

错误！未找到引用源。 12

Si1??1.2 Nx∴ x = 0.83

(b) ρ= 5× 1028e-33.3×1.2 = 2× 1011 Ω-cm

As the Si/N ratio increases, the resistivity decreases exponentially. 6.

Set Ta2O5 thickness = 3t, ?1 = 25 SiO2 thickness = t, ?2 = 3.9 Si3N4 thickness = t, ?3 = 7.6, area = A then

??A

CTa2O5?103tatomic % H?100y?20

1?0.83?y ∴ y = 0.46

The empirical formula is SiN0.83H0.46.

1CONOCONO?2?0A?3?0A?2?0A???A?230??2?2?3?t??t?t?tCTa2O5CONO

7. Set

?1??2?2?3?25?3.9?2?7.6???5.37.

3?2?33?3.9?7.6 BST thickness = 3t, ?1 = 500, area = A1

SiO2 thickness = t, ?2 = 3.9, area = A2 Si3N4 thickness = t, ?3 = 7.6, area = A2 then

?1?0A13t??2?3?0A2??2?2?3?tA1?0.0093. A2

8. Let

Ta2O5 thickness = 3t, ?1 = 25 SiO2 thickness = t, ?2 = 3.9

13

错误！未找到引用源。

Si3N4 thickness = t, ?3 = 7.6 area = A then

?1?0A?2?0A?3td 3?td?2?0.468t.?1

9. The deposition rate can be expressed as r = r0 exp (-Ea/kT) where Ea = 0.6 eV for silane-oxygen reaction. Therefore for T1 = 698 K

??1r(T2)1????2?exp ?0.6?? ? ??r(T1)??kT1kT2??0.6??300300??? ??? ? ln 2 = ??0.0259??698T2??

∴ T2 =1030 K= 757 ℃.

10. We can use energy-enhanced CVD methods such as using a focused energy

source or UV lamp. Another method is to use boron doped P-glass which will

reflow at temperatures less than 900℃.

11. Moderately low temperatures are usually used for polysilicon deposition, and

silane decomposition occurs at lower temperatures than that for chloride reactions. In addition, silane is used for better coverage over amorphous materials such SiO2.

12. There are two reasons. One is to minimize the thermal budget of the wafer,

reducing dopant diffusion and material degradation. In addition, fewer gas phase reactions occur at lower temperatures, resulting in smoother and better adhering films. Another reason is that the polysilicon will have small grains. The finer grains are easier to mask and etch to give smooth and uniform edges. However, for temperatures less than 575 oC the deposition rate is too low.

有两个原因。一是减少硅片的热预算，降低掺杂剂扩散和材料的降解。此外，少气相反应在较低的温度下发生，导致更顺畅，更好的粘合膜。另一个原因是，多晶硅将有小颗粒。细颗粒容易掩模蚀刻给光滑和均匀的边缘。然而，温度低于575oC沉积速率太低。

13. The flat-band voltage shift is

错误！未找到引用源。

14

?VFB = 0.5 V ~

Qot C03.9?8.85?10?14?8?2C0???6.9?10F/cm. ?8d500?10∴ Number of fixed oxide charge is

?ox

0.5C00.5?6.9?10?811-2 ??2.1?10cm?19q1.6?10To remove these charges, a 450℃ heat treatment in hydrogen for about 30

minutes is required. 14.

20/0.25 = 80 sqs.

Therefore, the resistance of the metal line is

5?50 = 400 ? .

15. For TiSi2 30 ? 2.37 = 71.1nm

For CoSi2 30 ? 3.56 = 106.8nm.

16. For TiSi2:

Advantage: low resistivity

It can reduce native-oxide layers

TiSi2 on the gate electrode is more resistant to high-field-induced hot-electron degradation.

Disadvantage: bridging effect occurs.

Larger Si consumption during formation of TiSi2

Less thermal stability For CoSi2:

Advantage: low resistivity High temperature stability No bridging effect

A selective chemical etch exits Low shear forces Disadvantage: not a good candidate for polycides

L1?63R???2.67?10??3.2?10?17. (a) ?4?4A0.28?10?0.3?10

?A?TL3.9?8.85?10?14?0.3?10?4?1?104?10?6 C????2.9?10?13F?4dS0.36?10

错误！未找到引用源。

15

RC?3.2?105?2.9?10?15?0.93 ns

(b) R??L13?1.7?10?6??2?10? ?4?4A0.28?10?0.3?10

2.8?8.85?10?14?0.3?10?4?1?13C????2.1?10 F ?4dS0.36?10RC?2?103?2.1?10?13?0.42 ns?A?TL(c) We can decrease the RC delay by 55%. Ratio =

0.42 = 0.45. 093

L1318. (a) R? ? ?2.67 ?10 ?6? ?3.2?10?44A0.28?10?0.3?10

?A?TL3.9?8.85?10?14?0.3?10?4?1?3 ?13C????8.7?10F4dS0.36?10

. = 3.2 ×103 ×8.7 × 10-13 = 2.8 ns. RC

(b) R??L1?1.7?10?6??2?103? 44A0.28?10?0.3?102.8?8.85?10?14?0.3?10?4?1?3?13???6.3?10 F C?4dS0.36?10RC?2?103?8.7?10?13?2.5 ns

3?13RC?3.2?10?8.7?10?2.5 ns.19. (a) The aluminum runner can be considered as two segments connected in series:

?A?TL20% (or 0.4 mm) of the length is half thickness (0.5 μm) and the remaining 1.6 mm is full thickness (1μm). The total resistance is

?????0.16?0.04R???1?2??3?10?6??4? ?4?4?4?AA10?1010?(0.5?10)??2??1 = 72 Ω.

The limiting current I is given by the maximum allowed current density times

cross-sectional area of the thinner conductor sections: I = 5×105 A/cm2× (10-4×0.5×10-4) = 2.5×10-3 A = 2.5 mA. The voltage drop across the whole conductor is then

V?RI?72??2.5?10?3 A= 0.18V. 20.

0.5 ?m 40 nm

Al Cu =

错误！未找到引用源。 0.5 ?m 60 nm

16

h: height , W : width , t : thickness, assume that the resistivities of the cladding layer and TiN are much larger than ?A? and ?Cu

RAl??Al?RCu??Cu??? ?2.7h?W(0.5?0.1)?0.5?? ?1.7h?W(0.5?2t)?(0.5?2t) When RAl?RCu

Then 2.71.70.4?0.5?(0.5?2t)2 ?

t = 0.073 ?m = 73 nm .

错误！未找到引用源。 17

LITHOGRAPHY AND ETHING

1·对等级为100的洁净室，试依粒子大小计算每单位立方米中尘埃粒子总数． (a)0.5μm到1μm； (b)1μm到2μm； (c)比2μm大．

2．试计算一有9道掩模版工艺的最后成品率．其中有4道平均致命缺陷密度为0.1/cm2，4道为0.25cm2。，1道为1.0/cm2．芯片面积为50 mm2．

3．一个光学光刻系统，其曝光功率为0.3mW/cm2。．正性光刻胶要求的曝光能量为140mJ/cm2。，负性光刻胶为9mJ/cm2。．假设忽略装载与卸载晶片的时间，试比较正性光刻胶与负性光刻胶的产率．

4．(a)对波长为193nm的ArF-准分子激光光学光刻系统，其DNA=0.65，k1=0.60，k2=0.50．此光刻机理论的分辨率与聚焦深度为多少?

(b))实际上我们可以如何修正DNA、k1与k2参数来改善分辨率? (c)相移掩模版(PSM)技术改变哪一个参数可改善分辨率? 5．右图为光刻系统的反应曲线(response curves)：

(a)使用较大γ值的光刻胶有何优缺点?

(b)传统的光刻胶为何不能用于248nm或193rim光刻系统? 6．(a)解释在电子束光刻中为何可变形状电子束比高斯电子束拥有较高的产率?

(h)电子束光刻图案如何对准?为何X射线光刻的图案对准如此困难?

(c)X射线光刻比电子束光刻的潜在优点有哪些?

7·(a)为何光学光刻系统的工作模式由邻近影印法进化到投影，最后进化到5：1 的步进重复投影法?

(b)X射线光刻系统是否可能使用重复扫描系统?并说明原因．

错误！未找到引用源。

18

8．如果掩蔽层与衬底不能被某一腐蚀剂腐蚀，试画出下列几种情形薄膜厚度为hf的各向异性腐蚀图案的侧边轮廓； (a)刚好完全腐蚀； (b)100％过度腐蚀； (c)200％过度腐蚀．

9．一个<100>晶向硅晶片，利用KOH溶液腐蚀一个利用二氧化硅当掩蔽层的1.5μm×l.5μm窗，垂直于<100>晶面的腐蚀速率为0.6μm/min．而<100>：<110>：<111>晶面的腐蚀速率比为100：16：1．画出20s、40s与60s的腐蚀轮廓．

10．续上题，一个<110>晶向硅晶片利用薄的SiO2当掩蔽层，在KOH溶液中藕蚀．画出<110>硅的腐蚀轮廓．

11．一个直径150mm<100>晶向硅晶片厚度为625μm．晶片上有1 000μm×1 000μm的IC．这些IC是利用各向异性腐蚀的方式来隔开．试用两种方法来完成此工艺，并计算使用这两种工艺方法损失的面积所占的比例．

12．粒子碰撞平均移动的距离称为平均自由程λ，λ≈5×1 0-3/p(cm)，其中P为压强，单位为Torr．一般常用的等离子体，其反应腔压强范围为1Pa～150Pa．其相关的气体浓度(cm-3)与平均自由程是多少?

13．氟原子(F)刻蚀硅的刻蚀速率为： 刻蚀速率(nm/min)=2.86×10-13×nF×T1/2exp(-Ea/RT)． 其中nF为氟原子的浓度(cm-3)，T为绝对温度(K)，Ea与R分别为激活能(10.416kJ/mol)与气体常数(8.345J?K)．如果nF为3×l015cm-3，试计算室温时硅的刻蚀速率． 1 4．续上题，利用氟原子一样可以刻蚀SiO2，刻蚀速率可表示为 刻蚀速率(nm/min)=0.614×10-13×nF×T1/2exp(-Ea/RT)．

其中nF为3×1015cm-3，Ea为15.12kJ/mol．计算室温时SiO2的刻蚀速率及SiO2对Si的刻蚀选择比．

1 5．可以用多重步骤的刻蚀工艺来刻蚀薄栅极氧化层上的多晶硅栅极．如何设计一个刻蚀工艺使之满足：没有做掩蔽效应(micrornasking)、各向异性刻蚀、对薄的栅极氧化层有适合的选择比?

16．刻蚀400 nm多晶硅而不会移去1 nm厚的底部栅氧化层，试找出所需的刻蚀选择比?假设多晶硅的刻蚀工艺有10％的刻蚀速率均匀度．

17．1 um厚的A1薄膜淀积在平坦的场氧化层区域上．并且利用光刻胶来定义图案．接着金属层利用Helicon刻蚀机，混合BCI3/Cl2气体。在温度为70 oC来刻蚀．A1与光刻胶的刻蚀选择比维持在3．假设有30％的过度刻蚀，试问为确保顶部的金属不被侵蚀·所需光刻胶的最薄厚度为多少?

错误！未找到引用源。

19

18．在ECR等离子体中，一个静磁场B驱使电子沿着磁场随一个角频率ω做圆周运动ωe=qB/me，其中q为电荷、me为电子质量．如果微波的频率为2.45GHz，试问所需的磁场太小为多少?

19．传统的反应离子刻蚀与高密度等离子体(ECR，ICP等)相比，最大的区别是什么? 20．叙述如何消除Al金属线在氯化物等离子体刻蚀后所造成的腐蚀．

1. With reference to Fig. 2 for class 100 clean room we have a total of 3500 particles/m3 with

particle sizes ?0.5 μm

21?3500= 735 particles/m2 with particle sizes? 1.0 μm 1004.5?3500= 157 particles/m2 with particle sizes? 2.0 μm 100Therefore, (a) 3500-735 = 2765 particles/m3 between 0.5 and 1 μm (b) 735-157 = 578 particles/m3 between 1 and 2 μm (c) 157 particles/m3 above 2 μm. 2. Y??e?D1A

n?19A = 50 mm2 = 0.5 cm2

Y?e?4(0.1?0.5)?e?4(0.25?0.5)?e?1(1?0.5)?e?1.2?30.1% .

3. The available exposure energy in an hour is

0.3 mW2/cm2 × 3600 s =1080 mJ/cm2 For positive resist, the throughput is

1080?7 wafers/hr 1401080?120 wafers/hr. 9For negative resist, the throughput is

4. (a) The resolution of a projection system is given by

lm?k1?NA?0.6?0.193μmm ?0.178 μ

0.65DOF?k2?0.193?m?= 0.228 μm ?0.5?22?(NA)?(0.65)??(b) We can increase NA to improve the resolution. We can adopt resolution enhancement

techniques (RET) such as optical proximity correction (OPC) and phase-shifting Masks (PSM). We can also develop new resists that provide lower k1 and higher k2 for better resolution and depth of focus.

(c) PSM technique changes k1 to improve resolution.

错误！未找到引用源。

20

5. (a) Using resists with high ? value can result in a more vertical profile but throughput decreases.

(b) Conventional resists can not be used in deep UV lithography process because these resists

have high absorption and require high dose to be exposed in deep UV. This raises the concern of damage to stepper lens, lower exposure speed and reduced throughput.

6. (a) A shaped beam system enables the size and shape of the beam to be varied, thereby

minimizing the number of flashes required for exposing a given area to be patterned. Therefore, a shaped beam can save time and increase throughput compared to a Gaussian beam.

(b) We can make alignment marks on wafers using e-beam and etch the exposed marks. We can

then use them to do alignment with e-beam radiation and obtain the signal from these marks for wafer alignment.

X-ray lithography is a proximity printing lithography. Its accuracy requirement is very high, therefore alignment is difficult.

(c) X-ray lithography using synchrotron radiation has a high exposure flux so X-ray has better

throughput than e-beam.

7. (a) To avoid the mask damage problem associated with shadow printing, projection printing

exposure tools have been developed to project an image from the mask. With a 1:1 projection printing system is much more difficult to produce defect-free masks than it is with a 5:1 reduction step-and-repeat system. (b) It is not possible. The main reason is that X-rays cannot be focused by an optical lens. When

it is through the reticle. So we can not build a step-and-scan X-ray lithography system.

8. As shown in the figure, the profile for each case is a segment of a circle with origin at the

initial mask-film edge. As overetching proceeds the radius of curvature increases so that the profile tends to a vertical line. 9. (a) 20 sec

0.6 × 20/60 = 0.2 μm…..(100) plane

0.6/16 × 20/60 = 0.0125 μm……..(110) plane 0.6/100 × 20/60 = 0.002 μm…….(111) plane

Wb?W0?2l?1.5?2?0.2?1.22 μm

(b) 40 sec

0.6 × 40/60 = 0.4 μm….(100)plane 0.6/16 × 40/60 = 0.025 μm…. (110) plane 0.6/100 × 40/60 = 0.004 μm…..(111) plane

Wb?W0?2l?1.5?2?0.4= 0.93 μm

(c) 60 sec

21

错误！未找到引用源。

0.6 ×1 = 0.6 μm….(100)plane

0.6/16 ×1 = 0.0375 μm…. (110) plane 0.6/100 ×1= 0.006 μm…..(111) plane

Wb?W0?2l?1.5?2?0.6?0.65 μm.

10. Using the data in Prob. 9, the etched pattern profiles on <100>-Si are shown in below.

(a) 20 sec l = 0.012 μm, W0?Wb?1.5μm (b) 40 sec l = 0.025 μm, W0?Wb?1.5 μm (c) 60 sec l = 0.0375 μm W0?Wb?1.5 μm.

11. If we protect the IC chip areas (e.g. with Si3N4 layer) and etch the wafer from the top, the

width of the bottom surface is

W?W1?2l?1000?2?625?1884μm

The fraction of surface area that is lost is (W2?W12)/W2× 100%=(18842-10002) /18842× 100% = 71.8 %

In terms of the wafer area, we have lost 71.8 % × ?(15/2)2=127 cm2

Another method is to define masking areas on the backside and etch from the back. The width of each square mask centered with respect of IC chip is given by

W?W1?2l?1000?2?625= 116 μm

Using this method, the fraction of the top surface area that is lost can be negligibly small.

12. 1 Pa = 7.52 m Torr PV = nRT 7.52 /760 × 10-3 = n/V ×0.082 × 273 n/V = 4.42 × 10-7 mole/liter = 4.42 × 10-7 × 6.02 × 1023/1000 =2.7 ×1014 cm-3 mean–free–path ??5?10?3/P cm = 5× 10-3 ×1000/ 7.52 = 0.6649 cm = 6649 μm 150Pa = 1128 m Torr

PV = nRT 1128/ 760 × 10-3 = n/V × 0.082 × 273 n/V = 6.63 × 10-5 mole/liter = 6.63 ×10-5×6.02×1023/1000 = 4 × 1016 cm-3 mean-free-path ??5?10?3/Pcm = 5× 10-3 ×1000/1128 = 0.0044 cm = 44 μm. 13. Si Etch Rate (nm/min) = 2.86 × 10 × nF?T

-13

12?Ea?eRT

12 = 2.86 × 10-13 ×3×1015×(298)22

?e?2.48?1031.987?298

错误！未找到引用源。

= 224.7 nm/min.

?3.76?1031.987?29814. SiO2 Etch Rate (nm/min) = 0.614× 10-13 ×3×1015×(298)Etch selectivity of SiO2 over Si =

5.6?0.025 224.712?e = 5.6 nm/min

0.614(?3.76?2.48)1.987?298?e?0.025. Or etch rate (SiO2)/etch rate (Si) =

2.8615. A three–step process is required for polysilicon gate etching. Step 1 is a nonselective etch

process that is used to remove any native oxide on the polysilicon surface. Step 2 is a high polysilicon etch rate process which etches polysilicon with an anisotropic etch profile. Step 3 is a highly selective polysilicon to oxide process which usually has a low polysilicon etch rate. 16. If the etch rate can be controlled to within 10 %, the polysilicon may be etched 10 % longer or

for an equivalent thickness of 40 nm. The selectivity is therefore

40 nm/1 nm = 40.

17. Assuming a 30% overetching, and that the selectivity of Al over the photoresist maintains 3. The

minimum photoresist thickness required is

(1+ 30%) × 1 μm/3 = 0.433 μm = 433.3 nm. 18. ?e?qB me91.6?10?19?B 2??2.45?10? ?319.1?10 B = 8.75 × 10-2(tesla)

= 875 (gauss).

19. Traditional RIE generates low-density plasma (109 cm-3) with high ion energy. ECR and ICP

generate high-density plasma (1011 to 1012 cm-3) with low ion energy. Advantages of ECR and ICP are low etch damage, low microloading, low aspect-ratio dependent etching effect, and simple chemistry. However, ECR and ICP systems are more complicated than traditional RIE systems.

20. The corrosion reaction requires the presence of moisture to proceed. Therefore, the first line of

defense in controlling corrosion is controlling humidity. Low humidity is essential,. especially if

copper containing alloys are being etched. Second is to remove as much chlorine as possible from the wafers before the wafers are exposed to air. Finally, gases such as CF4 and SF6 can be used for fluorine/chlorine exchange reactions and polymeric encapsulation. Thus, Al-Cl bonds are replaced by Al-F bonds. Whereas Al-Cl bonds will react with ambient moisture and start the corrosion process , Al-F bonds are very stable and do not react. Furthermore, fluorine will not catalyze any corrosion reactions.

错误！未找到引用源。 23

DOPING

1．试计算在中性环境中，950oC、30min硼预置掺杂情况的结深与杂质总量．假设衬底是n型硅，ND=1.88×1016cm-3，而硼的表面浓度为Cs=1.8×1020cm-3。 2．如果习题1中的例子放入1 050oC、60min的中性环境进行再分布扩散，试计算扩散分布与结深．

3．假设测得的磷扩散分布可以用高斯函数表示，其扩散系数D=2.3×10-13cm2/s，测出的表面浓度是1×1018cm-3，在衬底浓度为1×1015cm-3下测得的结深为1μm.请计算扩散时间和在扩散层中的全部杂质量．

4．为防止突然降温而引起的硅晶片翘曲，扩散炉管的温度在20min内自1 000oC线性地下降至500oC．对硅内的磷扩散而言，初始扩散温度的有效时间为多少? 5．硅中低浓度磷在1 000oC下再分布，若扩散时间与温度有1%变动，试找出表面浓度变化的比例．

6．在1 100oC将砷扩散到掺有硼的厚硅晶片中(硼浓度为1015cm-3.)，历时3h，如果表面浓度保持恒定在4×1018cm-3，则砷的最后浓度分布、扩散长度及结深为多少?

7．在900oC将砷扩散到掺有硼的厚硅晶片中(硼浓度为1015cm-3)达3h，如果表面浓度恒定在4×1018 cm-3，则结深为多少?假设D=Doexp(一Ea/kT)×(n/ni)，D0=45.8cm2/s，Ea=4．05eV，xj=1.6Dt． 8．解释本征与非本征扩散的意义． 9．定义分凝系数．

10．气相淀积后测得二氧化硅中铜的浓度是5×1013cm-3，在HF/H2O2内溶解之后在硅层内的铜浓度是3×1011cm-3，计算在二氧化硅与硅层内铜的分凝系数. 11．在一个200mm硅晶片硼离子注入系统中，假设离子束电流是10μA．对P沟道晶体管来说，试计算将闯值电压由-1.1V降低到-0.5V所需的注入时间．假设被注入的受主在硅表面的下方形成一层负电荷而氧化层厚度是10nm．

12．假设100mm砷化镓硅晶片在固定离子束电流10μA下均匀地注入100keV的锌离子达5min，请问在单位面积上的离子剂量与离子浓度的峰值．

13．通过氧化层上所开的窗注入80keV的硼到硅中形成p-n结．如果硼的剂量是2×1015cm-2，而n型衬底的浓度是1015cm-3，试找出冶金结的位置．

14．通过厚度为25nm的栅极氧化层进行阈值电压调整注入．衬底是方向为<100>的P型硅，电阻率为10Ω?cm．如果在40keV硼注入下增加的阈值电压是1V，

错误！未找到引用源。

24

计算单位面积的总注入剂量，并估计硼浓度的峰值所在位置． 15．同习题11中的衬底，请问总剂量在硅中所占比例为多少?

16．如果50keV的硼注入进硅衬底，试计算损伤密度．假设硅原子密度为5．02×1022cm-3，硅的移位能量为15eV，范围是2.5nm，硅晶面间距为0.25nm． 17．解释为何高温RTA较低温RTA更适用于形成无缺陷浅结．

18．如果栅极氧化层厚度为4nm，试计算将P沟道闽值电压降低1V所需的注入剂量．

假设注入电压被调整到可使分布的峰值发生在氧化硅与硅的界面上，因此只有一半的注入

离子进入硅中．进而假设硅中90％的注入离子由退火X-艺而激活电特性．这些假设使45%被注入的离子可用于阈值电压调整．同时也假设所有在硅中的电荷都位于硅-二氧化硅界面．

19·我们要在亚微米MOSFET的源极与漏极形成一个0.1μm重掺杂的结．能选择哪几种杂质?注入将其激活的方法有几种?你会推荐哪一种?为什么?

20．当砷以100keV注入而光刻胶的厚度为400nm．试推算此光刻胶掩蔽层防止离子穿透的阻挡率(Rp=0.6μm，σp=0．2μm)．如果光刻胶厚度改为1μm，请计算掩蔽层的阻挡率．

21．当硼离子以200keV注入时，需要多厚的SiO2来阻挡99.999%的入射离子？投影射程为0.53μm，投影偏差为0.093μm 。 1. Ea(boron) = 3.46 eV, D0 = 0.76 cm2/sec

?E?3.46???152From Eq. 6, D?D0exp(a)?0.76exp??4.142?10cm/s ??5kT?8.614?10?1223?

L?Dt?4.142?10?15?1800?2.73?10?6 cm From Eq. 9, C(x)?Cserfc(?? ?If x?0,C(0)?1.8?1020 atoms10-4, C(5× 10-6) = 3.6 × 1019 /cm3; x = 0.05 ×

xx?)?1.8?1020erfc ??62L?5.46?10atoms/cm3; x = 0.075 ×10-4 , C(7.5×10-6) = 9.4 ×1018 atoms/cm3; x = 0.1×10-4,

C(10-5) = 1.8 × 1018 atoms/cm3; x = 0.15× 10-4, C(1.5×10-5) = 1.8× 1016 atoms/cm3.

CThe xj?2Dt (erfc-1sub)?0.15?m

CsTotal amount of dopant introduced = Q(t)

错误！未找到引用源。 25

=

2?CsL?5.54?1014atoms/cm2.

?3.46??Ea????1422. D?D0exp???0.76exp???4.96?10cm/s ?5?8.614?10?1323??kT?S3From Eq. 15, CS?C(0,t)? ?2.342?1019atoms/cm?Dtx?x??? C(x)?CSerfc???2.342?1019erfc??5?2L2.673?10????If x = 0, C(0) = 2.342 × 1019 atoms/cm3; x = 0.1×10-4, C(10-5) = 1.41×1019 atoms/cm3;

x = 0.2×10-4, C(2×10-5) = 6.79×1018 atoms/cm3; x = 0.3×10-4, C(3×10-5) = 2.65×1018 atoms/cm3;

x = 0.4×10-4, C(4×10-5) = 9.37×1017 atoms/cm3; x = 0.5×10-4, C(5×10-5) = 1.87×1017 atoms/cm3;

x = 0.6×10-4, C(6×10-5) = 3.51×1016 atoms/cm3; x = 0.7×10-4, C(7×10-5) = 7.03×1015 atoms/cm3;

x = 0.8×10-4, C(8×10-5) = 5.62×1014 atoms/cm3. The xj?4Dtln

SCB?Dt?0.72 ?m.

??10?83. 1?10?1?10exp??4?2.3?10?13t??

??1518t = 1573 s = 26 min

For the constant-total-dopant diffusion case, Eq. 15 gives CS?2 S?1?1018??2.3?10?13?1573?3.4?1013atoms/cm.

S?Dt

4. The process is called the ramping of a diffusion furnace. For the ramp-down situation, the

furnace temperature T is given by

T = T0 - rt

where T0 is the initial temperature and r is the linear ramp rate. The effective Dt product during a ramp-down time of t1 is given by

(Dt)eff?? t1 0D(t)dt

In a typical diffusion process, ramping is carried out until the diffusivity is negligibly small. Thus the upper limit t1 can be taken as infinity:

错误！未找到引用源。

26

1T?1T0?rt?1T0(1?rtT0?...)

and

?Ea??Dexp??Ea(1?rt?...)??D(exp?Ea)(exp?rEat...)?D(T)exp?rEatD?D0exp??000?kT?22kT???T0kT0kT0kT0?0?

where D(T0) is the diffusion coefficient at T0. Substituting the above equation into the expression for the effective Dt product gives

(Dt)eff?? D(T0)exp 0 ??rEatkT02kTdt?D(T0)0

rEa2Thus the ramp-down process results in an effective additional time equal to kT02/rEa at the initial diffusion temperature T0.

For phosphorus diffusion in silicon at 1000?C, we have from Fig. 4: D(T0) = D (1273 K) = 2× 10-14 cm2/s

1273?773r??0.417K/s

20?60Ea = 3.66 eV

Therefore, the effective diffusion time for the ramp-down process is

kT20arE?1.38?10?23(1273)2?190.417(3.66?1.6?10)?91s?1.5min.

5. For low-concentration drive-in diffusion, the diffusion is given by Gaussian distribution.

The surface concentration is then

C(0,t)?SS?E??exp?a? ?Dt?D0t?2kT????t3/2?????2?C???0.5? ?t?dCS?E?exp?adt?D0?2kT??0.5? Ctwhich means 1% change in diffusion time will induce 0.5% change in surface

or

dCdtconcentration.

错误！未找到引用源。 27

dCS?E???Ea?exp?a??2dT?D0t?2kT??2kTEa???C ?22kT??19or

dCC??Ea2kT?dTT??3.6?1.6?102?1.38?10?23 ???16.9?T?1273TdTdTwhich means 1% change in diffusion temperature will cause 16.9% change in

surface concentration.

6. At 1100?C, ni = 6×1018 cm-3. Therefore, the doping profile for a surface concentration

of 4 × 1018 cm-3 is given by the “intrinsic” diffusion process:

?x?C(x,t)?Cserfc????

?2Dt?where Cs = 4× 1018 cm-3, t = 3 hr = 10800 s, and D = 5x10-14 cm2/s. The diffusion length is then

Dt?2.32?10?5cm?0.232?m

x??The distribution of arsenic is C(x)?4?1018erfc? ?5??4.64?10?The junction depth can be obtained as follows

xj??10?4?10erfc??4.64?10?5??

??1518xj = 1.2× 10-4 cm = 1.2 ?m.

7. At 900?C, ni = 2× 1018 cm-3. For a surface concentration of 4×1018 cm-3, given by

the “extrinsic” diffusion process

D?D0e?EakTn4?10181.38?10?23?1173??45.8e??3.77?10?16cm2/s 18ni2?10?4.05?1.6?10?19xj?1.6Dt?1.63.77?10?16?10800?3.23?10?6cm?32.3 nm.

8. Intrinsic diffusion is for dopant concentration lower than the intrinsic carrier

concentration ni at the diffusion temperature. Extrinsic diffusion is for dopant concentration higher than ni.

9. For impurity in the oxidation process of silicon,

equilibrium concentration of impurity in siliconn coefficeint ? segregatio.

equilibrium concentration of impurity in SiO2错误！未找到引用源。

28

3?10113??0.006 . 10. ??135005?1011. –0.5 = –1.1 + qFB/Ci

3.9?8.85?10?14?7??3.45?10 Cox? ?6d103.45?10?7FB??0.6?1.3?1012cm?2 ?191.6?1010?52?s?(10.16)t?1.3?10?1.6?1012?19

the implant time t = 6.7 s.

12. The ion dose per unit area is

It10?10?6?5?60?19Nq1.6?10 ???2.38?1012 ions/cm2 10AA??()22From Eq. 25 and Example 3, the peak ion concentration is at x = Rp. Figure. 17 indicates the ?p is 20 nm.

Therefore, the ion concentration is

S?2.38?101220?10?72??4.74?1017cm?3.

?p2?13. From Fig. 17, the Rp = 230 nm, and ?p = 62 nm.

The peak concentration is

S?2?101562?10?72??1.29?1020cm?3

?p2?From Eq. 25,

2???(x?R)jp152010?1.29?10exp?? 22?p????xj = 0.53 ?m.

QC0?VT3.9?8.85?10?14?111?214. Dose per unit area = ? ??8.6?10cm?8?19qq250?10?1.6?10 From Fig. 17 and Example 3, the peak concentration occurs at 140 nm from the surface. Also, it is at (140-25) = 115 nm from the Si-SiO2 interface. 15. The total implanted dose is integrated from Eq. 25

错误！未找到引用源。

29

QT??

?S 0?p??(x?Rp)2?Rp??S?S???S exp?dx?1?1?erfc()?[2?erfc(2.3)]??1.9989?????22222??p2?????2?p???????The total dose in silicon is as follows (d = 25 nm):

QSi??

?S d?p??(x?Rp)2?Rp?d??S?S???Sexp?dx?1?1?erfc()?[2?erfc(1.87)]??1.9918?????22222??p2?????2?p???????the ratio of dose in the silicon = QSi/QT = 99.6%.

16. The projected range is 150 nm (see Fig. 17).

The average nuclear energy loss over the range is 60 eV/nm (Fig. 16). 60× 0.25 = 15 eV (energy loss of boron ion per each lattice plane) the damage volume = VD = ? (2.5 nm)2(150 nm) = 3× 10-18 cm3 total damage layer = 150/0.25 = 600 displaced atom for one layer = 15/15 = 1 damage density = 600/VD = 2×1020 cm-3

2×1020/5.02×1022 = 0.4%.

17. The higher the temperature, the faster defects anneal out. Also, the solubility of

electrically active dopant atoms increases with temperature.

Q18. ?Vt?1 V?1

Coxwhere Q1 is the additional charge added just below the oxide-semiconductor surface by ion implantation. COX is a parallel-plate capacitance per unit area given by Cox??sd

(d is the oxide thickness, ?sis the permittivity of the semiconductor)

C1V?3.9?8.85?10?14F/cm?7?10 Q1??VtCox? = 8.63

cm20.4?10?6cm

8.63?10?712 2

= 5.4 ×10ions/cm

1.6?10?195.4?1012Total implant dose = = 1.2 × 1013 ions/cm2.

45%

19. The discussion should mention much of Section 13.6. Diffusion from a surface film

avoids problems of channeling. Tilted beams cannot be used because of

错误！未找到引用源。

30

shadowing problems. If low energy implantation is used, perhaps with preamorphization by silicon, then to keep the junctions shallow, RTA is also necessary.

20. From Eq.35

Sd1?0.4?0.6??erfc???0.84 S2?0.22?The effectiveness of the photoresist mask is only 16%. Sd1?1?0.6??erfc???0.023 S2?0.22?The effectiveness of the photoresist mask is 97.7%.

e-u21. T? ?10?5

2?u?u?3.02

1d = Rp + 4.27?p= 0.53 + 4.27 × 0.093 = 0.927 μm.

2错误！未找到引用源。 31

INTEGRATION

1．已知薄层电阻为1kΩ/口，求出在一2.5mm×2.5mm芯片上可以制造出线条宽为2μm、间距为4μm (即平行线条中心间的距离)的最大电阻．

2．设计一个5pF的MOS电容掩模版组．氧化层厚度为30nm，假设最小窗的尺寸为2μm×10μm，最大的真准误差(registration error)为2μm．

3．试完整地绘出在衬底上制作具有三圈螺旋形电感所需的掩模版组中的每一道掩模版．

4．请设计一个10nH方形螺旋型电感，其金属连线的全长为350μm，每N间的间距为2μm.

5．试绘出一个箝制晶体管的电路图与器件截面图． 6·请说明下列用于自对准双多晶硅双极型晶体管结构中的步骤的目的：

(a)右图(a)中位于沟槽内的未掺杂多晶硅； (b)右图(b)中的多晶硅1； (c)右图(d)中的多晶硅2．

7．在NMOS工艺中，起始材料为P型、10Ω?cm<100>晶向的硅晶片．利用30keV、1016/cm2。的砷离子注入，经过25nm栅极氧化层形成源极与漏极． (a)估计器件的阈值电压变化．

(b)试绘出沿着垂直于表面且经过沟道区域或是源极区域的坐标上的掺杂分布．

8．(a)为什么在NMOS工艺中，较常使用<100>晶向的晶片?

(b)若用于NMOS器件的场氧化层太薄，会有何缺点?

(c)多晶硅栅极用于栅极长度小于3μm时。会有何问题产生?可用其他材料取代多晶硅吗? (d)如何得到自对准的栅极?其优点是什么? (e)磷硅玻璃的用途是什么?

9．对一个浮栅极非挥发性存储器而言，下端绝缘层的介电常数为4，厚度为10nm．在浮栅极上方的绝缘层其介电常数为10，厚度为l00nm．如果在下端的

32

绝缘层中电流密度J=σE，σ=10-7S/cm，而在另一绝缘层中的电流小到可以忽略，试找出因外加电压10V于控制栅极(a)0.25μs，(b)足够长的时间以致于在下端的J变为可忽略不计时，所产生的器件闽值电压漂移． 10．试完整地绘出右图中CMOS反相器的掩模版组中的每一个掩模版．特别注意以图(c)中的截面图为作图比例．

11．一个0．5μm数字CMOS工艺包含有宽为5μm的晶体管，最小的导线宽为1μm，金属层为1μm厚的铝．假设μn为

400cm2/(V·s)，d是10nm, VDD为3.3V，阈值电压为0.6V．最后，假设截面积为

1μm2的铝导线载有NMOS晶体管可提供的最大电流时，其可承受的最大压降为0.1V．试问可容许多长的导线?利用简单的平方定律、长沟道模型去估计MOS驱动电流(铝的电阻率为2.7×10-8Ω?cm)．

1 2．绘出下列工艺步骤中双阱CMOS结构的截面图． (a)n型阱注入； (b)P型阱注入； (c)双阱注入；

(d)非选择性P+源极与漏极注入；

(e)以光刻胶作为掩蔽层时，选择性n+源极与漏极注入； (f)淀积磷硅玻璃．

13．为什么在PMOS中使用P+多晶硅栅极?

14．PMOS的P+多晶硅栅极中，什么是硼穿透问题?如何消除此问题?

15．为了得到好的界面性质，在高介电常数材料与衬底间需淀积一层缓冲层，试计算出其等效氧化层厚度．假设堆叠栅极介电层结构为 (a)0.5nm氮化硅的缓冲层；

33

(b)10nm的五氧化二钽．

16．试描述LOCOS技术的缺点及浅沟槽隔离技术的优点． 17．用于右图(f)中的聚酰亚胺的目的是什么?

18．为什么在GaAs上不易制作双极型晶体管与MOSFET?

19．(a)试计算位于0.5μm厚的热氧化层上0.5μm厚的铝导线的RC时间常数．导线长度与宽度分别为lcm和1μm．导线阻值为10-5Ω?cm．

(b)对于相同尺寸的多晶硅导线(R口=30Ω/□)，RC时间常数为多少? 20．为什么对于一个系统整合芯片(SOC)，需要多种的氧化层厚度? 21·通常需要一层缓冲层位于高介电常数的五氧化二钽与硅衬底之间．试计算当堆叠栅极介电层为一位于氮化硅缓冲

层(k=7，厚度l0?)上的75 ?厚的五氧化二钽(k=25)时，有效氧化层厚度为多少?对于一缓冲层为二氧化硅(k=3.9，厚度5 ?)时，等效氧化层厚度又是多少?

1. Each U-2

104 . Therefore, there are (2500)2/2 ×104 = 312.5 U-shaped section. Each section contains 2 long lines with 1248 squares each, 4 corner squares, 1 bottom square, and 2 half squares at the top. Therefore the resistance for each section is

1 k? /□ (1248×2 + 4×0.65 +2) = 2500.6 k?

The maximum resistance is then

312.5×2500.6 = 7.81 × 108 ? = 781 M?

34

2. The area required on the chip is

Cd(30?10?7)(5?10?12)A???4.35?10?5 cm2 ?14?ox3.9?8.85?10

2

= 4.35 × 103

Refer to Fig.4a and using negative photoresist of all levels

(a) Ion implantation mask (for p+ implantation and gate oxide) (b)

(c) Metallization mask (using Al to form ohmic contact in the contact window and form the MOS capacitor).

ed in all critical

dimensions.

35

turn). Assume there are n turns, from Eq.6, L ? ?0n2r ? 1.2 × 10-6n2r, where r can be replaced by 2 × n. Then, we can obtain that n is 13.

4. (a) Metal 1, (b) contact hole, (c) Metal 2. (a) Metal 1,

36

(b) contact hole,

(c) Metal 2.

5. The circuit diagram and device cross-section of a clamped transistor are shown in (a)

and (b), respectively.

37

6. (a) The undoped polysilicon is used for isolation.

(b) The polysilicon 1 is used as a solid-phase diffusion source to form the

extrinsic base region and the base electrode.

(c) The polysilicon 2 is used as a solid-phase diffusion source to form the emitter region

and the emitter electrode. 7. (a) For 30 keV boron, Rp = 100 nm and ?Rp = 34 nm. Assuming that Rp and ?Rp for boron are the same in Si and SiO2 the peak concentration is given by

S2??Rp?8?10112?(34?10?7)?9.4?1016 cm?3

The amount of boron ions in the silicon is

??x?Rp?2?QS?exp??2q?d2??Rp2?R?p??Rp?dS???2?erfc??2?R2?p??8?1011?2??????????dx??

??750??2?erfc????2?340?????7.88?1011cm?2Assume that the implanted boron ions form a negative sheet charge near the Si-SiO2 interface, then

?Q?1.6?10?19?(7.88?1011)?VT?q??q??/Cox?3.9?8.85?10?14/?25?10?7??0.91 V

??(b) For 80 keV arsenic implantation,

Rp = 49 nm and ? Rp = 18 nm. The peak arsenic concentration is

S2??Rp?1016??(18?10?7)?2.21?1021 cm?38.

.

(a) Because (100)-oriented

silicon has lower (~ one tenth) interface-trapped charge and a lower fixed oxide charge.

(b) If the field oxide is too thin,

38

it may not provide a large enough threshold voltage for adequate isolation between neighboring MOSFETs.

(c) The typical sheet resistance of heavily doped polysilicon gate is 20 to

30 ?

shorter gates, the sheet resistance of polysilicon is too high and will cause large RC delays. We can use refractory metals (e.g., Mo) or silicides as the gate material to reduce the sheet resistance to about 1 ? /□.

(d) A self-aligned gate can be obtained by first defining the MOS gate structure, then

using the gate electrode as a mask for the source/drain implantation. The self-aligned gate can minimize parasitic capacitance caused by the source/drain regions extending underneath the gate electrode (due to diffusion or misalignment).

(e) P-glass can be used for insulation between conducting layers, for diffusion and

ion implantation masks, and for passivation to protect devices from impurities,

moisture, and scratches.

9. The lower insulator has a dielectric constant ?1/?0 = 4 and a thickness d1= 10 nm The

upper insulator has a dielectric constant ?2/?0 = 10 and a thickness d2 = 100 nm. Upon application of a positive voltage VG to the external gate, electric field E1 and E2 are

established in the d1 and d2 respectively. We have, from Gauss’ law, that ?1E1 = ?2E2 +Q and VG = E1d1 + E2d2

where Q is the stored charge on the floating gate. From these above two equations, we obtain

E1?VGQ ?d1?d2??1/?2??1??2?d1/d2???Q?5??0.2?2.26?10Q

??10???14?4?10?8.85?10??????100??????10?107?7?? J??E1?10?4??10?100?????10??(a) If the stored charge does not reduce E1 by a significant amount (i.e., 0.2 >> 2.26×105 ?Q?,

we can write

?6 Q? ??E?5?10?8C 1dt'?0.2?t?0.2?0.25?10 0 t ??Q5?10?8 ?VT???0.565 V ?14?7C210?8.85?10/100?10????(b) when t??,J?0we have Q?0.2/2.26?105?8.84×10-7 C.

39

Q8.84?10?7 Then ?VT???9.98 V. ?14?5C210?8.85?10/10??10.

40

11. The oxide capacitance per unit area is given by

d and the maximum current supplied by the device is

1W15?m2?Cox?VG?VT?2?3.5?10?7?VG?VT??5mA IDS?2L20.5?mand the maximum allowable wire resistance is 0.1 V/5 mA, or 20?. Then, the length of the wire must be L? Cox??SiO2?3.5?10?7F/cm2

R?Area?20??10?8cm2??0.074 cm ?82.7?10??cmdriving signals between widely spaced logic blocks however, minimum feature sized lines would not be appropriate.

41

12.

13. To solve the short-channel effect of devices.

14. The device performance will be degraded from the boron penetration. There are

methods to reduce this effect: (1) using rapid thermal annealing to reduce the time at high temperatures, consequently reduces the diffusion of boron, (2) using nitrided oxide to suppress the boron penetration, since boron can easily combine with nitrogen and becomes less mobile, (3) making a multi-layer of polysilicon to trap the boron atoms at the interface of each layer.

42

15. Total capacitance of the stacked gate structure is :

C =

?1d1??2d2??1?2?725?725???? ? ????= 2.12 ?d?d0.5100.510??2??13.9= 2.12 d?d?3.9=1.84 nm. 2.1216. Disadvantages of LOCOS: (1) high temperature and long oxidation time cause VT

shift, (2) bird’s beak, (3) not a planar surface, (4) exhibits oxide thinning effect. Advantages of shallow trench isolation: (1) planar surface, (2) no high temperature processing and long oxidation time, (3) no oxide thinning effect, (4) no bird’s beak.

17. For isolation between the metal and the substrate. 18. GaAs lacks of high-quality insulating film. 19. (a)

A??1?L??RC??????ox???10?5?d??1?0.5?10?8 ?A??1??1?10?4?????14??3.9?8.85?10??0.5?10?4? ???2000??69.03?10?14??1.38?10?9s?1.38 ns. (b) For a polysilicon runner

L??A??RC??Rsquare???ox?W??d???1??30??4?69.03?10?14?2.07?10?7 s

?10??207 ns??Therefore the polysilicon runner’s RC time constant is 150 times larger than the aluminum runner.

20. When we combine the logic circuits and memory on the chip, we need multiple

supply voltages. For reliability issue, different oxide thicknesses are needed for different supply voltages.

121. (a) 1 ?1Ctotal?CTa2O5Cnitride hence EOT3.9?7525?107?17.3 ? (b) EOT = 16.7 ?.

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