HD74HCT373RPEL中文资料

元器件交易网

HD74HCT373, HD74HCT533

Octal D-type Transparent Latches (with 3-state outputs)

Octal D-type Transparent Latches (with inverted 3-state outputs)

REJ03D0666–0200 (Previous ADE-205-555)

Rev.2.00 Mar 30, 2006

Description

When the latch enable input is high, the Q outputs of HD74HCT373 will follow the D inputs and the Q outputs of HD74HCT533 will follow the inversion of the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals present at the other inputs and the state of the storage elements.

Features

LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility High Speed Operation: tpd (Data to Q) = 14 ns typ (CL = 50 pF) High Output Current: Fanout of 15 LSTTL Loads Wide Operating Voltage: VCC = 4.5 to 5.5 V Low Input Current: 1 µA max

Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Ordering Information

Part Name

Package Type

Package Code (Previous Code) PRDP0020AC-B (DP-20NEV) PRSP0020DD-B (FP-20DAV) PRSP0020DC-A (FP-20DBV) PTSP0020JB-A (TTP-20DAV)

Package Abbreviation

Taping Abbreviation

(Quantity)

pin HD74HCT373FPEL HD74HCT373RPEL HD74HCT533RPEL

SOP-20 pin (JEITA) SOP-20 pin (JEDEC)

FP RP T

EL (2,000 pcs/reel) EL (1,000 pcs/reel) ELL (2,000 pcs/reel)

pin

Note: Please consult the sales office for the above package availability.

Function Table

HD74HCT373 HD74HCT533

D Q Q Output Control Enable G

L L X No change No change

Notes: 1. H; High level, L; Low level, X; Irrelevant, Z; High impedance

Pin Arrangement

HD74HCT373

HD74HCT533

Logic Diagram

HD74HCT373

HD74HCT533

Absolute Maximum Ratings

Supply voltage range VCC –0.5 to 7.0 V Input / Output voltage VIN, VOUT –0.5 to VCC +0.5 V Input / Output diode current IIK, IOK ±Output current IOUT ±VCC, GND current ICC or IGND ±Power dissipation PTStorage temperature Tstg –65 to +150 °C Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of

which may be realized at the same time.

Recommended Operating Conditions

Supply voltage VCC 4.5 to 5.5 V Input / Output voltage VIN, VOUT 0 to VCC Operating temperature Ta –40 to 85 °Input rise / fall time tr, tf 0 to 500 ns VCC = 4.5 V Notes: 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics.

Electrical Characteristics

VCC (V)

Input voltage Output voltage

Ta = 25°C Ta = –40 to+85°C

VIH 4.5 to 5.5 2.0 — — 2.0 — V VIL 4.5 to 5.5 — — 0.8 — 0.8 V VOH Vin = VIH or VIL IOH = –20 µA

IOH = –6 mA

VOL Vin = VIH or VIL IOL = 20 µA

IOL = 6 mA

±±5.0 µA Vin = VIH or VIL, IOZVout = VCC or GND

Iin 5.5 — — ±±1.0 µA Vin = VCC or GND ICCµA Vin = VCC or GND, Iout = 0 µA

Off-state output

current

Input current

Quiescent current

Switching Characteristics

(CL = 50 pF, Input tr = tf = 6 ns)

VCC (V)

Propagation delay

time

tPLHns Latch control to Q tPHLtPLHns Data to Q

tPHLtZLtZHtLZtHZtsu 4.5 20 — — 25 — ns Data to latch control th 4.5 10 — — 13 — ns Latch control to data twLatch control, output control tTLH tTHL Cin

—

—

5

10

—

10

pF

Ta = 25°C

Ta = –40 to +85°C

Output enable time Output disable

time Setup time Hold time Pulse width Output rise/fall time

Input capacitance

Test Circuit

Waveforms

元器件交易网HD74HCT373, HD74HCT533 Waveform– 3tr Input G 10% 90% 90% 1.3 V 1.3 V tw tsu Input D 10% th VCC 1.3 V 1.3 V 0V tf VCC 0V

Waveform– 4tf Input OC 90% 1.3 V 10% tZL Waveform - A 1.3 V tZH Waveform - B 1.3 V tHZ 90% tr 90%

1.3 V 10% tLZ VCC 0V VOH 10% VOL VOH VOL

Notes: 1. Input waveform: PRR≤ 1 MHz, duty cycle 50%, tr≤ 6 ns, tf≤ 6 ns 2. Waveform– A is for an output with internal conditions such that the output is low except when disabled by the output control. 3. Waveform– B is for an output with internal conditions such that the output is high except when disabled by the output control. 4. The output are measured one at a time with one transition per measurement.

Rev.2.00 Mar 30, 2006 page 6 of 8

Package Dimensions

元器件交易网HD74HCT373, HD74HCT533JEITA Package Code P-SOP20-5.5x12.6-1.27 RENESAS Code PRSP0020DD-B Previous Code FP-20DAV MASS[Typ.] 0.31g

*1

D 11

F

20

NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.

bpHE

E

Index mark

*2

Terminal cross section ( Ni/Pd/Au plating )1 Z e*3

10 bp x M L1

c

Reference Dimension in Millimeters Symbol

θyA1

L

Detail F

D E A2 A1 A bp b1 c c1θ HE e x y Z L L1

Min Nom Max 12.60 13.0 5.50

0.00 0.10 0.20 2.20 0.34 0.40 0.46 0.15 0.20 0.25 0° 8° 7.50 7.80 8.00 1.27 0.12 0.15 0.80 0.50 0.70 0.90 1.15

JEITA Package Code P-TSSOP20-4.4x6.5-0.65

RENESAS Code PTSP0020JB-A

Previous Code TTP-20DAV

MASS[Typ.] 0.07g

*1

D F 11

A

20

NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.bp

HE

*2

E

Index mark

Terminal cross section ( Ni/Pd/Au plating )Reference Dimension in Millimeters Symbol

c

1 Z e*3

10 bp L1 x M

θA1

L

y

Detail F

D E A2 A1 A bp b1 c c1θ HE e x y Z L L1

Min Nom Max 6.50 6.80 4.40

0.03 0.07 0.10 1.10 0.15 0.20 0.25 0.10 0.15 0.20 0° 8° 6.20 6.40 6.60 0.65 0.13 0.10 0.65 0.4 0.5 0.6 1.0

Rev.2.00 Mar 30, 2006 page 8 of 8

A

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