MEMORY存储芯片MT29F256G08AUCABH3-10A中文规格书

Asynchronous Interface Bus Operation

The bus on the device is multiplexed. Data I/O, addresses, and commands all share the

same pins. I/O[15:8] are used only for data in the x16 configuration. Addresses and

commands are always supplied on I/O[7:0].

The command sequence typically consists of a COMMAND LATCH cycle, address input

cycles, and one or more data cycles, either READ or WRITE.

Table 4: Asynchronous Interface Mode Selection

Notes: 1.Mode selection settings for this table: H = Logic level HIGH; L = Logic level LOW; X = V IH

or V IL.

2.WP# should be biased to CMOS LOW or HIGH for standby.

Asynchronous Enable/Standby

When the device is not performing an operation, the CE# pin is typically driven HIGH

and the device enters standby mode. The memory will enter standby if CE# goes HIGH

while data is being transferred and the device is not busy. This helps reduce power con-

sumption.

The CE# “Don’t Care” operation enables the NAND Flash to reside on the same asyn-

chronous memory bus as other Flash or SRAM devices. Other devices on the memory

bus can then be accessed while the NAND Flash is busy with internal operations. This

capability is important for designs that require multiple NAND Flash devices on the

same bus.

A HIGH CLE signal indicates that a command cycle is taking place. A HIGH ALE signal

signifies that an ADDRESS INPUT cycle is occurring.

Asynchronous Commands

An asynchronous command is written from I/O[7:0] to the command register on the ris-

ing edge of WE# when CE# is LOW, ALE is LOW, CLE is HIGH, and RE# is HIGH.

Commands are typically ignored by die (LUNs) that are busy (RDY = 0); however, some

commands, including READ STATUS (70h), are accepted by die (LUNs) even when they

are busy.

For devices with a x16 interface, I/O[15:8] must be written with zeros when a command

is issued.

PDF: 09005aef83e5ffed

m68a_1gb_nand.pdf - Rev. L 10/12 EN

Table 11: Feature Addresses 01h: Timing Mode

1Gb x8, x16: NAND Flash Memory

Feature Operations

PDF: 09005aef83e5ffed

m68a_1gb_nand.pdf - Rev. L 10/12 EN

Table 12: Feature Addresses 80h: Programmable I/O Drive Strength

Note:

1.The programmable drive strength feature address is used to change the default I/O

drive strength. Drive strength should be selected based on expected loading of the memory bus. This table shows the four supported output drive strength settings. The default drive strength is full strength. The device returns to the default drive strength mode when the device is power cycled. AC timing parameters may need to be relaxed if I/O drive strength is not set to full.

Table 13: Feature Addresses 81h: Programmable R/B# Pull-Down Strength

Note:

1.This feature address is used to change the default R/B# pull-down strength. Its strength

should be selected based on the expected loading of R/B#. Full strength is the default,power-on value.

1Gb x8, x16: NAND Flash Memory

Feature Operations

PDF: 09005aef83e5ffed

m68a_1gb_nand.pdf - Rev. L 10/12 EN

Status Operations

Each die (LUN) provides its status independently of other die (LUNs) on the same target through its 8-bit status register.

After the READ STATUS (70h) command is issued, status register output is enabled. The contents of the status register are returned on I/O[7:0] for each data output request.When the asynchronous interface is active and status register output is enabled,

changes in the status register are seen on I/O[7:0] as long as CE# and RE# are LOW; it is not necessary to toggle RE# to see the status register update.

While monitoring the status register to determine when a data transfer from the Flash array to the data register (t R) is complete, the host must issue the READ MODE (00h)command to disable the status register and enable data output (see Read Operations).With internal ECC enabled, a READ STATUS command is required after completion of the data transfer (t R_ECC) to determine whether an uncorrectable read error occurred.

Table 14: Status Register Definition

Notes:

1.Status register bit 6 is 1 when the cache is ready to accept new data. R/B# follows bit 6.

2.Status register bit 5 is 0 during the actual programming operation. If cache mode is

used, this bit will be 1 when all internal operations are complete.

3. A status register bit defined as Rewrite Recommended signifies that the page includes

acertain number of READ errors per sector (512B (main) + 4B (spare) + 8B (parity). A re-writeof this page is recommended. (Up to a 4-bit error has been corrected if internal ECC was enabled.)

4. A status register bit defined as FAIL signifies that an uncorrectable READ error has oc-curred.

1Gb x8, x16: NAND Flash Memory

Status Operations

PDF: 09005aef83e5ffed

m68a_1gb_nand.pdf - Rev. L 10/12 EN

Column Address Operations

The column address operations affect how data is input to and output from the cache

registers within the selected die (LUNs). These features provide host flexibility for man-

aging data, especially when the host internal buffer is smaller than the number of data

bytes or words in the cache register.

When the asynchronous interface is active, column address operations can address any

byte in the selected cache register.

RANDOM DATA READ (05h-E0h)

The RANDOM DATA READ (05h-E0h) command changes the column address of the se-

lected cache register and enables data output from the last selected die (LUN). This

command is accepted by the selected die (LUN) when it is ready (RDY = 1; ARDY = 1). It

is also accepted by the selected die (LUN) during CACHE READ operations

(RDY = 1; ARDY = 0).

Writing 05h to the command register, followed by two column address cycles containing

the column address, followed by the E0h command, puts the selected die (LUN) into

data output mode. After the E0h command cycle is issued, the host must wait at least

t WHR before requesting data output. The selected die (LUN) stays in data output mode

until another valid command is issued.

Figure 31: RANDOM DATA READ (05h-E0h) Operation

Cycle type

I/O[7:0]

SR[6]

1Gb x8, x16: NAND Flash Memory Column Address Operations

PDF: 09005aef83e5ffed

m68a_1gb_nand.pdf - Rev. L 10/12 EN

本文来源：https://www.bwwdw.com/article/igu4.html