VerilogHDL代码 - AHB总线 - master部分

module ahb_master

(HBUSREQ,HLOCK,HTRANS,HADDR,HWRITE,HSIZE,HBURST,HWDATA,HSEL,hcount,HRESETn,HCLK,HGRANT,HREADY,HRESP,HRDATA,BUSREQ,ADDREQ,WRITE,ADDR,SIZE,BURST,SEL,TRANS,WDATA); output HBUSREQ,HLOCK,HWRITE; output [1:0]HTRANS,HSEL; output [31:0]HADDR,HWDATA; output [2:0]HSIZE,HBURST;

input HGRANT,HREADY,HCLK,HRESETn,BUSREQ,ADDREQ,WRITE; input [31:0]ADDE,WDATA; input [2:0]SIZE,BURST;

input [1:0]HRESP,SEL,TRANS; input [31:0]HRDATA;

reg HBUSRREQ,HLOCK,HWRITE,hcount; reg [1:0]HTRANS,HSEL; reg [31:0]HADDR,HWDATA; reg [2:0]HSIZE,HBURST;

wire HGRANT,HREADY,HCLK,HRESETn,WRITE; wire [31:0]ADDR,WDATA; wire [2:0]SIZE,BURST;

wire [1:0]HRESP,SEL,TRANS; wire [31:0]HRDATA;

reg bus_reg,adde_reg,new_hready,old_hready; reg [31:0]RDATA; reg [31:0]h_addr;

parameter OKAY=2'b00 ERROR=2'b01 RETRY=2'b10 SPLIT=2'b11;

always @(posedge HCLK) begin

if(!HRESETn) begin

HBUSREQ=0; HLOCK=0; HWRITE=0; HTRANS=2'b00; HSEL=2'b00;

HADDR=32'h000000000;

HWDATA=32'h000000000; HSIZE=2'b00; HBURST=2'b00; bus_reg=0; addr_reg=0; new_hready=0; old_hready=0; hcount=0; end end

always @(posedge HCLK) begin

if(HRESETn) begin

if(!addr_reg) begin

if(ADDREQ) begin

HADDR=ADDR; h_addr=ADDR; HWRITE=WRITE; HSIZE=SIZE; HBURST=BURST; HSEL=SEL;

HTRANS=TRANS; addr_reg=1'b1;

HWDATA=32'h000000000; end end

else if(addr_reg) begin

HADDR=32'h000000000; HWRITE=1'b0; HSIZE=3'b000; HBURST=3'b000; HTRANS=2'b00; addr_reg=1'b0; end if(!ADDREQ) begin if(WRITE) begin

hcount=0;

case({TRANS}) 2'b00:begin

HWDATA=WDATA;

if(HREADY && !new_hready && HRESP==ERROR) new_hready=1;

else if(new_hready!=old_hready) HWDATA=32'h00000000; end 2'b01:begin

hcount=hcount+1; new_hready=0; HWDATA=WDATA;

if(HREADY &&!new_hready && HRESP) new_hready=1;

else if(new_hready!=old hready) hWDATA=32'h00000000; end 2'b10:begin

HWDATA=32'h00000000; end 2'b11:begin

hcount=hcount+1; HWDATA=WDATA;

if(HREADY && HRESP==OKAY) begin

if(!new_hready) new_hready=1; end

else if(new_hready!=old_hready) begin

HWDATA=WDATA; new_hready=0; end

else if(HREADY && HRESP==ERROR) begin

HWDATA=32'h00000000; end end endcase end

else if(!WRITE) begin

case({TRANS})

2'b00:begin

if(!HREADY)

RDATA=HRDATA; else if(HREADY)

RDATA=32'h00000000; end 2'b01:begin

if(!HREADY) begin

RDATA=HRDATA; if(HBURST==000)

h_addr=h_addr+1; else

h_addr=h_addr-1; end

else if(HREADY)

RDATA=32'h00000000; end 2'b10:begin

RDATA=32'h00000000; end 2'b11:begin

if(!HREADY) begin

RDATA=HRDATA; if(HBURST==000)

h_addr=h_addr+1; else

h_addr=h_addr-1; end endcase end end end

endmodule

module ram_top( HCLK , HRESETn , HSEL_s , HADDR_s , HBURST_s , HTRANS_s ,

HRDATA_s , HWDATA_s , HWRITE_s , HREADY_s , HRESP_s );

input HCLK ; input HRESETn ;

input HSEL_s ;

input [19:0] HADDR_s ; input [2:0] HBURST_s ; input [1:0] HTRANS_s ; input [31:0] HWDATA_s ; input HWRITE_s ;

output [1:0] HRESP_s ; output [31:0] HRDATA_s ; output HREADY_s ;

wire [31:0] ram_RDATA ; wire [17:0] ram_ADDR ; wire [31:0] ram_WDATA ; wire ram_WRITE ;

ram_ahbif U_ram_ahbif ( .HCLK (HCLK ),

.HRESETn (HRESETn ), .HSEL_s (HSEL_s ), .HADDR_s (HADDR_s ), .HBURST_s (HBURST_s ), .HTRANS_s (HTRANS_s ), .HRDATA_s (HRDATA_s ), .HWDATA_s (HWDATA_s ), .HWRITE_s (HWRITE_s ), .HREADY_s (HREADY_s ), .HRESP_s (HRESP_s ),

.ram_RDATA (ram_RDATA ), .ram_ADDR (ram_ADDR ), .ram_WDATA (ram_WDATA ), .ram_WRITE (ram_WRITE ) );

ram_infer U_ram_infer(

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