AD402M91RBA-5中文资料

元器件交易网

ASCENDSemiconductor4Mx4 EDOData sheet

元器件交易网

元器件交易网

Description

The device CMOS Dynamic RAM organized as 4,194,304 words x 4 bits with extended data out access mode. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 3.3V oniy power supply. Low voltage operation is more suitable to be used on battery backup, portable elec-tronic application. lt is packaged in JEDEC standard 26/24-pin plastic SOJ or TSOP(II).Features

Single 3.3V(±10%) only power supply High speed tRAC acess time: 50/60ns Low power dissipation

- Active mode : 432/396 mW (Mas) - Standby mode: 0.54 mW (Mas)

Extended - data - out(EDO) page mode access I/O level: CMOS level (Vcc = 3.3V)

2048 refresh cycle in 32 ms(Std.) or 128 ms(S-version) 4 refresh modesh: - RAS only refresh

- CAS - before - RAS refresh- Hidden refresh- Self-refresh(S-version)

元器件交易网

Pin Configuration

26/24-PIN 300mil Plastic SOJ

26/24-PIN 300mil Plastic TSOP (ll)

VCCDQ1DQ2 NC A10 A0 A1 A2 A3VCC

1234568910111213

26 25

24232221191817161514

VSSDQ4DQ3A9A8A7A6A5A4VSS

VCCDQ1DQ2 NC A10 A0 A1 A2 A3VCC

1234568910111213

262524232221191817161514

VSSDQ4DQ3A9A8A7A5 A4VSS

AD404M42VT

AD404M42VS

Pin Description Pin NameA0-A10

Function

Address inputs

- Row address A0-A10- Column address A0-A10- Refresh address A0-A10Data-in / data-outRow address strobeColumn address strobeWrite enableOutput enablePower (+ 3.3V)Ground

DQ1~DQ4RASCASWEOEVccVss

元器件交易网

Block Diagram

WE

CAS

CONTROL

LOGIC

DATA-IN BUFFER

DQ1..DQ4

NO. 2 CLOCKGENERATOR

DATA-OUTBUFFER

OE

COLUMNADDRESSBUFFERS (11)

A0A1A2A3A4A5A6A7A8A9

ROWDECODER

COLUMNDECODER

REFRESHCONTROLLER

2048

SENSE AMPLIFIERS

I/O GATING

REFRESHCOUNTER

2048

A10

ROWADDRESSBUFFERS (11)

2048x2048x4MEMORYARRAY

RAS

NO. 1 CLOCKGENERATOR

VccVss

元器件交易网

TRUTH TABLE

ADDRESSES

FUNCTION

RAS

STANDBYREAD

WRITE: (EARLY WRITE )READ WRITEEDO-PAGE-MODE READ

1st Cycle2nd Cycle

EDO-PAGE1st Cycle

MODE WRITE

2nd Cycle1st CycleEDO-

PAGE-MODE

READ-WRITE2nd CycleHIDDENREFRESH

READWRITE

RAS-ONLY REFRESHCBR REFRESH

HLLLLLLLLLL→H→LL→H→L

LH→L

CASH→XLLLH→LH→LH→LH→LH→LH→LLLHL

WEXHLH→LHHLLH→LH→LHLXH

OEXLXL→HLLXX

ROWXROWROWROWROWn/aROWn/aROWn/aROWROWROWX

COLXCOLCOLCOLCOLCOLCOLCOLCOLCOLCOLCOLn/aX

High-ZData-OutData-ln

Data-Out,Data-lnData-OutData-OutData-InData-In

Data-Out, Data-InData-Out, Data-InData-OutData-InHigh-ZHigh-Z

1

DQS

Notes

L→HL→H

LXXX

Notes: 1. EARLY WRITE only.

元器件交易网

Absolute Maximum Ratings

Parameter

Voltage on any pin relative to Vss Supply voltage relative to Vss Short circuit output currentPower dissipationOperating temperatureStorage temperature

SymbolVTVCCIOUTPDTOPTTSTG

Value-0.5 to + 4.6-0.5 to + 4.6

501.00 to + 70-55 to + 125

UnitVVmAW

°C°C

Recommended DC Operating Conditions

Parameter/ConditionSymbol

Min

3.3 Volt Version

Typ3.3

Max

3.6

Unit

Supply Voltage

Input High Voltage, all inputsInput Low Voltage, all inputs

VCCVIHVIL

3.02.0-0.3

VVV

-VCC + 0.3-0.8

Capacitance

±10%, f = 1MHzTa = 25°C, VCC = 3.3V

Parameter

Input capacitance (Address)

Input capacitance (RAS, CAS, OE, WE)Output capacitance

(Data-in, Data-out)

SymbolCI1CI2CI/O

Typ ---

Max577

UnitpFpFpF

Note111, 2

Note: 1. Capacitance measured with effective capacitance measuring method. 2. RAS, CAS = VIH to disable Dout.

DC Characteristics :

(Ta = 0 to 70°C, VCC = + 3.3V ±10%, VSS = 0V)

ParameterSymbolTest Conditions

Min

AD404M42V-5Max120

Min--6Max110

UnitNotes

Operating current

ICC1

RAS cyclingCAS, cycling tRC = minLVTTL interfaceRAS, CAS = VIH Dout = High-ZCMOS interface≥VCCDout = High-Z

-mA1, 2

Low

powerS-version

ICC2

-0.5-0.5mA

-0.15-0.15mA

Standby Current

Standardpowerversion

LVTTL interfaceRAS, CAS = VIH Dout = High-ZCMOS interfaceRAS,CAS≥VCC-0.2VDout = High-Z

-2-2mA

-0.5-0.5mA

RAS- only refresh currentEDO page mode currentCAS- before- RAS refresh current

Self- refresh current(S-Version)

ICC3ICC4ICC5

RAS cycling, CAS = VIH tRC = mintPC = mintRC = min

RAS, CAS cycling

---

12090120

---

11080110

mAmAmAµA

1, 21, 31, 2

550ItRASS≥100µs

DC Characteristics :

(Ta = 0 to 70°C, VCC= +3.3V ±10%, VSS= 0V)

AD404M42V

-5

ParameterInput leakage currentOutput leakage currentOutput high VoltageOutput low voltageNotes:

1. ICC is specified as an average current. It depends on output loading condition and cycle rate when the device is selected. ICC max is specified at the output open condition.2. Address can be changed once or less while RAS = VIL.

3. For ICC4, address can be changed once or less within one EDO page mode cycle time.

SymbolILIILOVOHVOL

Test Conditions0V≤Vin≤VCC + 0.3V0V≤Vout≤VCC + 0.3VDout = DisableIOH = -2mAIOL = +2mA

2.4--0.4

2.4--0.4

VV

Min-5-5

Max

55

Min-5-5-6Max

55

µAµAUnit

Notes

AC Characteristics

(Ta = 0 to + 70°C, Vcc = 3.3V %, V±10ss = 0V) *1, *2, *3, *4

Test conditions

Output load: one TTL Load and 100pF (VCC = 3.3V ±10%) Input timing reference levels:

VIH = 2.0V, VIL = 0.8V (VCC = 3.3V ±10%) Output timing reference levels:VOH = 2.0V, VOL = 0.8V

Read, Write, Read- Modify- Write and Refresh Cycles(Common Parameters)

AD404M42V -5

Parameter

Random read or write cycle timeRAS precharge time

CAS precharge time in normal modeRAS pulse widthCAS pulse widthRow address setup timeRow address hold timeColumn address setup timeColumn address hold timeRAS to CAS delay time

RAS to column address delay timeColumn address to RAS lead timeRAS hold timeCAS hold time

CAS to RAS precharge timeOE to Din delay timeTransition time (rise and fall)Refresh period

Refresh period (S- Version)CAS to output in Low- ZCAS delay time from DinOE delay time from Din

SymboltRCtRPtCPNtRAStCAStASRtRAHtASCtCAHtRCDtRADtRALtRSHtCSHtCRPtOEDtTtREFtREFtCLZtDZCtDZO

Min84301050808081210258385121--000

Max

---1000010000

----3725-----5032128---Min1044010601001001014123010405151--000-6Max

---1000010000

----4530-----5032128---nsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsmsmsnsnsns

111089756

Unit

Notes

元器件交易网

Read Cycle

AD404M42V -5

Parameter

Access time from RASAccess time from CAS

Access time from column addressAccess time from OERead command setup timeRead command hold time to CASRead command hold time to RASOutput buffer turn-off time

Output buffer turn-off time from OE

SymboltRACtCACtAAtOEAtRCStRCHtRRHtOFFtOEZ

Min

----00000

Max50142512---1212

Min

----00000-6Max60153015---1515

nsnsnsnsnsnsnsnsns

710, 161617171213, 14 14, 15

Unit

Notes

Write Cycle

AD404M42V-5

Parameter

Write command setup time Write command hold timeWrite command pulse widthWrite command to RAS lead timeWrite command to CAS lead timeData-in setup timeData-in hold timeWE to Data-in delay

SymboltWCStWCHtWPtRWLtCWLtDStDHtWED

Min

0881380810

Max

--------Min

01010151001010-6Max

--------nsnsnsnsnsnsnsns

19197, 18

Unit

Notes

元器件交易网

Read- Modify- Write Cycle

AD404M42V

-5

Parameter

Read-modify- write cycle timeRAS to WE delay timeCAS to WE dealy time

Column address to WE delay timeOE hold time from WE

SymboltRWCtRWDtCWDtAWDtOEH

Min1086426398

Max

-----Min13377324710-6Max

-----nsnsnsnsns

181818

Unit

Notes

Refresh Cycle

AD404M42V -5

Parameter

CAS setup time (CBR refresh) CAS hold time (CBR refresh)RAS precharge to CAS hold timeRAS pulse width (self refresh)RAS precharge time (self refresh)CAS hold time (CBR self refresh)WE setup timeWE hold time

Symbol

tCSRtCHRtRPCtRASStRPStCHStWSRtWHR

Min

58510090-50010

Max

--------Min

5105100110-50010-6Max

--------Unitnsnsnsµsnsnsnsns

107Notes

EDO Page Mode Cycle

AD404M42V

-5

Parameter

EDO page mode cycle time

EDO page mode CAS precharge timeEDO page mode RAS pulse widthAccess time from CAS prechargeRAS hold time from CAS prechargeOE high hold time from CAS highOE high pulse width

Data output hold time after CAS lowOutput disable delay from WE

WE pulse width for output disable when

CAS high

SymboltPCtCPtRASPtCPAtCPRHtOEHCtOEPtCOHtWHZtWPZ

Min201050-30510537

Max

--10530----10-Min251060-35510537-6Max

--10535----10-Unitnsnsnsnsnsnsnsnsnsns

2010, 14Notes

EDO Page Mode Read Modify Write Cycle

AD404M42V-5

Parameter

EDO page mode read- modify- write cycle CAS precharge to WE delay time

EDO page mode read- modify- write cycle time

SymboltCPWtPRWC

Min4556

Max

--Min5568-6Max

--Unitnsns

Notes10

Notes :

1. AC measurements assume tT = 2ns.

µs 2. An initial pause of 100 is required after power up, and it followed by a minimum of eight

initialization cycles (RAS - only refresh cycle or CAS - before - RAS refresh cycle). If the internalrefresh counter is used, a minimun of eight CAS - before - RAS refresh cycles are required.

3. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data tothe device.

4. All the VCC and VSS pins shall be supplied with the same voltages. 5. tRAS(min) = tRWD(min)+tRWL(min)+tT in read-modify-write cycle.6. tCAS(min) = tCWD(min)+tCWL(min)+tT in read-modify-write cycle.

7. tASC(min), tRCS(min), tWCS(min), and tRPC are determined by the falling edge of CAS .

8. tRCD(max) is specified as a reference point only, and tRAC(max) can be met with the tRCD(max) limit.Otherwise, tRAC is controlled exclusively by tCAC if tRCD is greater than the specified tRCD(max) limit. 9. tRAD(max) is specified as a reference point only, and tRAC(max) can be met with the tRAD(max) limit.Otherwise, tRAC is controlled exclusively by tAA if tRAD is greater than the specified tRAD(max) limit. 10. tCRP, tCHR, tRCH, tCPA and tCPW are determined by the rising edge of CAS .

11. VIH(min) and VIL(max) are reference levels for measuring timing or input signals. Therefore, transition

time is measured between VIH and VIL.

≤RCD(max) and tRAD t≤RAD(max). If tRCD or tRAD is greater than the maximum 12. Assumes that tRCD t

recommended value shown in this table, tRAC exceeds the value shown. 13. Assumes that (max) andtRCD≥tRCDtRAD

≤tRAD(max).

14. Access time is determined by the maximum of tAA, tCAC, tCPA. 15. Assumes that (max) and (max). tRCD≤tRCDtRAD≥tRAD 16. Either tRCH or tRRH must be satisfied for a read cycle.

17. tOFF(max) and tOEZ(max) define the time at which the output achieves the open circuit condition (high

impedance). tOFF is determined by the later rising edge of RAS or CAS.

18. tWCS, tRWD, tCWD, and tAWD are not restrictive operating parameters. They are included in the data

sheet as electrical characteristics only. If (min), the cycle is an early write cycle and thetWCS≥tWCSdata out will remain open circuit (high impedance) throughout the entire cycle. If (min),tRWD≥tRWDtCWD

≥tCWD(min), (min) and (min), the cycle is a read-modify-write andtAWD≥tAWDtCPW≥tCPW

the data output will contain data read from the selected cell. If neither of the above sets of conditionsis satisfied, the condition of the data output (at access time) is indeterminate.

19. These parameters are referenced to CAS separately in an early write cycle and to WE edge in a

delayed write or a read-modify-write cycle.

20. tRASP defines RAS pulse width in EDO page mode cycles.

Timing Waveforms

Read Cycle

tRCRAS

tRP

RAS

t

CRP

t

CSH

t

RCD

tT

t

RSHt

CAS

t

CPN

t

RADtRAL

tASRt

RAHRow

t

t

CAHColumn

t

RRH

ADDRESS

t

RCSt

RCH

OE

OEAt

CAC

tAA

t

RAC

tOEZtOFFtOFF

DQ1~DQ4

tCLZ

DOUT

Early Write Cycle

t

RCtRAS

tRP

RAS

t

CSH

t

RCD

tt

RSHt

CAS

t

CRP

t

CPN

CAS

t

RAD

t

ASR

t

RAHRow

t

t

CAHColumn

tRAL

ADDRESS

ttWCStWCH

tDS

tDH

DQ1~DQ4

DIN

Delayed Write Cycle

t

RCtRAS

RP

RAS

t

CSH

t

RCD

tT

t

RSHtCAS

t

t

CPN

CAS

t

ASRt

RAHt

ASCt

CAH

ADDRESS

RowColumn

tCWL

tRCS

tRWLtWP

tOED

tOEH

tDS

tDS

tDH

DQ1~DQ4

OPEN

DIN

Read - Modify - Write Cycle

t

RWCRAS

ttt

RCD

t

CAS

t

CRPt

CPN

CAS

t

RAD

tASR

Row

t

RAH

t

ASC

t

CAH

ADDRESSColumnt

t

AWDt

CWLt

RWLtWP

t

DZC

tDS

tDH

DQ1~DQ4

OPEN

DIN

t

DZO

tOED

tOEH

tOEAtCACtAA

tOEZ

tRAC

DQ1~DQ4

DOUT

EDO Page Mode Read Cycle

t

t

tRP

t

CRP

t

CSH

t

CRP

t

RCD

t

CAS

tCP

tPC

t

CAS

tCP

t

RSHt

CAS

t

CPN

CAS

t

RAD

t

ASR

t

t

t

CAH

tASC

t

CAH

ttRALt

CAH

ADDRESS

RowColumn 1Column 2Column NRow

tRCS

t

RRHWEWE

tOEHC

tOEA

t

OEP

tOEA

OEOE

tRAC

tAA

tCPAtAA

tCPAtAAtOEZ

tCAC

tCACtCOH

tCAC

tOFF

tOEZ

tOFF

DQ1~DQ4

DOUT 1

DOUT 2

DOUT N

OPEN

EDO Page Mode Early Write Cycle

t

RASP

t

RP

RAS

tT

t

CSHt

RCD

tCAS

tCP

tPC

t

CAS

tCP

t

RSHtCAS

t

CRPt

CPN

CAS

t

ASR

t

RAH

t

ASC

t

CAHt

ASCt

CAHt

ASCt

CAH

ADDRESS

RowColumn 1Column 2Column N

tWCS

tWCHtWCStWCHtWCStWCH

WE

ttDHtDStDHtDStDH

DQ1~DQ4

DIN 1DIN 2DIN N

EDO Page Mode Read-Early-Write Cycle

tRASP

t

tRP

t

CRP

t

CSH

t

CRP

t

RCD

t

CAS

tCP

tPC

t

CAS

tCP

t

RSHt

CAS

t

CPN

CAS

t

CSHt

RAD

t

ASR

t

t

t

RAH

tASC

t

CAH

ttCALtRALt

CAH

ADDRESS

RowColumn 1Column 2Column NRow

tRCS

t

RCH

t

t

WCH

WEWE

tOEA

t

WED

OEOE

tRAC

tAA

tCPAtAA

tWHZ

tCAC

tCOH

ttDS

Data

Doutput 2

DataInput N

tDH

DQ1~DQ4

OPEN

Data

Doutput 1

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