电子科技大学2010期末数字电子技术考试题A卷-参考答案

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电子科技大学二零零九至二零一零学年第 二 学期期 末 考试

数字逻辑设计及应用 课程考试题 A 卷(120分钟)考试形式:闭卷 考试日期2010年7月12日

课程成绩构成:平时 20 分, 期中 20 分, 实验 0 分, 期末 60 分

复核人 一 二 三 四 五 六 七 八 九 十 合计 签名 得分 签名 得 分 一、To fill your answers in the blanks(1’×25)

1. If [X]10= - 110, then [X]two's-complement=[ 10010010 ]2,

[X]one's-complement=[ 10010001 ]2. (Assumed the number system is 8-bit long) 2. Performing the following number system conversions: A. [10101100]2=[ 000111010010 ]2421

B. [1625]10=[

0100100101011000 ]excess-3

10011000 ]8421BCD

C. [ 1010011 ]GRAY =[

3. If F??A,B,C(1,2,3,6), then FD??A,B,C( 1,4,5,6 )=?A,B,C(0,2,3,7 ). 4. If the parameters of 74LS-series are defined as follows: VOLmax = 0.5 V, VOHmin = 2.7 V, VILmax = 0.8 V, VIHmin = 2.0 V, then the low-state DC noise margin is 0.3V ,the high-state DC noise margin is 0.7V . 5. Assigning 0 to Low and 1 to High is called positive logic. A CMOS XOR gate in positive logic is called XNOR gate in negative logic.

6. A sequential circuit whose output depends on the state alone is called a Moore machine.

7. To design a \ 4 bit as least.

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8. If we use the simplest state assignment method for 130 sates, then we need at least 8 state variables.

9. One state transition equation is Q*=JQ'+K'Q. If we use D flip-flop to complete the equation, the D input terminal of D flip-flop should be have the function D= JQ'+K'Q . 10. Which state in Fig. 1 is ambiguous D

11. A CMOS circuit is shown as Fig. 2, its logic function z= A’B’+AB

Fig. 1 Fig. 2 12. If number [A]two's-complement =01101010 and [B]one's-complement =1001, calculate [A-B]two's-complement and indicate whether or not overflow occurs.(Assumed the number system is 8-bit long) [A-B]two's-complement = 01110000 , overflow no 13. If a RAM’s capacity is 16K words × 8 bits, the address inputs should be 14 bits; We need 8 chips of 8K ?8 bits RAM to form a 16 K ? 32 bits ROM.. 14. Which is the XOR gate of the following circuit A .

15. There are 2n-n invalid states in an n-bit ring counter state diagram. 16. An unused CMOS NOR input should be tied to logic Low level or 0 . 17. The function of a DAC is translating the Digital inputs to the same value of analog

outputs.

二、Complete the following truth table of taking a vote by A,B,C, when more than two of A,B,C approve a resolution, the resolution is passed; at the same time, the resolution can’t go through if

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A don’t agree. For A,B,C, assume 1 is indicated approval, 0 is indicated opposition. For the F, assume 1 is passed, 0 is rejected.(5’) A B C F 0 0 0 0 1 1 1 1

三、The circuit to the below realizes a combinational function F of four variables. Fill in the Karnaugh map of the logic function F realized by the multiplexer-based circuit. (6’)

0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 0 1 1 1 DC BA 00 01 11 10 00 1 1 01 1 1 11 1 1 10 1 1

四、(A) Minimize the logic function expression

F = A·B + AC’ +B’·C+BC’+B’D+BD’+ADE(H+G) (5’)

F = A·B + AC’ +B’·C+BC’+B’D+BD’ = A·(B ’C)’ +B’·C+BC’+B’D+BD’

= A +B’·C+BC’+B’D+BD’+C’D (或= A +B’·C+BC’+B’D+BD’+CD’)

= A +B’·C+BD’+C’D (或= A + BC’+B’D+CD’)

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(B) To find the minimum sum of product for F and use NAND-NAND gates to realize it(6’)

F(W,X,Y,Z)?Π(1,3,4,6,9,11,12,14)

WX YZ 00 01 11 10

------3分 F= X’Z’+XZ -----2分 =( X’Z’+XZ)’’=(( X’Z’)’(XZ)’)’ ------1分

五、Realize the logic function using one chip of 74LS139 and two NAND gates.(8’)

00 1 1 01 1 1 11 1 1 10 1 1 F(A,B,C)??(2,6) G(C,D,E)??(0,2,3)

F(A,B,C)=C’∑(1,3) ---- 3分 G(C,D,E)=C’∑(0,2,3) ----3分

Function table for a 1/2 74x139 Inputs Outputs G_L B A Y3_L Y2_L Y1_L Y0_L 1 X X 1 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 1

WX YZ 00 01 11 10 00 1 1 01 1 1 11 1 1 10 1 1 WX YZ 00 01 11 10 00 1 1 01 1 1 11 1 1 10 1 1 第 4 页 共 9页

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-

六、Design a self-correcting modulo-6 counter with D flip-flops. Write out the excitation equations and output equation. Q2Q1Q0 denote the present states, Q2*Q1*Q0* denote the next states, Z denote the output. The state transition/output table is as following.(10’)

Q2Q1Q0 000 100 110 111 011 001 Q2*Q1*Q0* 100 110 111 011 001 000 Z 0 0 0 0 0 1 激励方程式:D2=Q0’ (2分,错 -2分)

D1=Q2 (2分,错 -2分) D0=Q1 (2分,错 -2分)

修改自启动:D2=Q0 +Q2Q1’ (1分,错 -1分)

D1=Q2+Q1Q0’ (1分,错 -1分) D0=Q1+Q2Q0 (1分,错 -1分)

输出方程式:Z=Q1’Q0 (1分,错 -1分)

得 分

七、Construct a minimal state/output table for a moore sequential machine, that will detect the input sequences: x=101. If x=101 is detected, then Z=1.The input sequences DO NOT overlap one another. The states are denoted with S0~S3.(10’)

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For example:

X: 0 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 0 0 1 1 …… Z: 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 ……

state/output table

S X 0 1 Z S0 S0 S1 0 S1 S2 S1 0 S2 S0 S3 0 S3 S0 S1 1 S*

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(10’)

Transition/output table State/output table Excitation/output table

Q2Q1 00 01 10 11 X 1 0 01 11 00 10 01 01 01 01 Q2*Q1* Z 1 1 0 1 X S Z Q2Q1 1 0 A B D 1 00 B A C 1 01

C B B 0 10 D B B 1 11 S*

X 1 0 01 11 00 10 01 01 01 01 D2 D1 Z 1 1 0 1 (4分) (3分) (3分)

评分标准:

转移/输出表正确,得4分;每错一处扣0.5分,扣完4分为止;

由转移/输出表得到状态/输出表正确,得3分;每错一处扣0.5分,扣完3分为止;

激励/输出表正确,得3分;每错一处扣0.5分,扣完3分为止。

九、Clocked Synchronous State Machine Design(15’)

74x163 is a synchronous 4-bit binary counter with synchronous CLEAR input and

LOAD input. LD_L=(QBQC)', CLR_L=(QD'QB )' in the following circuit. 1. Finish the logic circuit.

2. Draw the state diagram with all states of “Q3Q2Q1Q0” . (“Q3Q2Q1Q0” is the output of 74x163)

3. Write the sequence of Y. Y is the output of 74x151. (Assumed state of 74x163 start in

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Q3Q2Q1Q0=0000.)

7415174163001111LDNABCDENTENPCLRNCLKinstQAQBQCQDRCOQ0Q1Q2Q3CLOCKCOUNTER010011100ABCD0D1D2D3D4D5D6D7GNinst1YWNYMULTIPLEXER

Function table for a 74x163 Inputs CLR_L LD_L ENT ENP 0 X X X 1 0 X X 1 1 0 X 1 1 X 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 解答:

Current State Next state Output QD QC QB QA QD* QC* QB* QA* RCO X X X X 0 0 0 0 0 X X X X D C B A 0 X X X X QD QC QB QA 0 X X X X QD QC QB QA 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 1 0 0 0 1 1 0 1 0 0 0 …………. ………….. 0 1 1 1 1 0 0 0 0 1

(1) Finish the logic circuit.(见下页图) LD_L=(QBQC)', CLR_L=(QD'QB )'--4分 (2) Q3Q2Q1Q0: 清零优先级高于置数 0000—0001—0010—0000 0011—0000

0100—0101—0110—0000 0111—0000

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1000—1001—1010—1011--1100—1101—1110--1100

1111—1100 -------7分 (3) Y=0100111111 -------4分

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