Fault Sensitivity Analysis and Reliability Enhancement of Analog-to-Digital Converters
更新时间:2023-08-20 11:34:01 阅读量: 高等教育 文档下载
- fault翻译推荐度:
- 相关推荐
Abstract — Reliability of systems used in space, avionic and biomedical applications is highly critical. Such systems consist of an analog front-end to collect data, an Analog-to-Digital Converter (ADC) to convert the collected data to digital form and a
1
FaultSensitivityAnalysisandReliabilityEnhancementofAnalog-to-DigitalConverters
MandeepSingh,Member,IEEE,andIsraelKoren,Fellow,IEEE
Abstract—Reliabilityofsystemsusedinspace,avionicandbiomedicalapplicationsishighlycritical.Suchsystemsconsistofananalogfront-endtocollectdata,anAnalog-to-DigitalCon-verter(ADC)toconvertthecollecteddatatodigitalformandadigitalunittoprocessit.Thoughconsiderableamountofresearchhasbeenperformedtoincreasethereliabilityofdigitalblocks,thesamecannotbeclaimedformixedsignalblocks.Thereliabilityenhancementwhichweemploystartswithfaultsensitivityanalysisfollowedbyredesign.Thedataobtainedfromthesensitivityanal-ysisisusedtogradeblocksbasedontheirsensitivitytofaults.Thehighlysensitiveblockscanthenbereplacedbymorereliablealter-natives.Theimprovementgainedbyoptingformorerobustim-plementationsmightbelimitedduetothenumberofpossibleim-plementations.Inthesecasesalternativereliabilityenhancementtechniquessuchasaddingredundancymayprovidefurtherim-provements.ThestepsinvolvedinthereliabilityenhancementofADCsareillustratedinthispaperby rstproposingasensitivityanalysismethodologyforα-particleinducedtransientsandthensuggestingredesigntechniquestoimprovethereliabilityoftheADC.Anovelconceptofnodeweightsspeci ctoα-particletran-sientsisintroducedwhichimprovestheaccuracyofthesensitivityanalysis.Thefaultsimulationsshowthat,usingtechniquessuchasalternativerobustimplementations,addingredundancy,patterndetectionandtransistorsizing,considerableimprovementsinre-liabilitycanbeattained.
IndexTerms—FaultTolerance,FaultSensitivity,Analog-to-DigitalConverters,Alphaparticles,Reliability,TransientFaults
I.INTRODUCTION
Criticalsystemsusedinspace,avionicsandbiomedicalap-plicationshavetobehighlyreliablesincetheeffectofafaultinthesesystemscanbecatastrophic.Thereliabilityofthesesys-temscanbeincreasedbyredesigningthemforimprovedfaulttolerance.Thesystemunderredesignundergoesafaultsensi-tivityanalysisbeforeandaftertheredesigntogaugethereliabil-ityimprovement.Faultsensitivityanalysisinvolvesinjectionoffaultseitherintheactualhardwareorinsoftwarethroughsimu-lation.Thelattermethodispreferablesincetheformerrequiresaprototypewhichisexpensive.Thelatteralsoenablesanearlyanalysisinthedesignphasethuseliminatingcostlyredesign.Twotypesoffaultshavebeenknowntoaffecttheproperworkingofacircuit:permanentandtransient.Whereasper-manentfaultscanbeintroducedduringthefabricationstageandinthe eld,transientfaultsarecausedinthe eldduetoElectroMagneticInterference(EMI)suchaspowertransients,
M.SinghiswithAdvancedMicroDevicesintheComputationProductsGroup,Austin,TX78704USA.
I.KoreniswiththeDepartmentofElectricalandComputerEngineering,Uni-versityofMassachusetts,Amherst,MA01003,USA.
ThisworkhasbeensupportedinpartbyNSFundercontractMIP-9710130andbyJPLundercontract961294.
crosstalkandvariousparticlehitsinradiationintenseenviron-mentslikespace.Theeffectoftransientfaultsistotemporarilychangethebehaviorofthecircuitoftenresultinginerroneousoutputs.Thistypeoffaultshasbeenknowntoaccountfor85%ormorefailuresindigitalsystems[1],[2].Sincethismightbecatastrophicincriticalapplications,thesecircuitsusuallyincor-poratesomemeasurestoincreasetheirfaulttolerance.
Thereliabilityofasystemisdeterminedbythefaulttoler-anceofitsconstituentblocks.Systemsinspace,biomedicalandavionicsapplicationsconsistofananalogfront-endtocol-lectdataforcontrolandobservationpurposesandadigitalunitwhichprocessesthecollecteddata.Digitalcircuitshavebeenstudiedextensivelyfortheirsensitivitytotransientfaults[3],[4]andmanytechniqueshavebeensuggestedtoimprovetheirfaulttolerance[4],[5].Incontrast,verylittlehasbeendonetoaddresstheissueoffaulttoleranceinanalogcircuitsandADCswhichareintegralpartsofalmostallmixed-signalcir-cuits.Hence,itisnecessarytoexploretechniquestoincreasethefaulttoleranceofADCs.Theprocessofincreasingthetol-eranceofacircuittotransientfaultscanbedividedintotwosteps:
(i)Gradingblocksofthecircuitbasedontheirsensitivities
totransientfaultsandidentifyingcritical(i.e.,mostsensi-tive)blocks.
(ii)Increasingthefaulttoleranceoftheidenti edcritical
blocks.Thisworkaddressesbothofthesestepsby rstproposingamethodologytoanalyzethesensitivityofanADCandthenbysuggestingtechniquestoincreasethereliabilityoftheADC.Thefaultinjectionexperiments,forgaugingthesensitivityofthedesignsaddressedinthiswork,wereperformedforα-particleinducedtransients.Thisisbecauseα-particleshavebeenidenti edasoneoftheenergeticnuclearparticlesthatcancauseatransientfault.However,thetechniquesdevelopedforthesefaultscanbeextendedtotransientfaultscausedbyothersources.α-particlesarefoundinspace[6]andintraceamountsinICsonthegroundduetodecayofradioactiveele-mentspresentinthepackagingmaterialorsolder[7].Thus,theapplicabilityofthisworkisnotrestrictedtosystemsinouterspacebutalsotoothergroundbasedcriticalsystems.
Thispaperisorganizedasfollows,SectionIIpresentsatax-onomyforADCsandprovidesabrieffunctionaldescriptionoftheADCsaddressedinthiswork.SectionIIIdescribesthesen-sitivityanalysismethodologyused.InSectionIVtheprocessofincreasingreliabilitybyoptingforrobustimplementationsandbyintroducingredundancyisdiscussed.SectionVsummarizesthe ndingsofthisworkandSectionVIdiscussesfuturework.
Abstract — Reliability of systems used in space, avionic and biomedical applications is highly critical. Such systems consist of an analog front-end to collect data, an Analog-to-Digital Converter (ADC) to convert the collected data to digital form and a
Fig.3.SuccessiveApproximationarchitecture
Fig.1.A ash
ADC
ENC EncoderCLK Clock
INT Interpolator
SHA Sample & Hold AmpliflierREF Reference Voltage Generator
FA* Folding AmpliflierC* ComparatorL* Latch
Fig.4.SuccessiveApproximationADC
Fig.2.A4-bitFoldingandInterpolatingADC
II.ANALOG-TO-DIGITALCONVERTERS
AnalogtoDigitalConvertersareintegralpartsofdataacqui-sitionsystemsandactasaninterfacebetweenanalogblocksthatacquirethedataanddigitalblocksthatprocessthedata.ADCscanbebroadlyclassi edintohigh-speedandhigh-accuracyarchitectures.High-speedarchitecturesinclude ash,foldingandinterpolating,pipelined,multi-stepandinterleavedADCs[8].High-accuracyarchitecturesincludesuccessiveap-proximation,delta-sigmaandintegratingADCs[8].Thesetwocategoriestradeoffspeedvsaccuracy.Basedonthedemandsoftheapplication,oneoftheseADCscanbechosenaftercarefullyweighingthetradeoffs.Thefollowingsectionsbrie ydescribetheworkingoftheADCswhichhavebeenaddressedinthiswork.
A.FlashADC
Thisarchitectureisconceptuallythesimplestandpotentiallythefastest.Itemploys“parallelism”and“distributed”samplingtoachievehighconversionspeeds.Figure1showsablockdi-agramofanm-bit ashADC.Thecircuitconsistsof2mcom-parators,aresistorladdercomprising2mequalsegmentsandadecoder.Theladdersubdividesthemainreferenceinto2mequallyspacedvoltages,andthecomparatorscomparethein-putsignalwiththesevoltages.Forexample,iftheanaloginputisbetweenVjandVj+1,comparatorsA1throughAjproduce1sattheir
outputswhiletherestgenerate0s.Consequently,thecomparatoroutputsconstituteathermometercodewhichisconvertedtobinarybythedecoder.
B.FoldingandInterpolatingADC
Thelargeinputcapacitanceposedbythecomparatorsattheinputof ashADCsledtotheadventoffoldingandinterpolat-ing(FI)ADCs[9].FIADCsfoldtheinformationrepresentedbythereferencevoltageswhichcharacterizethequantizationlevels.Figure2showstheblockdiagramofa4-bitfoldingandinterpolatingADC.TheFAblocksinFigure2arefoldingam-pli ers,eachoneofwhichisaseriesofcross-coupleddifferen-tialstages[9].Thesampleandholdampli er(SHA)samplestheinputandfeedsittotwofoldingampli ers(FA1andFA2)andacomparator(CM)whichgeneratesthemostsigni cantbit.TheINTblockinterpolatesbetweenthefoldingampli eroutputs.TheINTblockoutputisfedtotheencoder(ENC)whichgeneratesthethreeleastsigni cantbitsofthe naldigi-taloutput.
C.SuccessiveApproximationADC
TheSuccessiveApproximation(SA)ADCsprogresslikeabinarysearchalgorithmtoarriveatthe naldigitaloutputwithanerrorofnomorethanhalftheleastsigni cantbit.Figure3illustratesthesuccessiveapproximationarchitecture,whichconsistsofafront-endSHA,acomparator,aregister(shift)andaDigital-to-AnalogConverter(DAC).The(shift)registerholdsthebitsthathavebeenconvertedstartingfromthemostsigni cantbit(MSB).ThisdigitalpatternisthenconvertedbytheDACtoanalogandthisvalueiscomparedagainsttheheldinput.Theoutputofthecomparatordecidesthevalueofthenextbit.Thus,the nalm-bitdigitalpatternisgeneratedinsuchamannerstartingfromtheMSBtotheleastsigni cantbittakingmcyclestogenerateanm-bitoutput.SuccessiveapproximationconvertersthatincorporatecapacitorDACsareusuallybasedonthechargeredistributionprinciple.Figure4showstheblockdiagramofachargeredistributionimplemen-tationofthesuccessiveapproximation(SA)[10]ADC.Forthiswork,anSAADCbasedonchargeredistributionwasimple-mented.TheprinciplecanbeillustratedusingFigure4,wheretheDACconsistsofbinary-weightedcapacitorsC1···Cn 1
Abstract — Reliability of systems used in space, avionic and biomedical applications is highly critical. Such systems consist of an analog front-end to collect data, an Analog-to-Digital Converter (ADC) to convert the collected data to digital form and a
x(n 6)DFF
x(n 7)
(Z)
x(n 1)
x(n)
DFF(Z)
1 1
x(n 5)DFF(Z)
x(n 2)DFF(Z)
1 1
x(n 4)DFF(Z)
DFF
x(n 3)DFF(Z)
1 1
Digital Decimation
Modulator
(Z)
1
Filter
h(0)h(1)h(2)h(3)
Fig.5. -ΣADC
y(n)
Fig.7.ADigitalDecimationFilter
aroundthemainlobe,andtherefore,onlyfourcoef cients(h(0)
toh(3))arerequired.
III.FAULTSENSITIVITYANALYSIS
Therearedifferentapproachestoinvestigatetheeffectsoftransientfaults.Hardwareprototypinghasbeenused[11]butistootimeconsumingandexpensive.Simulationbasedap-proachesincludeexhaustiveandMonte-Carlomethods.Ex-haustivesimulationsareaccuratebutbecomeintractableforlargedesigns.Monte-Carlomethods,thoughtractableforlargedesigns,arenotasaccurate.SincetheADCswhichhavebeenanalyzedinthisworkarerelativelysmall,wepreferredthemoreaccurateexhaustivesimulationapproachandusedHspice[12]forthispurpose.Thefollowingsectiondiscussesthetheo-reticalbasisforthefaultsensitivityanalysismethodologyusedforthiswork.Wepresentthetransientfaultmodelusedfortheanalysisandthetheoreticalbasisforthefaultsensitivityanal-ysismethodologyused.Wealsoillustratethevariouskindsofanalysisthatcanbeperformedwiththedataobtainedfromafaultsimulationrun.A.TransientFaultModel
Severaltransientfaultmodelshavebeenproposedin[13],[14].Sincethisworkconcentratesonα-particleinducedtran-sients,thedoubleexponentialα-particletransientmodelfortheinjectioncurrentproposedin[13]isused.Theinjectioncurrentduetoanα-particlestrikeonanode,denotedbyIinj,isgivenby
Iinj(t)=I0(e t/τ1 e t/τ2)(1)whereI0isthemaximumcurrent,τ1isthecollectiontimecon-stantforajunctionandτ2istheiontrackestablishmenttime
constant.Thetimeconstantsdependonseveralprocessrelatedfactors,andinthiswork,thetimeconstantsgivenin[15]areused:τ1=1.63×10 10secandτ2=0.5×10 10sec.I0canbecalculatedby
Qinj
I0=(2)
τ1 τ2whereQinjisthechargeinjectionlevelinCoulombs.Chargeinjectionlevelisafunctionoftheangleatwhichtheα-particlehits.I0canbepositiveornegativedependingonwhethertheα-particlehitsanNMOSdrainoraPMOSdrain[15].FigureFig.6. -ΣModulator
(Cj=2·Cj 1,j=2,···,n 1andC1=C0).Inthesam-plingmodethebottom-plateisgrounded(inCLinFigure4) 1toVrefaccordingtoabinarysearchalgorithm,suchthatthetopplateeventuallybecomes0.TheobjectiveduringtheconversionistodrivetozerothedifferencebetweentheDAC(convertlatch)outputandthesam-pledinput.Onebitisconvertedineachcycle,startingwiththemostsigni cantbit.Aprecisecapacitormatchingisrequiredforthisconversion.Currentfabricationtechnologiescatertothisrequirementquiteeffectively.D. -ΣADC
The -ΣADCfallsunderthecategoryofoversamplingconverterswhichhavebecomepopularforhigh-resolution,medium-to-lowspeedapplicationssuchashigh-qualitydigitalaudio.Figure5showstheblockdiagramofa -ΣADC.The -Σmodulatorisananalogcomponentandthedigitaldecimation lterisadigitalcomponent.Themostcommonimplementationofthe -Σmodulator(showninFigure6)pro-videsanoversampledserialoutputwhichisadigitalrepresen-tationoftheinputsignal.Thisserialoutputthusobtainedhashighfrequencynoiseinadditiontothesignalinformation.Thedigitaldecimation lterstage,followingthemodulator, ltersoutthisnoiseandprovidesahighresolutionoutput.Adigitallowpass lterrealizationinvolvesamultiplicationoftheserialbitpatternwithcoef cientswhichrepresentthesincfunction.Sinceanidealsincfunctionwouldneedanin nitenumberofcoef cients,practicalcasesimplementawindowedsincfunc-tion.Figure7showsablockdiagramofan8-pointdigital-decimation lter.DFFisadelayelementandx(i)istheserialinputattheithtimeinstance.Thecoef cientsaresymmetrical
Abstract — Reliability of systems used in space, avionic and biomedical applications is highly critical. Such systems consist of an analog front-end to collect data, an Analog-to-Digital Converter (ADC) to convert the collected data to digital form and a
Fig.8.(a)α-particlehitonthedrainofaPMOStransistor(b)Theα-particlehitmodeledasacurrentsource
0.020.0180.0160.014
1pC2pC3pC4pC5pC
Fig.10.Thesensitiveandinsensitivepartsofanode
0.0120.010.0080.0060.0040.002
00
1
2
3
4
5
6
Time (ns)
Fig.9.Currentpulsegeneratedasaresultofanα-particlestrike
8(a)showsthedrainofaPMOStransistorandtheeffectoftheinjectedcharge.Anα-particlehitgenerateselectron-holepairsalongitstrajectory.Thesechargecarriersdriftunderthein u-enceoftheelectric eldacrossthejunctiongivingrisetoaninjectioncurrent(Iinj)thatcanbemodeledbyequation(1).Vistheinitialvoltageonthenode(drainofthePMOS),dVisthevoltagechangeduetotheα-particlehitandisdependentonIinjandtheloadconnectedtothenode.Figure8(b)showsthecurrentsourceequivalentmodelofthetransientfaultcausedbyanα-particlehit.Figure9showsthecurrentpulsesthataregen-eratedasaresultofanα-particlehitfordifferentvaluesoftheinjectioncharge.Thus,anα-particlehitonacircuitnodecanbesimulatedbyconnectingacurrentsourceinjectingacurrentpulseofIinjatthesaidnode.B.TheoreticalBasis
Traditionally,faultconditionsinsimulationstrategieshavebeenvariedalongthreedimensions:space,timeandinjectionlevel.Itisimportanttoconsidervaryingtheinputstothecircuitaswell,sincethiscanhaveabearingonselectingcriticalblocksforredesign.Thisisduetothefactthatablockidenti edasacriticalblockforoneinputmaynotbeassensitiveforanotherinput.Hence,criticalblocksshouldbeidenti edbasedonthedistributionoftheinputvalues.Thecircuitshouldbeoptimizedforinputvalueswhicharethemostprobable.
Thedesign owofADCscanbebroadlyclassi edintothreesteps:1)Choosingthearchitecturebasedontherequirementsandspeci cations
oftheapplication.2)Schematicentryoftheselectedarchitectureandfunctionalveri cation.3)Finallayoutdesignofthecircuitandare-veri cationwithparasitics.Sincefaultconditionshavetobevariedspatially,thephysicaldesignstep(3)isthemostsuitablepointtocarryoutthefaultsensi-tivityanalysis.However,thecomplexityofthedesigneffort
fori=1,2,···,nwherenisthenumberofcircuitnodesinablock.ThePOFisnowde nedas
n1
Ei(4)POF=
ni=1
neededtocreatethelayoutemphasizestheneedtomovetheanalysistoanearlierstage.Whenmovingthefaultsensitivityanalysisupinthedesigncycleweexpecttoreducethenumberoftimeconsumingdesigniterations,butshouldalsoexpecttopayapenaltyintermsofaccuracyoftheresults.
Faultsensitivityanalysisatthetransistorlevelschematiccanbedonebyselectingnodesinthecircuitandinjectingα-particletransientsatthesenodes.Wede nethefaultsensitivityofablockastheprobabilitythatanα-particlehittingtheblockwillresultinacircuitfailureandwedenoteitbyPOF(ProbabilityofFailure).Foragiveninputvoltage,POFiscalculatedasfollows.Anα-particletransientisinjectedintoeachnodeoftheblockandwedenotetheoutcomeoftheexperimentbyEi:
1iftheinjectionintonodeiresultsin
afailureEi=(3)
0otherwise
Current (A)
Thiscalculationassignsequalweightstoallnodes,whichmaycauseinaccuraciessincetheareasofdifferentnodesmayvaryconsiderably.Ahigheraccuracycanbeachievedbyas-signingtoeachnodeaweightwhichisproportionaltotheareathatitconsumes[16].However,acircuitnodemaymapontotwotypesofareainthelayout:fault-insensitivearea(inter-connect)andfault-sensitivearea(terminalsoftransistorscon-nectedtothenode)(seeFigure10).Itisknownthatanα-particlehithasapotentialofresultinginanerroronlyifithitstheactivearea(fault-sensitivearea)ofatransistor[4].Ahitattheinterconnect(fault-insensitivearea)willnotcauseatran-sientfaultbecauseofthelackofasigni cantelectric eldinthatarea.Wetherefore,assigntonodeiaweight,denotedbywi,givenby
As,i
(5)wi=i=1As,iwhereAs,iistheareaofthefault-sensitiveportionofnodei.ThesizesofthetransistorsintheschematicscanserveasagoodestimateforAs,i.WenowcalculatethePOFas
POF=
n i=1
wiEi(6)
Abstract — Reliability of systems used in space, avionic and biomedical applications is highly critical. Such systems consist of an analog front-end to collect data, an Analog-to-Digital Converter (ADC) to convert the collected data to digital form and a
TABLEI
POF
OVERALLARECOMPARISONFORREPRESENTATIVE(1.25V,1.85V,2.35V)VSCOMPLETE(1.05VTO2.55VINSTEPSOF0.1V)INPUTSFOR
THE4-BITFLASHADC
Fig.11.WeightedvsNon-weighted(logscale)approachfortheFIADC(averagedoverallinputs)
Fig.12.WeightedvsNon-weightedapproachfortheSAADC(averagedover
allinputs)
Figures11and12showtheblocksensitivitiesfortheFIandSAADCs,respectively,withthenon-weightedandtheweightedapproach.These guresshowthatthelessaccuratenon-weightedanalysismayleadtoincorrectconclusions.Forexam-ple,SHAinFigure11hasthehighestblocksensitivityaccord-ingtothenon-weightedanalysisbuthasaconsiderablylowersensitivitythanFA1andFA2accordingtotheweightedanal-ysis.Eventhemoreaccuratesensitivitymetricpresentedin(6)treatsallfaultsuniformly.However,somefaultsmayre-sultinlargererrorsattheADCoutputthanotherfaults.Hence,anothermetric,namely,therelativeerrordenotedbyErel,isproposed.Erelisgivenby
Erel= V/Vexp,
V=|Verr Vexp|
(7)
wherepisthenumberofinputvaluesforwhichthesimulationwasperformed,qisthenumberofinjectionlevelsconsideredandristhenumberoftimeinstancesatwhichfaultswerein-jected.Erel,iiscalculatedusing(7)andwiiscalculatedusing(5).TheMaximumRelativeError(MRE)canbeusedasanad-ditionalmetricwhichprovidestheworstcasemagnitudeoftheerror.ThechoiceofametricforsensitivityanalysisisbasedonthedesignobjectivesandnotontheADCarchitecture.Ourearlierworkin[17]hasshownthattheuseoftheAREmetricmaysometimesmasksensitivityimprovements.Therefore,thechoiceofametric(POF,ARE)togaugethesensitivityshouldbebasedonwhetherthecandidateapplicationrequiresareduc-tioninthefrequencyoferrorsorthemagnitudeoferror.Basedontherequirementsofthesystem,anappropriatemetriccanbechosenforthefaultsensitivityanalysis.FollowingarethestepsinvolvedinthefaultsensitivityanalysisofanADC:(i)Calculateweightsofthenodes(wi).
(ii)Performtransientfaultsimulationsonallnodes.
(iii)Basedonthedesignobjectives,useequation(6)or(8)to
calculatethesensitivityoftheconstituentblocks.
Inthiswork,thereductionoffrequencyoferrorsfortheFIandSAADCs,andreductionofrelativesizeoferrorsforthe ashand -ΣADCsweretheassumeddesignobjectives.Therefore,POFhasbeenusedasthesensitivitymeasurefortheFIandSAADCs,andAREhasbeenusedforthe ashand -ΣADCs.C.ADCSensitivityAnalysis
Transientfaultinjectionexperimentswereperformedon4-bittransistorlevelimplementationsofsuccessiveapproxima-tion,foldingandinterpolating, ashand -ΣADCs.There-sultsobtainedfromthesimulationshavebeenusedtogradethefaultsensitivitiesoftheblocksintheADC.Itisessentialtovarytheinputsinthesensitivityanalysisasitcanhaveabearingonselectingcriticalblocksforredesign.However,per-forminganexhaustivesimulationforallpossibleinputsispro-hibitivelyexpensive.Therefore,aschemeofselectingthreerepresentativeinputs,oneeachinthelower,middleandup-perinputrangesandperformingexhaustivesimulationonlyforthoseinputs,wasstudied.Thisstudywasperformedontheanaloganddigitalblocksofa4-bit ashADC.Thesimula-tionswereperformedforeightinjectionlevelsandfourtimeinstancesforeachnode.TheAREandPOFobtainedwiththerepresentativeinputsandwiththecompleterangeofinputs(ataquantizationstepof0.1v)werecompared.TablesIandIIshowthattheAREandPOFforbothcasesarereasonablyclose.Therefore,thesimulationsintheremainingpartsofthisworkwhereVexpistheexpectedcorrectoutputandVerristheerro-neousoutput.
Basedonthede nitionofrelativeerror,auni edmetriccalledtheAverageRelativeError(ARE)whichincludesthemagnitudeoferror,isproposed.IncontrasttothePOFwherealltheerrorsaretreateduniformly,AREgivesmoreweighttoα-particlehitswhichcauselargerrelativeerrorsattheADCoutput.Thesensitivity,characterizedbytheARE,isgivenby
ARE=
n i=1
¯rel,iwiE
(8)
¯rel,iistheaveragerelativeerrorduetoaninjectionatwhereE
nodeiandiscalculatedusing
¯rel,iE
k
1
Erel,i,=
ki=1
k=p·q·r(9)
Abstract — Reliability of systems used in space, avionic and biomedical applications is highly critical. Such systems consist of an analog front-end to collect data, an Analog-to-Digital Converter (ADC) to convert the collected data to digital form and a
TABLEII
POF
1
0.1
OVERALLPOFCOMPARISONFORREPRESENTATIVEVSCOMPLETE
INPUTSFORTHE4-BITFLASHADC
0.01
0.001
TABLEIII
FLASHADC
BLOCKSENSITIVITY,
0.0001
Fig.14.
Blocksensitivity(logscale)variationwithinjectionlevels(FI),p=3,r=4
0.1
SHAFA1
q=8,r=4
POF
0.01
1
0.1
0.001
012345678
Charge Injected (in pC)
POF
0.01
Fig.15.Blocksensitivities(logscale)variationwithinjections(FI),p=3,r=4
0.001
1Maximum Relative Error
0.0001
0.8
Fig.13.Blocksensitivity(logscale)variationwithinputsfortheFIADC,q=14,r=4
0.6
0.4
havebeenperformedforonerepresentativeinputinthelower,middleandupperinputranges.
1)FlashADC:TheAREmetric(8)wasusedforevaluatingthesensitivityoftheblocksina ashADC.TableIIIshowsthattheanalogblockofthe ashADCwhichcomprisesofcompara-torsismoresensitivethanthedigitalblock.Itisalsoseenthattheanalogblockremainsmoresensitivethanthedigitalblockforalltheinputsubrangesconsidered.Thus,forthe ashADCtheanalogblockisidenti edasthecriticalblock.
2)FoldingandInterpolatingADC:ThevariationsofthesensitivityofthisADCtochangesininputvoltageandlevelofinjectionwereinvestigated.ThePOFmetric(6)wasusedforevaluatingthesensitivityoftheindividualblocks.Theana-logblockinthisADCwasfurtherpartitionedasitcomprisedofmorecomponentsasopposedtothe ashADCwhereintheanalogblockcomprisedofcomparatorsonly.Figure13showsthesensitivitiesoftheblocksforthethreeinputlevels.This g-ureshowsthatthesensitivitiesofsomeblockstoα-particlehitsvaryfromoneinputvaluetoanother(C2andC3inFigure13).Thecomparators(C1throughC4)inFIwerefoundtobemoresusceptiblewhentheiroutputisalogic0.ThiscorrespondstoanADCinputintherangeof1.42-1.52vforthecompara-torC2.Hence,itcanbeconcludedthatC2isrelativelymoresensitiveintheseinputranges(asisshowninthebargraphcor-respondingtoaninputof1.5vinFigure13).Figure14showsthatthesensitivitiesofblocks
donotvaryconsiderablyifthe
0.2
Fig.16.Maximumrelativeerror(FI),p=3,q=14,r=4
injectionlevelismorethan6pico-Coulomb(pC).Thus,thereisnoneedtorepeatthesensitivityanalysisforinjectionslevelsbeyond6pC.
Figure15showsthatforlowerinjectionlevelstheorderingofcriticalblocksmightchange(SHAismoresensitivethanFA1from0pCto0.25pC).This gurealsoshowsthatbeyondacertaininjectionlevelthereisnofurtherincreaseinblocksensi-tivity.Figure16showsthemaximumrelativeerrorduetoeachblock.Theresultsagainshowthataswegettoblocksclosertotheinputthemaximumrelativeerrorincreases,reachingapeakforthesampleandholdampli ers(SHAinFigure16).Thus,theSHAandFAblockshavebeenidenti edascriticalblocksfortheFIADC.
3)SuccessiveApproximationADC:ThePOFmetric(6)wasusedforevaluatingthesensitivityoftheblocksintheSuc-cessiveApproximation(SA)ADC.Figure17showsthesensi-tivitiesoftheblocksforthethreerepresentativeinputs.Itisev-identfromthis gurethatthesensitivitiesofsomeblockstoα-particlehitsvaryfromoneinputvaluetoanother(outputlatch,convertlatchinFigure17).Figure18showsthatforlowerinjec-
Abstract — Reliability of systems used in space, avionic and biomedical applications is highly critical. Such systems consist of an analog front-end to collect data, an Analog-to-Digital Converter (ADC) to convert the collected data to digital form and a
Fig.17.BlocksensitivityvariationwithinputsfortheSAADC,q=14,r
=32
Fig.20.Maximumrelativeerror(SA),p=3,q=14,r=32
outputlatch
sha
0.1
0.0090.008
0.01
0.0070.006POF
2
0.001
0.0050.004
1e 05
Charge injected (pC)
468
0.0030.002
01
Bit Position
23
Fig.18.
r=32
Blocksensitivities(logscale)variationwithinjections(SA),p=3,
Fig.21.Sensitivityofthefourlatchesinconvertlatch(SA),p=3,q=14,r=32
0.080.070.060.05
-ΣADC
POF
0.040.030.020.0100
TABLEIV
SENSITIVITYANALYSIS,
p=2,q=8,r=16
sampleBit4Bit3Bit2Bit1readout
Injection Time
Fig.19.VariationofPOFwithfaultinjectiontimes(SA),p=3,q=14
tionlevelstheorderingofcriticalblocksmightchange(SHAismoresensitivethantheoutputlatchfrom0pCto0.25pC).This gurealsoshowsthat,asfortheFIADC,beyondacertainin-jectionlevelthereisnofurtherincreaseinthesensitivityoftheblocksintheSAADC.Figure19showsthevariationinsensi-tivitywithfaultsinjectedatdifferenttimeinstancesforasuc-cessiveapproximationADC.TheresultsindicatethattheADCismoresusceptibletoα-particlehitsduringtheearlypartofeachbitconversioncycle.Figure20showsthemaximumrel-ativeerrorduetoeachblock.Ourresultsindicatethataswegettoblocksclosertotheinput,themaximumrelativeerrorin-creases,reachinga
peakforthesampleandholdampli ers(shainFigure20).Anotheranalysisperformedontheconvertlatchrevealedthatoutofthefourlatchesintheconvertlatch,thelatchcontainingthemostsigni cantbitisthemostsensitive(Figure21).Theoutputlatch,convertlatchandshahavebeenthusiden-ti edascriticalblocksthatshouldberedesignedtoimprovethereliabilityofthecircuit.
4) -ΣADC:The -ΣADCliketheSAADCtakessev-eralcyclestogeneratethe nalADCoutput.Thenumberofcyclesrequiredtogeneratethe naloutputisgovernedbytheoversamplingratioofthe -Σconverter.Forthe4-bit -ΣADCimplementedforthiswork,the -Σmodulatorgenerateseightbitsin8clockcycles.Theseeightbitsarethendigitally lteredandthe nal4-bitADCoutputisgeneratedatadeci-matedfrequency.Themiddlebits(bit3to6)amongtheeightbitsgeneratedbythe -Σmodulatorcontributemoretowardsthe nalADCoutputasthelarger ltercoef cientsaremulti-pliedbythesebits.However,thesebitsarenotnecessarilythemostsensitiveones.Therefore,itisofinteresttoanalyzethenumberoferrorsineachoftheeightbitsresultingfrominjec-tionsinthe -Σmodulator.Figure22showsthevariationofthenumberoferrorswithbitsgeneratedinthe rsttotheeighthclockcycles.Itisobservedthatthebitsgeneratedinthelatercyclesaremorepronetofaults.Thiscanbeattributedtothefactthatthebitgeneratedinthenthcycleisdependentontheoffsetstoredintheintegratorinthe(n 1)thcycle.Therefore,thebitgeneratedinthelastcycle(inthiscasethe8thcycle)willbesensitivetofaultsinjectedinallprecedingcyclesinadditiontothoseinjectedinthecurrentcycle.Asensitivityanalysisof
Abstract — Reliability of systems used in space, avionic and biomedical applications is highly critical. Such systems consist of an analog front-end to collect data, an Analog-to-Digital Converter (ADC) to convert the collected data to digital form and a
TABLEV
AreaSENSITIVITIESOFFOURCOMPARATORSWITHVARYINGINPUTSFOR4-BITFLASHADC,p=3,q=8,r=4
6005004003002001000
Number of Errors
TABLEVI
1
2
3
4
5
6
7
8
Bit Number
SENSITIVITIESOFTHE4-BITFLASHADCWITHDIFFERENT
COMPARATORS,p=3,q=8,r=4
Fig.22.Variationinnumberoferrorswithtimeforthe -ΣADC,p=3,q=8,r=16
Itisessentialtogaugetheimprovementthateachofthesetech-niquesoffersasthiswouldhelpthedesignertodecideonaneffectivefaulttolerancedesignstrategy.Thefollowingsectionsdescribeseveralredesigntechniques[21]andalsoillustratetheamountofsensitivityimprovementthatcanbegainedbyem-ployingthem.
A.AlternativeRobustImplementations
MostoftheADCbuildingblockslikethesampleandholdampli erandcomparatorshaveseveralpossibleimplementa-tionswhichtrade-offarea,speedandsusceptibilitytonoiseandparametricvariations.Theseimplementationsinherentlyhavedifferentsensitivitiestoα-particletransients.WhendecidingonanimplementationfortheADCinquestion,thesensitivityoffeasibleimplementationsshouldbecomparedandanappro-priateimplementationshouldbechosen.
1)FlashADC:Oursensitivityanalysisofthe4-bitFlashADChasidenti edtheanalogblockprimarilycomprisingofcomparatorsasthecriticalblock.Fourcomparatorswerethenconsideredforsensitivityevaluationtoidentifythemostrobustimplementation.
Tabatabaei’sComparator[18]isarecentimplementationofasinglestagecomparator.Suchsinglestagecomparatorsprovidethedesiredgaininmostcasesbuttheirdelaymaybetoohigh.Toalleviatetheproblemofhighdelay,comparatorswithmulti-plepreampli cationstageshavebeenproposed.Onesuchmul-tistagecomparatorimplementation(Hester’scomparator[20])incorporatespositivefeedbacktoachievethedesiredgain.An-othercomparator(Yee’scomparator[19])usesinvertersbiasedinthehighgainregionaspreampli ers.Thesimplicityofthismultistagecomparatorhasmadeitquitepopularintheresolu-tionrangefrom8to10bits.TableVshowstheresultsofsen-sitivityanalysisofthefouralternativecomparatorimplemen-tations.Theinitialversionofthe4-bit ashADC(discussedFig.23.DigitalDecimationFilterinthe -ΣADC
the -ΣADCrevealedthatthedigitaldecimation lter(de-pictedinFigure23)isthecriticalblock(seeTableIV).There-sultsshownaboveillustratethedifferentkindsofanalysisthatcanbeperformedtoaidthedesignerinarrivingatamorereli-ableimplementation.ThismethodologycanbeusedtoanalyzethefaultsensitivitiesoftheconstituentblocksinanyADCar-chitectureatanearlystageinthedesigncycle,thusreducingconcept-to-silicontime.
IV.RELIABILITYIMPROVEMENTTECHNIQUESAsensitivityanalysisidenti escriticalblocksthatthede-signercanconcentrateontoimprovethereliabilityofthesys-tem.Faulttoleranceofablockcanbeimprovedinoneoftwoways:
1.Evaluatingthesensitivitiesofalternativeimplementationsofablockandselectingthemostrobustimplementation.2.Affectingdesignchangesintheexistingimplementation
Abstract — Reliability of systems used in space, avionic and biomedical applications is highly critical. Such systems consist of an analog front-end to collect data, an Analog-to-Digital Converter (ADC) to convert the collected data to digital form and a
AreaTABLEVII
SENSITIVITIESOFSHASWITHVARYINGINPUTSFOR4-BITFIADC,p=3,q=10,r
=4
Fig.24.ConventionalSampleandHoldAmpli erFig.26.MillerHoldCapacitor
SHA
POF
Fig.25.ClockFeedthroughCancellationSHA
Resistance (in K)
insubsectionII-A)incorporatedthecomparatorproposedbyTabatabaei[18].Eitheroneoftheabovefourimplementationscanbechosenbasedontherequirementsoftheapplication.WehavefoundthatthecomparatorproposedbyHester[20]andthedifferentialone[8]aretheleastsensitiveamongtheimple-mentationsconsidered.Sensitivitygainsofasmuchas89%wereobserved.Thedifferentialimplementationalsoshowedanimprovementof50%intheMRE.Theimprovementinsen-sitivityisachievedwithapenaltyintermsofarea(seeTableV).However,thelesssensitivecomparatorshavealsoalowerdelay.AlesserareaoverheadisobservedinHester’simplemen-tationwithalmostcomparablesensitivityimprovement.TableVIshowstheeffectonthesensitivityofthewholeADC.Sincethecomparatorsarethecriticalblocksinthe ashADC,asim-ilarsensitivityimprovementisobservedforthewholeADC.2)FoldingandInterpolatingADC:Thesensitivityanalysisofthe4-bitFIADChasidenti edthesampleandholdam-pli er(SHA)asacriticalblock.ThreeimplementationswereconsideredtoidentifythemostrobustSHA.Figure24showstheconventionalimplementation[8]oftheSHA.Thisimple-mentationissusceptibletoclockfeedthroughwhichcausesanextrachargeofQch/2(Qchisthechannelcharge)ontheholdcapacitor(Ch)wheneverCk
turnsthesamplingswitchoff.Animplementation[22]whichalleviatestheproblemofclockfeedthrough(seeFigure25)usesadummyswitch(Q2)with(W/L)Q2=0.5·(W/L)Q1.Thedummyswitchturnsonwhen-Fig.27.Variationinsensitivitywithincreasingresistance(R),p=3,q=8,r=32
everthesamplingswitch(Q1)turnsoffandabsorbsthechannelcharge(Qch/2)releasedbyQ1,leavingtheholdcapacitorun-affected.
Sincetheholdingcapacitorhastoholdthesampledvalueforsometime,itsvalueisusuallylarge.However,alargervalueoftheholdingcapacitoralsoimpliesthattheacquisitiontimeforsamplingtheinputwillincrease.Analternateimplementation(Figure26)[23]changesthecon gurationinthesampleandholdmodessothattheinputseesasmallcapacitanceinthesamplingmodewithoutsacri cingintermsoftheholdtime.Thefollowingexpressionsshowthevaluesoftheacquisition(Cacq)andthehold(Chold)capacitancesinthiscon guration:Cacq=C1+C2,
Chold=(1+A)·
C1C2C1+C2
(10)
whereAisthegainoftheoperationalampli er.
TableVIIshowstheresultsofthesensitivityanalysisoftheabovethreepossibleimplementationsoftheSHA.McCreary’s[22]implementationshowsa19.8%sensitivityimprovementovertheconventional[8]implementation.Inaddition,italsoshowsanimprovementof11%intheMRE.Ithowever,con-sumesmoreareaandincursahigherdelay.AlthoughLim’s[23]implementationshowsahigherimprovementinsensitiv-ity,itconsumesmuchmoreareathanMcCreary’simplemen-
Abstract — Reliability of systems used in space, avionic and biomedical applications is highly critical. Such systems consist of an analog front-end to collect data, an Analog-to-Digital Converter (ADC) to convert the collected data to digital form and a
9876
Delay (ns)
5432100
2
4
6
8
10
12
14
16
(ARE)(ARE)TABLEIX
-ΣADC(NFTVSFT)
SENSITIVITY,
p=2,q=8,r=16
Resistance (in K)
Fig.28.r=32
Variationinperformancewithincreasingresistance(R),p=3,q=8,
(ARE)(ARE)TABLEVIII
DIGITALDECIMATIONFILTERSENSITIVITYOFTHENONFAULTTOLERANT(NFT)ANDTHEFAULTTOLERANT(FT)VERSIONS,p=2,
q=8,r=4
Fig.29. -Σmodulatorwithredundancy
tationandhencemaynotbeaneffectivereplacementfortheconventionalimplementation.
3)SuccessiveApproximationADC:Thesensitivityanaly-sisofthe4-bitSAADChasidenti edtheconvertlatchandtheoutputlatchascriticalblocks.TheTransientPulseToler-antLatch(TPTL)proposedin[24]wasconsideredforreliabil-ityimprovement.TheresistorsintheTPTL lteroutthetran-sientsarrivingattheinputofthelatchthushardeningitagainsttransients.Withincreasingvaluesoftheresistors,thelatchbe-comesmorefaulttolerantbutatthesametimeaperformancepenaltyisincurred[17](Figure27).Theoverheadcanbere-ducedbyreplacingonlythemostsensitivelatchinconvertlatchbyTPTL.
Figure28showsthatthedelayduetohigherresistancein-creasesexponentially.Therefore,the nalresistancevalueshouldbechosenbytakingtheperformancedegradationintoaccount.
4) -ΣADC:Sincethedigitaldecimation lterinthe -ΣADCuseslatchesextensively,usingtheTPTLdescribedintheprevioussubsectioncanlowerthesensitivityofthedecima-tion lter.Wetherefore,replacedalllatcheswithTPTLandobservedimprovementsinsensitivitiesofasmuchas21%(Ta-blesVIIIandIX).Thisimprovementisachievedhowever,atacostofreducedperformance.Figure28showstheperformancedegradationduetointroductionoftheresistance(R).B.AddingRedundancy
Whereastheprevioustechniquetendstowardsfaultre-silience,thistechniqueattemptstomasktheeffectofafault.Oneofthewaysfaulttolerancecanbeachievedthroughre-dundancyisto rstdetectthefaultandthenrecoverfromthefault.Thisinvolvesduplicationoftheblock,anddesignofan
(ARE)OF
(ARE)TABLEX
SENSITIVITY(×10 4)ANDMRE
-ΣMODULATOR,p=3,q=8,r=16
errordetectionschemewhichcanactivatetheredundantblockwhenafaultisdetected.Thistechniquehasbeenimplementedforthemodulatorinthe -ΣADC.The -Σmodulatorisanidealcandidateforapplyingthistechniquebecausethetech-niqueaddressestheintegratorwhichisauto-zeroedonthedec-imatedclock(T3inFigure29).Iftheerrorisnotcorrecteditwilleffectthesubsequentserialbitstreamgeneratedanditwillgenerateerroneousbitstillthenexttimetheintegratorisauto-zeroed.ThoughthistechniquecanbeusedforotherADCs,itwillhavethemaximumimpactonADCslikethe -Σ,partofwhichretainssomeinformationfromthepreviouscycle(liketheintegrator).
Whiletheinputisbeingsampledontothesamplingcapaci-tor,therestofthenodesintheADCaremaintainedatthevalueevaluatedinthepreviouscycle.Thischaracteristiccanbeusedtodetectanerrorandprotectthecircuitfromfaultsinjectedduringthesamplingtime.Sincerecent -ΣADCimplemen-tationsshowthatalmost50%[18]ofthecycletimeisspentinsampling,thisschemewouldaddressasizeablenumberoffaults.Thisfactfurtherforti estheargumentthattheproposedtechniqueisbettersuitedtothe -ΣADCascomparedtootherADCs.Figure29showsthemodi ed rst-order -Σmodula-torwiththeredundancyincorporatedinit.ThecapacitorC1
Abstract — Reliability of systems used in space, avionic and biomedical applications is highly critical. Such systems consist of an analog front-end to collect data, an Analog-to-Digital Converter (ADC) to convert the collected data to digital form and a
(ARE)(ARE)SENSITIVITY,
p=3,q=8,r=4
TABLEXI
FLASHADC(NFTVSFT)
0.16
Fig.30.FaultTolerant4-bitFlashADC
0.140.12
"2pC""4pC""6pC""8pC""10pC"
storesacopyofthevalueintheintegrator.Whentheinputisbeingsampled(T1ishighandT2islow),theintegratoroutput(markedbyXinFigure29)shouldnotchange.Intheeventthatafaultcausesittochange,theerrordetectionblock agsanerrorwhichactivatestheredundantblock(whenT2goeshigh).TableXshowstheresultofthesensitivityanalysisrunontheNon-FaultTolerant(NFT)andtheFaultTolerant(FT)versionsofthe -ΣModulator.Theresultsshowa65.8%im-provementinsensitivityand25%improvementinMREwithapproximately75%areaoverhead.C.PatternDetection
InsomeADCs(e.g.,FlashandFI)thesignallinesattheboundarybetweentheanalogandthedigitalblocksexhibitaspeci cpattern.Iftheexpectedpatternisnotdetected,eithera agcanbeassertedor,ifpossible,acorrectioncanbeat-tempted.Thistechniquehasbeenusedforimprovingthereli-abilityofa4-bit ashADC.Theoutputofthecomparatorsinthe ashADCexhibitathermometercodepattern.Therefore,a0detectedwithinastringof1sorvice-versa,indicatesanerror.Thiserrorcanbecorrectedbyselectingthemajorityvaluefromwithinaneighborhoodofxbitsoneithersideofthebittobecorrected,wherex≥1.Forourimplementation,xwastakenas1.Figure30showsthemodi edblockdiagramofthefaulttolerant4-bit ashADC.TheErrorCorrectionblockcontainsthreetypesoferrorcorrectingsubblocks,twofortheboundarysignals(A15andA0)andonefortherestofthesignals.ThefollowingBooleanexpressionsillustratethelogicusedforthecorrection.
A(11)15=A15·(A13+A14)
0=A0+(A1·A2)A
j=Aj·Aj 1+Aj·Aj+1+Aj+1·Aj 1A
(12)(13)
0.1
POF
0.080.060.040.0201
2
3
4
5
6
Sizing Factor
Fig.31.Sensitivityvariationwithsizingandinjectionlevels,q=14,r=4
D.TransistorSizing
Anα-particleinjectionresultsinacurrentspikeatthefaulty
node.Thiscurrenttranslatestoavoltage uctuationwhosemagnitudedependsonthedrivingstrengthofthetransistor,thecapacitanceatthenodeandtheinjectioncurrent[24].Oneoftheprimaryfactorsin uencingthemagnitudeofthe uctuationistheresistanceposedbythetransistorsconnectedtothatnode.Therefore,onewouldexpectanimprovementinthereliabilitybysizingupthetransistorandthusreducingtheresistance.Ontheotherhand,sizingupatransistoralsoincreasesitsfault-sensitivearea.Thebene tsoftransistorsizingwereanalyzedforbothdigitalandanalogcircuitsin[17]andarefurtherdis-cussedinthefollowingsubsections.
1)DigitalCircuits:Thistechniquewasimplementedina2-bitcounter(with73circuitnodes)usedinthedigitaldecima-tion lterinthe -ΣADC,andthevariationofthesensitivitywithsizingandbyboundingthemaximuminjectionlevelwasanalyzed.Figure31showsthatthesensitivityincreasesandthendecreaseswithsizingforboundedinjections.Forinjectionlevelsboundedby1pCanimprovementinreliabilityof33%isobservedwhensizingthecircuitbytwiceitsoriginalsize.Fur-thermore,themaximumvalueofthePOFforahigherinjectionboundoccursatahighersizingratio(1for1pCand2for4pCinFigure31).Fortheabovesimulationsthewholecircuitwassized.Thebene tsofselectivenodesizingonthesensitivityofthe2-bitcounterwerealsostudiedandarediscussednext.Thenodeswhichwillresultinmaximumsensitivitygainsshouldbechosenascandidatesforsizing.Oneoftheschemesthatcanbefollowedsortsthenodesindecreasingorderoftheircontri-butiontotheoverallsensitivityoftheblock.Outofthissortedlistthe rstnnodescanbeselectedascandidatesforresizing.Figure32showsthatforlowerinjectionlevelbounds(1pC)sensitivityimprovementofasmuchas60%isobservedwithanTableXIshowstheresultsofthesensitivityanalysisonthe ashADC.Itwasobservedearlier(SubsectionIII-C.1)thattheanalogportionoftheADCwhichisprimarilycomprisedofcomparatorswasmoresensitive(TableIII)thanthedigitalpart.Sincethistechniqueaddressestheerrorsduetofaultsin-jectedintheanalogblock,itwillprovideconsiderableoverallsensitivityimprovement.Animprovementofaround67.8%insensitivityatthecostof55%areaoverheadwasobserved.
Abstract — Reliability of systems used in space, avionic and biomedical applications is highly critical. Such systems consist of an analog front-end to collect data, an Analog-to-Digital Converter (ADC) to convert the collected data to digital form and a
0.025
"All 73 nodes"
"4 nodes""8 nodes""12 nodes"
0.025
"All 73 nodes"
"4b""8b"0.02
0.02
1.008
0.015
1.02
0.015
POF
0.01
POF
4.00
1.21.381.51
0.01
0.005
0.005
4.00
1.51
1
2
3
4
5
6
12350
Sizing FactorSizing Factor
Fig.32.Sensitivityvariationwithselectivenoderesizingwithinjectionlevelboundedby1pC(thenumberonthecurvesindicatethecorrespondingfault-sensitiveareaincreasefactor)q=14,r=4
0.0450.040.0350.03
Fig.35.Sensitivityvariationwithselectivenoderesizing(injectionlevelboundedby1pC)q=14,r=4
0.045
"All 73 nodes"
"4 nodes""8 nodes""12 nodes"
0.040.0350.03
1.05All 73 nodes
4b nodes8b nodes12 nodes
1.641.86
POF
0.0250.020.015
POF
0.0250.020.0150.01
0.010.005
6.00
1
2
3
4
5
0.005
01
2
3
4
5
6
Sizing Factor
Sizing Factor
Fig.33.Sensitivityvariationwithselectivenoderesizing(injectionlevelboundedby2pC)q=14,r=4
0.070.060.05
Fig.36.Sensitivityvariationwithselectivenoderesizing(injectionlevelboundedby2pC)q=14,r=4
0.07
"4b nodes""8b nodes""12 nodes"
"All 73 nodes"
"4 nodes""8 nodes""12 nodes"
0.060.050.040.030.02
POF
0.040.030.020.010
6.00
POF
0.010
123456
12
Sizing Factor
3456
Sizing Factor
Fig.34.Sensitivityvariationwithselectivenoderesizing(injectionlevelboundedby4pC)q=14,r=4
Fig.37.Sensitivityvariationwithselectivenoderesizing(injectionlevelboundedby4pC)q=14,r=4
areaoverheadofonly20%.Thenumbersonthecurvesindi-catetheareaincreasefactorforthesizingfactorwhichresultsinthelowestsensitivity.Theabovenodeselectionschemeworkswellforinjectionlevelsboundedby1pC.However,theimprovementisnotsosizeableforhigherinjectionlevelbounds(seeFigures33and34).Thismotivatesasearchforabetternodeselectionschemeandaninsightintowhytheimprove-mentislimitedforhigherinjectionlevels.Theerroroffsetatanodecausedbyaninjectionisdependentamongotherfac-torsontheinjectionlevelandthetransistordrivingstrength.Denoteby Vtheerroneousvoltageoffset,whichisequalto V=IinjRon,whereIinjisthemagnitudeoftheinjectedcurrentandRonistheresistanceposedbythetransistorcon-nectedtothenode. VcanbereducedbyloweringRon,which
canbeachievedbysizingupthetransistor.ButifRonislargethenthetransistorwillhavetobeconsiderablysizedbeforeanygaininsensitivitycanbeachieved.Itisverylikelythatthiskindofnodeswillshowupatthetopofthesortedlistofnodes.Thus,insuchcasesitispossibletoachievehighersensitivitygainswithasmallerareaoverheadbyoptingforanalternatescheme.Inthisschemeonlythemnodesatthebottomofthesortedlistofthenmostsensitivenodesaresized.Notethatsincethemnodesareselectedfromalistofthenmostsensi-tivenodestheyarestillquitesensitive.Figures35,36and37showthatforhigherinjectionbounds,asizeableimprovementinsensitivitycanbeattainedbyoptingforthealternatescheme(seeFigure37,the4band8bcurvesshowthesensitivityvaria-tionwhenmis4and8,respectively,forn=12).Insummary,forlowerinjectionlevels(≤1pC)resizingthenmostsensi-
Abstract — Reliability of systems used in space, avionic and biomedical applications is highly critical. Such systems consist of an analog front-end to collect data, an Analog-to-Digital Converter (ADC) to convert the collected data to digital form and a
0.070.060.050.040.030.020.010
"1pc""2pc""4pc""6pc""8pc"
V.CONCLUSIONS
AgenericmethodologyforthereliabilityenhancementofADCshasbeenpresented.Faultsensitivityanalysisfollowedbycircuitredesignwasidenti edasthefaulttolerancestrategytobeapplied.Theuseofnodeweights,speci ctoα-particletransients,wasproposedtoincreasetheaccuracyofthesensi-tivityanalysis.Twometrics,namelythePOFandAREwhichcharacterizethesensitivityofablock,werepresented.Thefol-lowingstepshavebeenidenti edforα-particleinducedfaultsensitivityanalysis:
(i)Calculateweightsofthenodes.
(ii)Performtransientfaultsimulationsonallnodes.
(iii)Useequation(6)or(8)tocalculatethesensitivityofthe
constituentblocks.
Thismethodologywasusedto rstidentifycriticalblocksintheFI,SA, ashand -ΣADCsandthenincreasetheirrelia-bilitybycircuitredesign.Severalredesigntechniqueswerepre-sentedincludingtheselectionofmorerobustimplementations,addingredundancy,patterndetectionandtransistorsizing,us-ingwhich,sensitivitygainsofasmuchas89%,65.8%,67.8%and60%,respectively,wereobserved.EachoftheproposedcircuitredesigntechniquescanbeusedforotherADCs.Forexample,theSHAandcomparatoraresomeofthemostubiq-uitousblocksinADCsandnumerouscircuitimplementationshavebeenproposed.Thus,severalalternativerobustimplemen-tationsofthesecanbeevaluatedformostADCs.Theproposedredundancytechniquewillbeusefulincircuitswherethenodevoltageshavetobeheldtoaconstantvalueforasubstantialamountoftime(likeinthe -Σmodulator).PatterndetectioncanbeusedinADCswherethesignallinesattheboundarybetweentheanaloganddigitalblocksarelimitedtocertainpat-terns(likethe ashandFIADCs).Lastly,transistorsizingwasfoundtobebene cialforbothdigitalandanalogcircuitsundercertaincircumstances.
VI.FUTUREWORK
ADCarchitectureslikethepipelined,multi-stepandintegrat-ingADCscanbesimilarlyanalyzedfortheirsensitivitiestoα-particletransients.Itisalsonecessarytostudytheimpactofparametricvariationsinmixed-signalcircuitsonthesensitiv-itytoα-particletransients.Currently,thisworkassumesthatthecircuitundertestisproperlycenteredintheprocessenve-lope.Initialsimulationsbyvaryingthewidthandthethresh-oldvoltageofthetransistorsinacomparatorhaveshownthatsometimesan“uncentered”designcanhavealowerratherthanhighersensitivitytoα-particletransients.Inmostofthecaseshowever,thevariationwassmallforthetypeofparametricvari-ationsconsidered.Allinall,thereisaneedtostudythesen-sitivityofsocalled“uncentered”designstoα-particleinducedtransients.Finally,thisworkcanbeextendedforothertypesoftransientfaultsbydevelopingappropriatemodelsforthecandi-datefaults.
REFERENCES
[1]H.BallandF.Hardy,“Effectsanddetectionofintermittentfailuresin
digitalsystems,”inProc.ofFJCC,AFIPSConf.,Vol.351969,pp.329–335.
Average Relative Error
12
Sizing Factor
3456
Fig.38.AnalogBlockAREvariationwithsizingandinjectionlevels,p=3,q=14,r=4
0.160.140.120.1
"1pc""2pc""4pc""6pc""8pc"
POF
0.080.060.040.02
12
Sizing Factor
3456
Fig.39.AnalogBlockPOFvariationwithsizingandinjectionlevels,p=3,q=14,r=4
tivenodesprovedbene cialwhileforhigherinjectionlevels(≥2pC)resizingtheleastsensitivemnodesinthesortedlistofnprovedbene cial.Theselectivenodeselectionstrategyprovidessensitivitygainswithminimumareaoverheadamongthetwostrategiesconsidered.Thisisanexampleofastrategyforeffectivenodeselectionforreliabilityenhancement.
2)AnalogCircuits:Thistechniquewasimplementedforthecomparatorswhichwereidenti edasthecriticalblocksinthe4-bitFlashADC.Figure38showsthatanimprovementofaround50%inAREcanbeachievedbysizingforinjectionlev-elsboundedby1pC.However,theAREincreaseswithsizingforinjectionlevelsabove4pC.AninterestingpointtonotehereisthatthePOFmetric(seeFigure39)indicatesthatthesensitivitydoesnotchangebymuchforasizingfactorof2foraninjectionboundedby1pC.Thisimpliesthatthenum-berofinjectedfaultstranslatingtoerrorsstillremainsaboutthesamebutthemagnitudeoferrorduetoeachofthosefaultshasreduced,thusresultinginanoverallreductionof50%intheARE(seeFigure38).Furtherreductioninsensitivityforahighersizingratioissmallerbecauseincreasingthewidthofthetransistorinananalogcircuitentailsincreasingitslengthalso,sincetheW/Lratiosmustbemaintained.Thisimpliesthattheresistanceposedbythetransistorwillnotchange,butthecapacitanceseenbythenodewillincrease,thuscausingareductioninthesensitivityinsomecasesasshowninFigure38.
Therefore,sensitivitygainscanbeattainedforlowerinjec-tionlevels(≤2pC)butastheinjectionlevelboundincreasesthistechniquedoesnotprovebene cial.
Abstract — Reliability of systems used in space, avionic and biomedical applications is highly critical. Such systems consist of an analog front-end to collect data, an Analog-to-Digital Converter (ADC) to convert the collected data to digital form and a
[2]R.IyerandD.Rosetti,“AstatisticalloaddependencyofCPUerrorsat
SLAC,”inProc.FTCS-12,1982,pp.363–372.
[3]F.L.YangandR.A.Saleh,“SimulationandAnalysisofTransientFaults
inDigitalCircuits,”IEEEJournalofSolid-StateCircuits,vol.27,pp.258–264,1992.
[4]S.KangandD.Chu,“CMOScircuitdesignforthepreventionofsin-gleeventupset,”inProceedingsofIEEEInternationalConferenceonComputerDesign,Oct1986,pp.385–388.
[5]A.Antola,R.Negrini,M.SamiandN.Scarabottolo,“Tolerancetotran-sientfaultsinmicroprogrammedcontrolunits,”IEEETransactionsonReliability,vol.27,pp.258–264,1992.
[6]J.F.Ziegler,“TerrestrialCosmicRays,”IBMJournalofResearchand
Development,vol.40,pp.19–40,1996.
[7]J.F.Ziegleret.al.,“IBMExperimentsinSoftFailsinComputerElec-tronics,”IBMJournalofResearchandDevelopment,vol.40,pp.3–17,1996.
[8]B.Razavi,Principlesofdataconversionsystemdesign,IEEEpress,
1995.
[9]R.E.J.VanDeGrift,I.W.J.M.RuttenandM.VanDerVeen,“An8-bitvideoADCincorporatingfoldingandinterpolatingtechniques,”IEEEJournalofSolid-StateCircuits,pp.944–953,1987.
[10]Z.Zhou,B.PainandE.R.Fossum,“CMOSactivepixelsensorwithon-chipsuccessiveapproximationanalog-to-digitalconverter,”IEEETrans-actionsonElectronDevices,vol.44,pp.1759–1763,1997.
[11]H.Amer,M.CortesandE.McCluskey,“Robustdynamicrecoverymech-anisms,”inProceedingsofIEEEInternationalConferenceonComputerDesign,Oct1987,pp.310–313.
[12]Avant!Corporation,Star-Hspicemanual,Dec1999.
[13]G.C.Messenger,“Collectionofchargeonjunctionnodesfromion
tracks,”IEEETransactionsonNuclearScience,pp.2024–2031,1982.[14]gunaandR.Treece,“VLSImodelinganddesignforradiationen-vironments,”inProceedingsofIEEEInternationalConferenceonCom-puterDesign,Oct1986,pp.380–384.
[15]H.Cha,E.M.Rudnick,J.H.Patel,R.K.IyerandG.S.Choi,“Agate
levelsimulationenvironmentforalpha-particle-inducedtransientfaults,”IEEETransactionsonComputers,vol.45,pp.1248–1256,1996.
[16]M.Singh,R.RachalaandI.Koren,“TransientFaultSensitivityAnalysis
ofAnalog-to-DigitalConverters(ADCs),”inIEEEAnnualWorkshoponVLSI(WVLSI),Apr.2001,pp.140–145.
[17]M.SinghandI.Koren,“IncorporatingFaultToleranceinAnalog-to-DigitalConverters(ADCs),”inIEEEInternationalSymposiumonQual-ityElectronicDesign(ISQED),Mar.2002,pp.286–291.
[18]A.TabatabaeiandB.A.Wooley,“ATwo-PathBandpassSigma-Delta
ModulatorwithExtendedNoiseShaping,”IEEEJournalofSolid-StateCircuits,vol.35,pp.1799–1809,2000.
[19]Y.S.Yee,L.M.TermanandL.G.Heller,“A1mVMOSComparator,”
IEEEJournalofSolid-StateCircuits,vol.13,pp.294–297,1978.
[20]R.K.Hesteretal.,“FullyDifferentialADCwithRail-to-RailCommon
ModeRangeandNonlinearCapacitorCompensation,”IEEEJournalofSolid-StateCircuits,vol.25,pp.173–183,1990.
[21]M.SinghandI.Koren,“ReliabilityEnhancementofAnalog-to-Digital
Converters(ADCs),”inIEEEInternationalSymposiumonDefectandFaultToleranceinVLSISystems(DFT),Oct.2001,pp.347–353.
[22]J.McCrearyandP.R.Gray,“All-MOSChargeRedistributionAnalog-to-DigitalConversiontechniques-PartI,”IEEEJournalofSolidStateCircuits,pp.371–379,1975.
[23]P.LimandB.Wooley,“AHighSpeedSample-and-HoldTechniqueUs-ingaMillerHoldingCapacitor,”IEEEJournalofSolidStateCircuits,vol.26,pp.643–651,1991.
[24]H.ChaandJ.H.Patel,“ALogic-LevelModelforα-ParticleHitsin
CMOSCircuits,”inProceedingsofIEEEInternationalConferenceonComputerDesign,Oct1993,pp.538–542.MandeepSingh(M’01)receivedtheB.E(Hons.)de-greeinelectricalengineeringfromtheBirlaInsti-tuteofTechnologyandSciences,Rajasthan,Indiain1997andtheM.S.degreeinelectricalandcomputerengineeringfromtheUniversityofMassachusetts,PLACE
Amherst,in2001.WhileattheUniversityofMas-PHOTO
sachusetts,hecompletedhisthesisontheReliabilityHERE
EnhancementofAnalog-to-DigitalConverters.HeworkedforWiproGlobalResearchandDevelop-ment,Bangalore,Indiafrom1997to1999,wherehewasinvolvedinthedesignanddevelopmentofhigh
speedcommunicationASICs.HeiscurrentlyworkingforAdvancedMicroDe-vicesintheComputationProductsGroup,Austin,TX,whereheisinvolvedinhighperformancemicroprocessordesign.
IsraelKoren(S’72-M’76-SM’87-F’91)receivedtheB.Sc.,M.Sc.andD.Sc.degreesfromtheTech-nion-IsraelInstituteofTechnology,Haifa,in1967,1970,and1975,respectively,allinElectricalEn-gineering.HeiscurrentlyaProfessorofElectri-PLACE
calandComputerEngineeringattheUniversityofPHOTO
Massachusetts,Amherst.PreviouslyhewaswiththeHERE
Technion-IsraelInstituteofTechnology.HealsoheldvisitingpositionswiththeUniversityofCali-forniaatBerkeley,UniversityofSouthernCalifornia,LosAngelesandUniversityofCalifornia,SantaBar-bara.HehasbeenaconsultanttoseveralcompaniesincludingIBM,Intel,AnalogDevices,AMD,DigitalEquipmentCorp.,NationalSemiconductorandTolerantSystems.
Dr.Koren’scurrentresearchinterestsincludeTechniquesforYieldandReliabilityEnhancement,Fault-TolerantArchitectures,Real-timesystemsandComputerArithmetic.HepublishedextensivelyinseveralIEEETransactionsandhasover150publicationsinrefereedjournalsandconferences.Hecur-rentlyservesontheEditorialBoardoftheIEEETransactionsonVLSISystems.HewasaCo-GuestEditorfortheIEEETransactionsonComputers,specialis-sueonHighYieldVLSISystems,April1989andthespecialissueonComputerArithmetic,July2000,andservedontheEditorialBoardoftheseTransactionsbetween1992and1997.HealsoservedasGeneralChair,ProgramChairandProgramCommitteememberfornumerousconferences.Hehaseditedandco-authoredthebook,DefectandFault-ToleranceinVLSISystems,Vol.1,Plenum,1989.HeistheauthorofthetextbookComputerArithmeticAlgo-rithms,2ndEdition,A.K.Peters,Ltd.,2002.
- 1ECONOMIC RELIABILITY FORECASTING IN AN UNCERTAIN WORLD
- 2A TWO-STAGE ALGORITHM FOR ENHANCEMENT OF REVERBERANT SPEECH
- 3Enhancement of the anomalous Hall effect and spin glass beha
- 4Further investigation on the dynamic compressive strength enhancement
- 5FLEX IO Digital InputOutput Modules
- 6The Digital Game-Based Learning
- 7FLEX IO Digital InputOutput Modules
- 8fault 管脚——如何防止功放POP声
- 9basic CMOS analog ic design Lecture 1 background
- 10NonClinical Dose Formulation Analysis Method Validation and Sample Analysis
- 2012诗歌鉴赏讲座 师大附中张海波
- 2012-2013学年江苏省苏州市五市三区高三(上)期中数学模拟试卷(一)
- 市政基础设施工程竣工验收资料
- 小方坯连铸机专用超越离合器(引锭杆存放用)
- 荀子的学术性质之我见
- 氩弧焊管轧纹生产线操作说明
- 小学科学六年级上册教案
- (商务)英语专业大全
- 外汇储备的快速增长对我国经济发展的影响
- 幼儿园中班优秀语言教案《小猴的出租车》
- 第七章 仪表与显示系统
- 身份证号码前6位行政区划与籍贯对应表
- 单位(子单位)工程验收通知书
- 浅谈地铁工程施工的项目成本管理
- 沉积学知识点整理
- 前期物业管理中物业服务企业的法律地位
- 2014微量养分营养试卷
- 地质专业校内实习报告范文(通用版)
- 内部审计视角下我国高校教育经费支出绩效审计研究
- 高次插值龙格现象并作图数值分析实验1
- Sensitivity
- Reliability
- Enhancement
- Converters
- Analysis
- Digital
- Analog
- Fault