5962R9689104VYC中文资料

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Standard Products

Data Sheet

December 2002

UT28F256 Radiation-Hardened 32K x 8 PROM

FEATURES

qProgrammable, read-only, asynchronous, radiation-hardened, 32K x 8 memory

-Supported by industry standard programmerq45ns and 40ns maximum address access time (-55 oC to +125 oC)

qTTL compatible input and TTL/CMOS compatible output levelsqThree-state data bus

qLow operating and standby current

-Operating: 125mA maximum @25MHz Derating: 3mA/MHz

-Standby: 2mA maximum (post-rad)qRadiation-hardened process and design; total dose irradiation testing to MIL-STD-883, Method 1019-Total dose: 1E6 rad(Si)

- LETTH(0.25) ~ 100 MeV-cm2/mg

-Memory cell LET threshold: >128 MeV-cm2/mg

qQML Q & V compliant part-AC and DC testing at factory

qPackaging options:

-28-lead 50-mil center flatpack (0.490 x 0.74)

-28-lead 100-mil center DIP (0.600 x 1.4) - contact factoryqVDD: 5.0 volts 10%

q Standard Microcircuit Drawing 5962-96891

PRODUCT DESCRIPTION

The UT28F256 amorphous silicon anti-fuse PROM is a high performance, asynchronous, radiation-hardened,

32K x 8 programmable memory device. The UT28F256 PROM features fully asychronous operation requiring no external clocks or timing strobes. An advanced radiation-hardened twin-well CMOS process technology is used to implement the UT28F256. The combination of radiation-hardness, fast access time, and low power consumption make the UT28F256 ideal for high speed systems designed for operation in radiation environments.

- 2/mg

- Saturated Cross Section cm2 per bit, 1.0E-11

- 1.2E-8 errors/device-day, Adams 90% geosynchronous

heavy ion

A(14:0)DECODER

MEMORYARRAY

SENSE AMPLIFIER

CEPEOE

PROGRAMMING

CONTROLLOGIC

DQ(7:0)

Figure 1. PROM Block Diagram

DEVICE OPERATION

The UT28F256 has three control inputs: Chip Enable (CE), Program Enable (PE), and Output Enable (OE); fifteen address inputs, A(14:0); and eight bidirectional data lines, DQ(7:0). CE is the device enable input that controls chip selection, active, and standby modes. Asserting CE causes IDD to rise to its active value and decodes the fifteen address inputs to select one of 32,768 words in the memory. PE controls program and read operations. During a read cycle, OE must be asserted to enable the outputs.PIN CONFIGURATION

PIN NAMES

A(14:0)CEOEPEDQ(7:0)

AddressChip EnableOutput EnableProgram EnableData Input/Data Output

Table 1. Device Operation Truth Table 1

A14A12A7A6A5A4A3A2A1A0DQ0DQ1DQ2VSS

1234567891011121314

2827262524232221201918171615

VDDPEA13A8A9A11OEA10CEDQ7DQ6DQ5DQ4DQ3

Notes:

1. “X” is defined as a “don’t care” condition. 2. Device active; outputs disabled.

OEX011

PE1101

CE1000

I/O MODEThree-stateData OutData InThree-state

MODEStandbyReadProgramRead 2

ABSOLUTE MAXIMUM RATINGS 1(Referenced to VSS)

SYMBOLVDDVI/OTSTGPDTJΘJCII

PARAMETER

DC supply voltageVoltage on any pinStorage temperatureMaximum power dissipationMaximum junction temperatureThermal resistance, junction-to-case 2DC input current

LIMITS-0.3 to 7.0-0.5 to (VDD + 0.5)-65 to +150

1.5+1753.3

UNITSVV°CW°C°C/WmA

±10

Notes:

1.Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.2.Test per MIL-STD-883, Method 1012, infinite heat sink.

RECOMMENDED OPERATING CONDITIONS

SYMBOLVDDTCVIN

PARAMETER

Positive supply voltageCase temperature rangeDC input voltage

LIMITS4.5 to 5.5-55 to +1250 to VDD

UNITSV°CV

DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*(VDD = 5.0V ±10%; -55°C < TC < +125°C)SYMBOLVIHVILVOL1VOL2VOH1VOH2CIN 1CIO 1, 4IINIOZ

PARAMETERHigh-level input voltageLow-level input voltageLow-level output voltageLow-level output voltageHigh-level output voltageHigh-level output voltageInput capacitance

(TTL)(TTL)

IOL = 4.0mA, VDD = 4.5V (TTL)IOL = 200µA, VDD = 4.5V (CMOS)IOH = -200µA, VDD = 4.5V (CMOS)IOH = -2.0mA, VDD = 4.5V (TTL) = 1MHz, VDD = 5.0VVIN = 0V

= 1MHz, VDD = 5.0VVOUT = 0V

Input leakage currentThree-state output leakage current

Short-circuit output current Supply current operating @25.0MHz (40ns product)@22.2MHz (45ns product)Supply current standby

VIN = 0V to VDDVO = 0V to VDD V = 5.5VOE = 5.5V

VDD = 5.5V, VO = VDDVDD = 5.5V, VO = 0V

TTL inputs levels (IOUT = 0), VIL = 0.2V

VDD, PE = 5.5V

CMOS input levels VIL = VSS +0.25VCE = VDD - 0.25 VIH = VDD - 0.25V

-5-10

510

µAµA

VDD -0.12.4

15

CONDITION

MINIMUM

2.4

0.80.4VSS + 0.10MAXIMUM

UNITVVVVVVpF

Bidirectional I/O capacitance 15pF

IOS 2,3IDD1(OP)5

90

-90mAmA

1251172

mAmAmA

IDD2(SB)post-rad

Notes:

* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1E6 rad(Si).

1. Measured only for initial qualification, and after process or design changes that could affect input/output capacitance.2. Supplied as a design limit but not guaranteed or tested.

3. Not more than one output may be shorted at a time for maximum duration of one second.4. Functional test.

5. Derates at 3.0mA/MHz.

3

READ CYCLE

A combination of PE greater than VIH(min), and CE less than VIL(max) defines a read cycle. Read access time is measured from the latter of device enable, output enable, or valid address to valid data output.

An address access read is initiated by a change in address inputs while the chip is enabled with OE asserted and PE deasserted. Valid data appears on data output, DQ(7:0), after the specified tAVQV is satisfied. Outputs remain active throughout the entire cycle. As long as device enable and output enable are active, the address inputs may change at a rate equal to the minimum read cycle time.

AC CHARACTERISTICS READ CYCLE (Post-Radiation)*(VDD = 5.0V ±10%; -55°C < TC < +125°C)

SYMBOLtAVAV1tAVQVtAXQX2tGLQX2tGLQVtGHQZtELQX2 tELQV tEHQZ

PARAMETERRead cycle timeRead access timeOutput hold time

OE-controlled output enable time OE-controlled access timeOE-controlled output three-state timeCE-controlled output enable timeCE-controlled access time CE-controlled output three-state time

The chip enable-controlled access is initiated by CE going active while OE remains asserted, PE remains deasserted, and the addresses remain stable for the entire cycle. After the specified tELQV is satisfied, the eight-bit word addressed by A(14:0) appears at the data outputs DQ(7:0).

Output enable-controlled access is initiated by OE going active while CE is asserted, PE is deasserted, and the addresses are stable. Read access time is tGLQV unless tAVQV or tELQV have not been satisfied.

28F256-45 MIN MAX45

45

00

1515

4515

28F256-40 MIN MAX40

40

00

1515

4015

UNITnsnsnsnsnsnsnsnsns

Notes:

* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1E6 rads(Si).1. Functional test.

2. Three-state is defined as a 400mV change from steady-state output voltage.

A(14:0)CE

OE

Figure 2. PROM Read Cycle

RADIATION HARDNESS

The UT28F256 PROM incorporates special design and layout features which allow operation in high-level radiation

environments. UTMC has developed special low-temperature processing techniques designed to enhance the total-dose

radiation hardness of both the gate oxide and the field oxide while RADIATION HARDNESS DESIGN SPECIFICATIONS 1Total Dose

Latchup LET Threshold Memory Cell LET ThresholdTransient Upset LET Threshold

Transient Upset Device Cross Section @ LET=128 MeV-cm2/mg

maintaining the circuit density and reliability. For transient radiation hardness and latchup immunity, UTMC builds all radiation-hardened products on epitaxial wafers using an advanced twin-tub CMOS process. In addition, UTMC pays special attention to power and ground distribution during the design phase, minimizing dose-rate upset caused by rail collapse.

1E6>128>128541E-6

rad(Si)MeV-cm2/mgMeV-cm2/mgMeV-cm2/mg

cm2

Note:

1.The PROM will not latchup during radiation exposure under recommended operating conditions.

5

330 ohms

VREF=1.73V

TTL3.0V50pF

0V

< 5ns

Input Pulses

Notes:

1. 50pF including scope probe and test socket.

2. Measurement of data output occurs at the low to high or high to low transition mid-point (TTL input = 1.5V).

Figure 3. AC Test Loads and Input Waveforms

10%

< 5ns

k0.0150.008

PIN NO. 1 ID. k0.0150.008

26 PLACES0.050 BSCe

-A--B-

D

S1

(4) PLACES0.022

0.01528 PLACES

0.010

H

A-B

D

E1

0.550 MAX

0.036HA-BDTOP VIEW

E0.460

-D-A0.1150.045

Q0.0450.026

L

0.370 0.250

c

0.0090.004

0.040-H-

E2

0.180 MIN

E3

0.030 MIN

Notes:

1. All exposed metalized areas to be plated per MIL-PRF-38535.2. The lid is connected to VSS.

3.Lead finishes are in accordance with MIL-PRF-38535.Dimension letters refer to MIL-STD-1835.

END VIEW

Figure 5. 28-Lead 50-mil Center Flatpack (0.490 x 0.74)

ORDERING INFORMATION

256K PROM: SMD

5962 * 96891 * * * *

Lead Finish:(A)= Solder (C)=Gold(X)=Optional

Case Outline:

(Y)=28-pin DIP (contact factory) (X)=28-lead Flatpack

Class Designator:(Q)=Class Q(V)=Class V

Device Type

(03)= 45ns Access Time, TTL inputs, CMOS/TTL compatible outputs(04)= 40ns Access Time, TTL inputs, CMOS/TTL compatible outputs

Drawing Number: 96891Total Dose:

(F)=3E5 rads(Si)(G)=5E5 rads(Si) (H)=1E6 rads(Si)(R)=1E5 rads(Si)

Federal Stock Class Designator: No options

Notes:

1. Lead finish (A, C, or X) must be specified.

2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).3. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening.4. Check factory for availability of 45ns part.

5. Lead finish: Factory programming either solder or gold. Field programming gold only.

256K PROM

Total Dose:

( )=Total dose characteristics neither tested nor guaranteed

Lead Finish: (A)=Solder (C) = Gold(X)=OptionalScreening:

(C)=Mil Temp(P)=Prototype

Package Type:

(P)=28-lead DIP (contact factory)(U)=28-lead Flatpack

Access Time:

(40) = 40ns access time, TTL compatible inputs, CMOS/TTL compatible outputs(45) = 45ns access time, TTL compatible inputs, CMOS/TTL compatible outputs

Device Type Modifier:

(T)= TTL compatible inputs and CMOS/TTL compatible outputsDevice Type:

(28F256) = 32Kx8 One Time Programmable PROM

Notes:

1.Lead finish (A,C, or X) must be specified.

2.If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold).

3.Military Temperature Range flow per UTMC Manufacturing Flows Document. Radiation characteristics are neither tested nor guaranteed and may not be specified.

4.Prototype flow per UTMC Manufacturing Flows Document. Devices have prototype assembly and are tested at 25°C only. Radiation characteristics are neither tested nor guaranteed and may not be specified.5.Check factory for availability of 45ns part.

6.Lead finish: Factory programming either solder or gold. Field programming gold only.

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