实验二 4位十进制计数器的设计

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实验二 4位十进制计数器的设计

一、实验目的：

1、深入理解信号和变量的区别；

2、深入理解并行语句和顺序语句的区别； 3、深入理解异步和同步的概念； 4、掌握计数器的设计方法；

5、能会看最大系统运行频率和资源使用报告。二、实验原理：

四位十进制计数器程序A： library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;

entity bcd_counter is

end entity;

architecture bev of bcd_counter is begin 0);

process (clk)

variable cnt

: std_logic_vector(3 downto

port ( );

clk : in std_logic; reset : in std_logic; co : out std_logic; q

: out std_logic_vector(3 downto 0)

end bev;

begin

if (rising_edge(clk)) then

if reset = '1' then

cnt := \

else

if cnt < 9 then

cnt := cnt + \ else

cnt := \

co <= '1';

end if;

end if; q <= cnt;

end process;

四位十进制计数器程序B： library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;

entity bcd_counter2 is

port ( );

clk : in std_logic; reset : in std_logic; co : out std_logic; q

: out std_logic_vector(3 downto 0)

end entity;

architecture bev of bcd_counter2 is signal cnt begin

end bev;

四位十进制计数器程序C： library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;

entity bcd_counter3 is

process (clk) begin

if (rising_edge(clk)) then

if reset = '1' then

cnt <= \

: std_logic_vector(3 downto 0);

else

if cnt < 9 then

cnt <= cnt + \ else

cnt <= \

co <= '1';

end if;

end process; q <= cnt;

port ( );

clk : in std_logic; reset : in std_logic; co : out std_logic; q

: out std_logic_vector(3 downto 0)

end entity;

architecture bev of bcd_counter3 is signal cnt begin

end bev; 三、实验内容：

process (clk) begin

if reset = '1'then cnt <= \

elsif (rising_edge(clk)) then

if cnt < 9 then

: std_logic_vector(3 downto 0);

cnt <= cnt + \ else

cnt <= \

co <= '1';

end if;

end process; q <= cnt;

1、资源使用情况和最大运行频率：程序 A B C 使用逻辑单元数 7 7 4 使用寄存器数 4 4 4 最大运行频率（MHz）（slow 1200mV 85C Model） 452.49 452.49 710.73 2、RTL 视图和Technology Map视图

程序A

程序B

程序C

3、testbench文件

程序A

LIBRARY altera ; LIBRARY cycloneiii ; LIBRARY ieee ;

USE altera.altera_primitives_components.all ; USE cycloneiii.cycloneiii_components.all ; USE ieee.std_logic_1164.all ;

ENTITY bcd_counter_tb IS END ;

ARCHITECTURE bcd_counter_tb_arch OF bcd_counter_tb IS SIGNAL q : std_logic_vector (3 downto 0) ; SIGNAL clk : STD_LOGIC := '0' ; SIGNAL co : STD_LOGIC ;

SIGNAL reset : STD_LOGIC := '0' ; COMPONENT bcd_counter PORT (

q : out std_logic_vector (3 downto 0) ; clk : in STD_LOGIC ; co : out STD_LOGIC ; reset : in STD_LOGIC ); END COMPONENT ; BEGIN

DUT : bcd_counter PORT MAP ( q => q , clk => clk , co => co ,

reset => reset ) ; reset <= '1' after 380ns, '0' after 550ns; clk <= not clk after 100ns; END ;

程序B

LIBRARY altera ; LIBRARY cycloneiii ;

LIBRARY ieee ;

USE altera.altera_primitives_components.all ; USE cycloneiii.cycloneiii_components.all ; USE ieee.std_logic_1164.all ; ENTITY bcd_counter2_tb IS END ;

ARCHITECTURE bcd_counter2_tb_arch OF bcd_counter2_tb IS SIGNAL q : std_logic_vector (3 downto 0) ; SIGNAL clk : STD_LOGIC :='0'; SIGNAL co : STD_LOGIC ;

SIGNAL reset : STD_LOGIC :='0' ; COMPONENT bcd_counter2 PORT (

q : out std_logic_vector (3 downto 0) ; clk : in STD_LOGIC ; co : out STD_LOGIC ; reset : in STD_LOGIC ); END COMPONENT ; BEGIN

DUT : bcd_counter2 PORT MAP ( q => q , clk => clk , co => co ,

reset => reset ) ; reset <= '1' after 150ns, '0' after 450ns; clk <= not clk after 100ns;

END ;

程序C

LIBRARY altera ; LIBRARY cycloneiii ; LIBRARY ieee ;

USE altera.altera_primitives_components.all ; USE cycloneiii.cycloneiii_components.all ; USE ieee.std_logic_1164.all ; ENTITY bcd_counter3_tb IS END ;

ARCHITECTURE bcd_counter3_tb_arch OF bcd_counter3_tb IS SIGNAL q : std_logic_vector (3 downto 0) ; SIGNAL clk : STD_LOGIC := '0' ; SIGNAL co : STD_LOGIC ;

SIGNAL reset : STD_LOGIC := '0' ; COMPONENT bcd_counter3 PORT (

q : out std_logic_vector (3 downto 0) ; clk : in STD_LOGIC ; co : out STD_LOGIC ; reset : in STD_LOGIC ); END COMPONENT ; BEGIN

DUT : bcd_counter3 PORT MAP ( q => q , clk => clk , co => co ,

reset => reset ) ; clk <= not clk after 100ns; reset <= '1' after 50ns, '0' after 350ns; END ;

4、最终的时序波形及输出延时

程序A 时序仿真波形

程序A输出延时的波形及时间

延时7ns 程序B 时序仿真波形

程序B输出延时的波形及时间

延时7ns 程序C 时序仿真波形

程序C输出延时的波形及时间

输出延时5ns