W3E32M72S-266BM中文资料

W3E32M72S-XBX

1

White Electronic Designs Corporation ? (602) 437-1520 ? 1196086acaaedd3383c4d31c

White Electronic Designs

March 2006Rev. 2

White Electronic Designs Corp. reserves the right to change products or speci? cations without notice.32Mx72 DDR SDRAM

FEATURES

Data rate = 200, 250, 266, 333Mbs Package:

? 219 Plastic Ball Grid Array (PBGA), 32 x 25mm 2.5V ±0.2V core power supply 2.5V I/O (SSTL_2 compatible) Differential clock in p uts (CK and CK#) Commands entered on each positive CK edge Internal pipelined double-data-rate (DDR)

ar c hi t ec t ure; two data accesses per clock cy c le Programmable Burst length: 2,4 or 8

Bidirectional data strobe (DQS) transmitted/re c eived with data, i.e., source-syn c hro n ous data capture (one per byte) DQS edge-aligned with data for READs; center-aligned with data for WRITEs DLL to align DQ and DQS transitions with CK Four internal banks for concurrent operation Data mask (DM) pins for masking write data

(one per byte) Programmable IOL/IOH option Auto precharge option

Auto Refresh and Self Refresh Modes Commercial, Industrial and Military

TemperatureRang e s Organized as 32M x 72

Weight: W3E32M72S-XBX – 3.0 grams typical

* This product is subject to change without notice.

BENEFITS

40% SPACE SAVINGS vs. TSOP Re d uced part count 34% I/O reduction vs TSOP

Re d uced trace lengths for low e r par a s it i c

ca p ac i t ance Suit a ble for hi-re l i a bil i t y ap p li c a t ions Lam i n ate in t er p os e r for op t i m um TCE match

GENERAL DESCRIPTION

The 256MByte (2Gb) DDR SDRAM is a high-speed CMOS, dy n am i c ran d om-access, memory using 5 chips containing 536,870,912 bits. Each chip is internally configured as a quad-bank DRAM.

The 256MB DDR SDRAM uses a double data rate ar c hi t ec t ure to achieve high-speed operation. The double data rate ar c hi t ec t ure is essentially a 2n-prefetch architecture with an in t er f ace designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 256MB DDR SDRAM effectively consists of a single 2n-bit wide, one-clock-cycle data tansfer at the internal DRAM core and two cor r e s pond i ng n-bit wide, one-half-clock-cycle data transfers at the I/O pins.A bi-directional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver.strobe transmitted by the DDR SDRAM during READs and by the memory contoller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. Each chip has two data strobes, one for the lower byte and one for the upper byte.

The 256MB DDR SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Com m ands (ad d ress and control signals) are registered at every positive edge of CK. Input data is registered on both edg e s of DQS, and out p ut data is ref e r e nced to both edges of DQS, as well as to both edges of CK.

元器件交易网1196086acaaedd3383c4d31c

W3E32M72S-XBX

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White Electronic Designs Corporation ? (602) 437-1520 ? 1196086acaaedd3383c4d31c

White Electronic Designs

March 2006Rev. 2

White Electronic Designs Corp. reserves the right to change products or speci? cations without notice.DENSITY COMPARISONS

Read and write accesses to the DDR SDRAM are burst ori e nt e d; accesses start at a selected location and continue for a pro g rammed number of locations in a programmed sequence. Accesses begin with the registration of an AC T IVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed. The ad d ress bits registered coincident with the READ or WRITE com m and are used to select the bank and the starting column location for the burst access.

The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4, or 8 locations. An auto precharge func t ion may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access.

The pipelined, multibank architecture of DDR SDRAMs al l ows for concurrent operation, thereby providing high ef f ec t ive band w idth by hiding row precharge and activation time.An auto refresh mode is provided, along with a power-saving power-down mode. All inputs are compatible with the Jedec Standard for SSTL_2. All full drive options outputs are SSTL_2, Class II compatible.

22.3

66TSOP

66TSOP

66TSOP

66TSOP

66TSOP

FUNCTIONAL DE S CRIP T ION

Read and write accesses to the DDR SDRAM are burst ori e nt e d; accesses start at a selected location and continue for a pro g rammed number of locations in a pro g rammed se q uence. Ac c ess e s begin with the registration of an AC T IVE com m and which is then followed by a READ or WRITE com m and. The address bits registered coincident with the AC T IVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank, A0-12 select the row). The address bits registered coincident with the READ or WRITE com m and are used to select the start i ng column location for the burst access.Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed information cov e r i ng device initialization, register de? nition, command de s crip t ions and de v ice operation.

INITIALIZATION

DDR SDRAMs must be powered up and initialized in a pre d e? ned manner. Operational procedures other than those speci? ed may result in unde? ned operation. Power must ? rst be applied to V CC and V CCQ simultaneously, and then to V REF (and to the system V TT ). V TT must be applied

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W3E32M72S-XBX

3White Electronic Designs Corporation ? (602) 437-1520 ? 1196086acaaedd3383c4d31c White Electronic Designs

March 2006

Rev. 2White Electronic Designs Corp. reserves the right to change products or speci? cations without notice.FIGURE 1 – PIN CONFIGURATION NOTE: DNU = Do Not Use.

Top View 1

2345678910111213141516A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T DQ1DQ3DQ6DQ7CAS0#CS0#V SS V SS CLK3#NC DQ56DQ57DQ60DQ62V SS V SS DQ30DQ28DQ25DQ24CLK1CKE1V CC V CC CS2#CAS2#DQ39DQ38DQ35DQ33V CC DQ0DQ2DQ4DQ5DQML0WE0#RAS0#V SS V SS CKE3CLK3DQMH3DQ58DQ59DQ61DQ63DQ31DQ29DQ27DQ26NC DQMH1CLK1#V CCQ V CCQ RAS2#WE2#DQML2DQ37DQ36DQ34DQ32DQ14DQ12DQ10DQ8V CC V CC V CC V CC V CC V CC V CC V CC DQ55DQ53DQ51DQ49DQ17DQ19DQ21DQ23V SS V SS V SS Vss V SS V SS V SS V SS DQ40DQ42DQ44DQ46DQ15DQ13DQ11DQ9DQMH0CLK0CKE0V CCQ V CCQ CS3#CAS3#WE3#DQ54DQ52DQ50DQ48DQ16DQ18DQ20DQ22DQML1WE1#CS1#V SS V SS CKE2CLK2DQMH2DQ41DQ43DQ45DQ47V SS V SS V CC V CCQ DQSH3DQSL3CLK0#V SS V SS DQSL4RAS3#DQML3DQSH4V SS V CC V CCQ V CCQ V CC V SS V SS V REF RAS1#CAS1#V CC V CC CLK2#DQSL2CS4#DQSH2V CC V SS V SS A9A0A2A12DQSH0DQMH4DQ73DQ75DQ77DQ79A8A1A3DNU DQSL1WE4#DQ70DQ68DQ66DQ64A10A7A5DNU BA0CLK4DQ72DQ74DQ76DQ78A11A6A4DNU BA1CAS4#DQ71DQ69DQ67DQ65V SS V SS V CC V CCQ DQSL0CKE4CLK4#V SS V CC V CCQ V CCQ V CC V SS V SS DQSH1RAS4#DQML4V CC V SS V SS 元器件交易网1196086acaaedd3383c4d31c

W3E32M72S-XBX

4

White Electronic Designs Corporation ? (602) 437-1520 ? 1196086acaaedd3383c4d31c

White Electronic Designs

March 2006Rev. 2

White Electronic Designs Corp. reserves the right to change products or speci? cations without notice.

FIGURE 2 – FUNCTIONAL BLOCK DIAGRAM

after V CCQ to avoid device latch-up, which may cause per m a n ent dam a ge to the device. V REF can be applied any time after V CCQ but is expected to be nominally coincident with V TT . Except for CKE, inputs are not recognized as valid until after VREF is applied. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after V CC is applied. After CKE passes through V IH , it will transition to an SSTL_2 signal and remain as such until power is cycled. Maintaining an LVCMOS LOW level on CKE during power-up is required to ensure that the DQ and DQS outputs will be in the High-Z state, where they will remain until driven in normal operation (by a read ac c ess). After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200μs delay prior to applying an executable com m and.Once the 200μs delay has been satis? ed, a DESELECT or NOP command should be applied, and CKE should be brought HIGH. F ollowing the NOP command, a PRECHARGE ALL command should be applied. Next a LOAD MODE REG I S T ER command should be issued for the extended mode register (BA1 LOW and BA0 HIGH) to enable the D LL , fol l owed by another LOAD MODE REGISTER command to the mode register (BA0/BA1 both LOW) to reset the D LL and to program the operating parameters. Two-hundred clock cy c les are required between the DLL reset and any READ command. A PRECHARGE ALL command should then be applied, placing the device in the all banks idle state.

Once in the idle state, two AUTO REFRESH cycles must be performed (t RFC must be satis? ed.) Additionally, a LOAD MODE REGISTER command for the mode register with the reset DLL bit deactivated (i.e., to program operating pa r am e t ers without resetting the DLL) is required. Following these requirements, the DDR SDRAM is ready for normal op e r a t ion.

元器件交易网1196086acaaedd3383c4d31c

W3E32M72S-XBX

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White Electronic Designs Corporation ? (602) 437-1520 ? 1196086acaaedd3383c4d31c

White Electronic Designs

March 2006Rev. 2

White Electronic Designs Corp. reserves the right to change products or speci? cations without notice.REGISTER DEFINITION MODE REGISTER

The Mode Register is used to de? ne the speci? c mode of op e r a t ion of the DDR SDRAM. This de? nition includes the selection of a burst length, a burst type, a CAS latency, and an op e r a t i ng mode, as shown in Figure 3. The Mode Reg i s t er is programmed via the MODE REG I S T ER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored in f or m a t ion until it is pro g rammed again or the device loses power. (Ex c ept for bit A8 which is self clearing).

Reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. The Mode Reg i s t er must be load e d (reloaded) when all banks are idle and no bursts are in progress, and the con t rol l er must wait the spec i ? ed time be f ore ini t i a t i ng the sub s e q uent op e r a t ion. Vi o l at i ng either of these re q uire m ents will result in un s pec i ? ed operation.Mode register bits A0-A2 specify the burst length, A3 spec i ? es the type of burst (sequential or in t er l eaved), A4-A6 spec i f y the CAS latency, and A7-A12 specify the op e r a t i ng mode.

BURST LENGTH

Read and write ac c ess e s to the DDR SDRAM are burst ori e nt e d, with the burst length being programmable, as shown in F ig u re 3. The burst length determines the maximum num b er of column lo c a t ions that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4 or 8 lo c a t ions are avail a ble for both the sequential and the in t er l eaved burst types.Reserved states should not be used, as unknown op e r a t ion or incompatibility with future versions may result.When a READ or WRITE command is issued, a block of col u mns equal to the burst length is effectively selected. All accesses for that burst take place within this block, mean i ng that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-Ai when the burst length is set to two; by A2-Ai when the burst length is set to four (where Ai is the most signi? cant column address for a given con? guration); and by A3-Ai when the burst length is set to eight. The remaining (least sig n i? c ant) ad d ress bit(s) is (are) used to select the starting lo c a t ion within the block. The pro g rammed burst length ap p lies to both READ and WRITE bursts.

BURST TYPE

Accesses within a given burst may be pro g rammed to be

either se q uen t ial or interleaved; this is re f erred to as the burst type and is selected via bit M3.

The ordering of accesses within a burst is de t er m ined by the burst length, the burst type and the start i ng column address, as shown in Table 1.

READ LATENCY

The READ latency is the delay, in clock cycles, between the reg i s t ra t ion of a READ command and the avail a bil i t y of the ? rst bit of output data. The latency can be set to 2 or 2.5 clocks.

If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n+m. Table 2 below indicates the op e r a t i ng fre q uen c ies at which each CAS latency setting can be used.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

OPERATING MODE

The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7-A12 each set to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. Although not re q uired, JEDEC speci? cations recommend when a LOAD MODE REG I S T ER command is issued to reset the DLL, it should always be followed by a LOAD MODE REGISTER command to se l ect nor m al op e r a t i ng mode.All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result.

EXTENDED MODE REGISTER

The extended mode register controls functions beyond

those controlled by the mode register; these additional functions are DLL enable/disable, output drive strength, and QFC. These functions are controlled via the bits shown in Figure 5. The extended mode register is programmed via the LOAD MODE REGISTER command to the mode register (with BA0 = 1 and BA1 = 0) and will retain the stored information until it is programmed again or the

元器件交易网1196086acaaedd3383c4d31c

W3E32M72S-XBX

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White Electronic Designs Corporation ? (602) 437-1520 ? 1196086acaaedd3383c4d31c

White Electronic Designs

March 2006

Rev. 2

White Electronic Designs Corp. reserves the right to change products or speci? cations without notice.device loses power. The enabling of the DLL should always be followed by a LOAD MODE REGISTER command to the mode register (BA0/BA1 both LOW) to reset the DLL.

The extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the speci? ed time before initiating any sub s e q uent operation. Violating either of these requirements could result in unspeci? ed operation.

OUTPUT DRIVE STRENGTH

The normal full drive strength for all outputs are speci? ed to

be SSTL2, Class II. The DDR SDRAM supports an option for reduced drive. This option is intended for the support of the lighter load and/or point-to-point environments. The selection of the reduced drive strength will alter the DQs and DQSs from SSTL2, Class II drive strength to a reduced drive strength, which is approximately 54 percent of the SSTL2, Class II drive strength.

DLL ENABLE/DISABLE

When the part is running without the DLL enabled, device functionality may be altered. The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon re t urn i ng to normal operation after having disabled the DLL for the purpose of debug or evaluation. (When the device exits self refresh mode, the DLL is enabled automatically.) Any time the DLL is enabled, 200 clock cycles with CKE high must occur be f ore a READ command can be issued.

ALLOWABLE OPERATING FREQUENCY (MHz)

SPEED CAS LATENCY = 2

CAS

LATENCY = 2.5

-200≤ 75≤ 100-250≤ 100≤ 125-266≤ 100≤ 133-333

-≤ 166

TABLE 2 - CAS LATENCY

COMMANDS

The Truth Table provides a quick reference of available com m ands. This is followed by a written de s crip t ion of each command.

DESELECT

The DESELECT function (CS# High) prevents new com m ands from be i ng ex e c ut e d by the DDR SDRAM. The SDRAM is ef f ec t ive l y de s e l ect e d. Op e r a t ions already in progress are not af f ect e d.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to perform a NOP to the selected DDR SDRAM (CS# is LOW while RAS#, CAS#, and WE# are high). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected.

LOAD MODE REGISTER

The Mode Registers are loaded via inputs A0-12. The

LOAD MODE REGISTER command can only be issued when all banks are idle, and a subsequent executable com m and cannot be issued until t MRD is met.

ACTIVE

The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs se l ects the bank, and the address pro v id e d on inputs A0-12 selects the row. This row remains active (or open) for ac c ess e s until a PRECHARGE com m and is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank.

READ

The READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-9 se l ects the starting column location. The value on input A10 de t er m ines whether or not AUTO PRECHARGE is used. If AUTO PRECHARGE is selected, the row being accessed will be precharged at the end of the READ burst; if AUTO PRECHARGE is not selected, the row will remain open for subsequent ac c ess e s.

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White Electronic Designs Corporation ? (602) 437-1520 ? 1196086acaaedd3383c4d31c

White Electronic Designs

March 2006Rev. 2

White Electronic Designs Corp. reserves the right to change products or speci? cations without notice.TABLE 1 – BURST DEFINITION

Burst Length

Starting Column

Address

Order of Accesses With i n a Burst Type = Sequential

Type = In t er l eaved

2

A0

00-10-11

1-0

1-0

4

A1A00

00-1-2-30-1-2-3011-2-3-01-0-3-21 02-3-0-12-3-0-11

13-0-1-2

3-2-1-0

8

A2A1A00000-1-2-3-4-5-6-70-1-2-3-4-5-6-70011-2-3-4-5-6-7-01-0-3-2-5-4-7-60

102-3-4-5-6-7-0-12-3-0-1-6-7-4-50113-4-5-6-7-0-1-23-2-1-0-7-6-5-41004-5-6-7-0-1-2-34-5-6-7-0-1-2-31015-6-7-0-1-2-3-45-4-7-6-1-0-3-21106-7-0-1-2-3-4-56-7-4-5-2-3-0-11

1

1

7-0-1-2-3-4-5-6

7-6-5-4-3-2-1-0

NOTES:

1. For a burst length of two, A1-Ai select two-data-element block; A0

selects the starting column within the block.

2. For a burst length of four, A2-Ai select four-data-element block; A0-1

select the starting column within the block.

3. For a burst length of eight, A3-Ai select eight-data-element block;

A0-2 select the starting column within the block.

4. Whenever a boundary of the block is reached within a given

sequence above, the following access wraps within the block.

FIGURE 3 – MODE REGISTER DEFINITION

WRITE

The WRITE command is used to initiate a burst write access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-9 se l ects the starting column location. The value on input A10 de t er m ines whether or not AUTO PRECHARGE is used. If AUTO PRECHARGE is selected, the row being accessed will be precharged at the end of the WRITE burst; if AUTO PRECHARGE is not selected, the row will remain open for sub s e q uent accesses. Input data appearing on the DQ is written to the memory array subject to the DQM input logic level ap p ear i ng co i n c i d ent with the data. If a given DQM signal is reg i s t ered LOW, the cor r e s pond i ng data will be written to mem o r y; if the DQM signal is reg i s t ered HIGH, the cor r e s pond i ng data inputs will be ignored, and a WRITE will not be executed to that byte/column location.

PRECHARGE

The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a speci? ed time (t RP ) after the PRECHARGE command is is s ued. Except in the case of concurrent auto precharge, where a READ or WRITE command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing pa r am e t ers. Input A10 de t er m ines wheth e r one or all banks are to be precharged, and in the case where only one bank is to be precharged, in p uts BA0, BA1 select the bank. Oth e r w ise BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and

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W3E32M72S-XBX

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White Electronic Designs Corporation ? (602) 437-1520 ? 1196086acaaedd3383c4d31c

White Electronic Designs

March 2006

Rev. 2

White Electronic Designs Corp. reserves the right to change products or speci? cations without notice.

FIGURE 4 – CAS LATENCY

FIGURE 5 – EXTENDED MODE REGISTER

DEFINITION

must be ac t i v at e d pri o r to any READ or WRITE commands being is s ued to that bank. A PRECHARGE com m and will be treat e d as a NOP if there is no open row in that bank (idle state), or if the previously open row is already in the pro c ess of precharging.AUTO PRECHARGE

AUTO PRECHARGE is a feature which performs the

same in d i v id u a l-bank PRECHARGE function de s cribed above, but with o ut re q uir i ng an explicit command. This is ac c om p lished by using A10 to enable AUTO PRECHARGE in conjunction with a spe c i? c READ or WRITE command. A precharge of the bank/row that is ad d ressed with the READ or WRITE com m and is au t o m at i c al l y performed upon com p le t ion of the READ or WRITE burst. AUTO PRECHARGE is non p er s is t ent in that it is either en a bled or dis a bled for each in d i v id u a l READ or WRITE command. The device sup p orts concurrent auto precharge if the com m and to the oth e r bank does not in t er r upt the data transfer to the current bank.

AUTO PRECHARGE ensures that the precharge is initiated at the earliest valid stage within a burst. This

“earliest valid stage” is determined as if an explicit

precharge command was is s ued at the earliest possible time, without violating t RAS (MIN).The user must not is s ue an o th e r com m and to the same bank until the precharge time (t RP ) is com p let e d.

BURST TERMINATE

The BURST TERMINATE command is used to truncate READ bursts (with auto precharge disabled). The most recently registered READ command prior to the BURST TERMINATE command will be truncated. The open page which the READ burst was terminated from remains open.

AUTO REFRESH

AUTO REFRESH is used during normal op e r a t ion of the DDR SDRAM and is analogous to CAS-BEF ORE-RAS (CBR) RE F RESH in con v en t ion a l DRAMs. This com m and is non p er s is t ent, so it must be issued each time a refresh is required. All banks must be idle before an AUTO REFRESH command is issued.

The addressing is generated by the internal refresh con t rol l er. This makes the address bits “Don’t Care”

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White Electronic Designs Corporation ? (602) 437-1520 ? 1196086acaaedd3383c4d31c

White Electronic Designs

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White Electronic Designs Corp. reserves the right to change products or speci? cations without notice.TRUTH TABLE – COMMANDS (NOTE 1)

NOTES:

1. CKE is HIGH for all commands shown except SELF REFRESH.

2. A0-12 de? ne the op-code to be written to the selected Mode Register. BA0, BA1

select either the mode register (0, 0) or the extended mode register (1, 0).3. A0-12 provide row address, and BA0, BA1 provide bank address.

4. A0-9 provide column address; A10 HIGH enables the auto precharge feature (non

persistent), while A10 LOW disables the auto precharge feature; BA0, BA1 provide bank address.

5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks

precharged and BA0, BA1 are “Don’t Care.”

NAME (FUNCTION)CS#RAS#CAS#WE#ADDR DESELECT (NOP) (9)H X X X X NO OPERATION (NOP) (9)

L H H H X ACTIVE (Select bank and activate row) ( 3)

L L H H Bank/Row READ (Select bank and column, and start READ burst) (4)L H L H Bank/Col WRITE (Select bank and column, and start WRITE burst) (4) L H L L Bank/Col BURST T E RMINAT E

(8)

L H H L

X PRECHARGE (Deactivate row in bank or banks) ( 5)

L L H L Code AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7)L L L H X LOAD MODE REGISTER (2)L

L

L

L

Op-Code

TRUTH TABLE – DM OPERATION

NAME (FUNCTION)DM DQs WRITE ENABLE (10)L Valid WRITE INHIBIT (10)

H

X

6.

This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is

LOW.

7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t

Care” except for CKE.

8. Applies only to read bursts with auto precharge disabled; this command is

unde? ned (and should not be used) for READ bursts with auto precharge enabled and for WRITE bursts.

9. DESELECT and NOP are functionally interchangeable.

10. Used to mask write data; provided coincident with the corresponding data.

during an AUTO RE F RESH command. Each DDR SDRAM requires AUTO RE F RESH cycles at an average interval of 7.8125μs (maximum).

To allow for improved efficiency in scheduling and switch i ng between tasks, some ? exibility in the absolute refresh interval is provided. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM, mean i ng that the maximum absolute interval between any AUTO REF RESH command and the next AUTO REFRESH command is 9 x 7.8125μs (70.3μs). This maximum absolute interval is to allow future support for DLL updates internal to the DDR SDRAM to be restricted to AUTO REF RESH cycles, without allowing excessive drift in t AC between updates.

Although not a JEDEC requirement, to provide for future func t ion a l i ty features, CKE must be active (High) during the AUTO REFRESH period. The AUTO REFRESH period begins when the AUTO REFRESH command is registered and ends t RFC later.

SELF REFRESH*

The SELF REF RESH command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the DDR SDRAM re t ains data with o ut external clocking. The SELF RE F RESH com m and is ini t i a t e d like an AUTO REFRESH com m and except CKE is dis a bled (LOW). The DLL is automatically disabled upon entering SELF REFRESH and is automatically enabled upon exiting SELF REFRESH (A DLL reset and 200 clock cycles must then oc c ur before a READ command can be issued). Input sig n als except CKE are “Don’t Care” during SELF REFRESH. VREF voltage is also required for the full duration of SELF REFRESH.The procedure for exiting self refresh requires a sequence of commands. F irst, CK and CK# must be stable prior to CKE going back HIGH. Once CKE is HIGH, the DDR SDRAM must have NOP commands is s ued for t XSNR , be c ause time is required for the com p le t ion of any internal refresh in progress.

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White Electronic Designs Corp. reserves the right to change products or speci? cations without notice.A simple algorithm for meeting both refresh and DLL re q uire m ents is to apply NOPs for t XSNR time, then a DLL Reset and NOPs for 200 additional clock cycles before applying any other command.

* Self refresh available in commercial and industrial temperatures only.

ABSOLUTE MAXIMUM RATINGS

Parameter

Unit Voltage on V CC , V CCQ Supply relative to Vss -1 to 3.6V Voltage on I/O pins relative to Vss -0.5V to V CCQ +0.5V

V Operating Temperature T A (Mil)-55 to +125°C Operating Temperature T A (Ind)-40 to +85°C Storage Temperature, Plastic

-55 to +125

°C

NOTE:Stress greater than those listed under "Absolute Maximum Ratings" may cause per m a n ent damage to the device. This is a stress rating only and func t ion a l op e r a t ion of the device at these or any other conditions greater than those in d i c at e d in the operational sections of this speci? cation is not implied. Exposure to ab s o l ute maximum rating con d i t ions for extended periods may affect reliability.

CAPACITANCE (NOTE 13)

Parameter

Symbol

Max

Unit

Input Capacitance: CK/CK#C I18pF Addresses, BA 0-1 Input Capacitance CA 32pF Input Capacitance: All other input-only pins C I2

10

pF

Input/Output Capacitance: I/Os

C IO 12

pF

BGA THERMAL RESISTANCE

Description

Symbol Max Units Notes Junction to Ambient (No Air? ow)Theta JA 13.7°C/W 1Junction to Ball Theta JB 10.3°C/W 1Junction to Case (Top)

Theta JC

4.6

°C/W

1

Refer to "PBGA Thermal Resistance Correlation" Application Note at 1196086acaaedd3383c4d31c in the application notes section for modeling conditions.

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White Electronic Designs Corp. reserves the right to change products or speci? cations without notice.DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (NOTES 1-5, 16)

V CC , V CCQ = +2.5V ± 0.2V; -55°C ≤ T A ≤ +125°C

Parameter/Condition Symbol Min Max Units Supply Voltage (36, 41)V CC 2.3

2.7V I/O Supply Voltage (36, 41, 44)

V CCQ 2.3 2.7V Input Leakage Current: Any input 0V ≤ V IN ≤ V CC (All other pins not under test = 0V)II -2 2 μA Input Leakage Address Current (All other pins not under test = 0V)II -1010μA

Output Leakage Current: I/Os are disabled; 0V ≤ V OUT ≤ V CCQ I OZ -5

5 μA Output Levels: Full drive option (37, 39)

High Current (V OU T = V CCQ - 0.373V, minimum V REF , minimum V TT )Low Current (V OUT = 0.373V, maximum V RE F, maximum V TT )I OH -16.8-mA I OL 16.8-mA Output Levels: Reduced drive option (38, 39)

High Current (V OUT = V CCQ - 0.763V, minimum V REF , minimum V TT )Low Current (V OUT = 0.763V, maximum V REF , maximum V TT )I OHR -9-mA I OLR 9-mA I/O Reference Voltage (6,44)V REF 0.49 x V CCQ 0.51 x V CCQ V I/O Termination Voltage (7, 44)

V TT

V REF - 0.04

V REF + 0.04

V

AC INPUT OPERATING CONDITIONS

V CC , V CCQ = +2.5V ± 0.2V; -55°C ≤ T A ≤ +125°C

Parameter/Condition Symbol Min Max Units Input High (Logic 1) Voltage

V IH V REF +0.310

—V V IL

—

V REF -0.310

V

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White Electronic Designs Corp. reserves the right to change products or speci? cations without notice.I CC SPECIFICATIONS AND CONDITIONS (NOTES 1-5, 10, 12, 14)

V CC , = +2.5V ± 0.2V; -55°C ≤ T A ≤ +125°C

Parameter/Condition

Symbol

M AX

333Mbs 250Mbs

266Mbs 200Mbs

Units OPERATING CURRENT: One bank; Active-Precharge; t RC = t RC (MIN); t CK = t CK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles; (22, 48)

I CC0650650575mA OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2; t RC = t RC (MIN); t CK = t CK (MIN); I OUT = 0mA; Address and control inputs changing once per clock cycle (22, 48)

I CC1800800725mA PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down mode; t CK = t CK (MIN); CKE = LOW; (23, 32, 50)

I CC2P 252525mA IDLE STANDBY CURRENT: CS# = HIGH; All banks idle; t CK = t CK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. V IN = V REF for DQ, DQS, and DM (51)

I CC2F 225225200mA ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; Power-down mode; t CK = t CK (MIN); CKE = LOW (23, 32, 50)

I CC3P 175175150mA ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One bank; Active-Precharge; t RC = t RAS (MAX); t CK = t CK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle (22)

I CC3N 250250225mA OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; t CK = t CK (MIN); I OUT = 0mA (22, 48)

I CC4R 825825725mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; t CK = t CK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle (22)

I CC4W 975755675mA AUTO REFRESH CURRENT

t REF = t RC (MIN) (27, 50)I CC51,4501,4501,400mA t REF = 7.8125μs (27, 50)I CC5A 505050mA SELF REFRESH CURRENT: CKE ≤ 0.2V

Standard (11)

I CC6252525mA OPERATING CURRENT: Four bank interleaving READs (BL=4) with auto precharge, t RC =t RC (MIN); t CK = t CK (MIN); Address and control inputs change only during Active READ or WRITE commands. (22, 49)

I CC7

2,025

2,000

1,750

mA

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White Electronic Designs Corp. reserves the right to change products or speci? cations without notice.333 Mbs CL 2.5

266 Mbs CL 2.5200 CL 2250 Mbs CL2.5200 Mbs CL2200 Mbs CL2.5150 Mbs CL2Parameter

Symbol Min Max Min Max Min Max Min Max Units Access window of DQs from CK/CK# t AC -0.70+0.70-0.75+0.75-0.8+0.8-0.8+0.8ns CK high-level width (30)t CH 0.450.55 0.450.55 0.45

0.550.450.55t CK CK low-level width (30)t CL 0.450.550.450.550.450.550.450.55t CK Clock cycle time

CL = 2.5 (45, 51)t CK (2.5)7.5

13

7.5138131013ns CL = 2 (45, 51)

t CK

(2)1013

1013

1315

ns DQ and DM input hold time relative to DQS (26, 31)t DH 0.450.50.60.6ns DQ and DM input setup time relative to DQS (26, 31) t DS 0.450.50.60.6ns DQ and DM input pulse width (for each input) (31)t DIPW 1.75 1.7522

ns

Access window of DQS from CK/CK# t DQSCK -0.6+0.6

-0.75+0.75-0.8+0.8 -0.8

+0.8 ns

DQS input high pulse width t DQSH

0.350.350.350.35t CK DQS input low pulse width

t DQSL

0.35

0.35

0.35

0.35

t CK DQS-DQ skew, DQS to last DQ valid, per group, per access (25, 26)t DQSQ

0.45

0.50.60.6ns Write command to ? rst DQS latching transition t DQSS 0.75 1.25

0.75 1.25

0.75 1.25

0.75 1.25t CK DQS falling edge to CK rising - setup time t DSS 0.20.20.20.2t CK DQS falling edge from CK rising - hold time t DSH 0.20.20.20.2t CK Half clock period (34)

t HP t CH , t CL

t CH ,t CL

t CH ,t CL

t CH ,t CL

ns Data-out high-impedance window from CK/CK# (18, 42)t HZ +0.70

+0.75

+0.8

+0.8

ns Data-out low-impedance window from CK/CK# (18, 42)t LZ -0.70-0.75-0.8-0.8ns Address and control input hold time (fast slew rate)t IH F 0.750.90 1.1 1.1ns

Address and control input setup time (fast slew rate)t IS F 0.750.90 1.1 1.1 ns

Address and control input hold time (slow slew rate) (14)t IH S 0.81 1.1 1.1ns

Address and control input setup time (slow slew rate) (14)t IS S 0.81 1.1 1.1 ns

LOAD MODE REGISTER command cycle time

t MRD 121516

16ns DQ-DQS hold, DQS to ? rst DQ to go non-valid, per access (25, 26)t QH t HP - t QHS

t HP -t QHS

t HP -t QHS

t HP -t QHS

ns Data hold skew factor

t QHS 0.550.7511ns ACTIVE to PRECHARGE command (35)t RAS 4270,000

40120,000

40120,000

40120,000ns ACTIVE to READ with Auto precharge command t RAP 15202020ns ACTIVE to ACTIVE/AUTO REFRESH command period t RC 60657070ns AUTO REFRESH command period (49)t RFC 72758080ns ACTIVE to READ or WRITE delay t RCD 15202020ns PRECHARGE command period t RP 15202020

ns DQS read preamble (43)t RPRE 0.9 1.1

0.9 1.1

0.9 1.10.9 1.1t CK DQS read postamble (43)

t RPST 0.4 0.60.4 0.6

0.40.6

0.40.6t CK ACTIVE bank a to ACTIVE bank b command t RRD 12151515ns DQS write preamble

t WPRE 0.250.250.250.25t CK DQS write preamble setup time (20, 21)t WPRES 0000

ns DQS write postamble (19)t WPST 0.40.60.40.60.40.6

0.40.6t CK Write recovery time

t WR 15151515ns Internal WRITE to READ command delay t WTR 1

1

1

1

t CK Data valid output window (25)

na t QH - t DQSQ

t QH - t DQSQ

t QH - t DQSQ

t QH - t DQSQ

ns REFRESH to REFRESH command interval (23) (Commercial & Industrial only)t REFC 70.370.370.370.3μs REFRESH to REFRESH command interval (23) (Military temperature only)*t REFC 35353535.15μs Average periodic refresh interval (23) (Commercial & Industrial only)t REFI 7.87.87.87.8μs Average periodic refresh interval (23) (Military temperature only)*t REFI 3.8

3.9

3.9

3.9μs Terminating voltage delay to VDD

t VTD 0000ns Exit SELF REFRESH to non-READ command t XSNR 75758080ns Exit SELF REFRESH to READ command

t XSRD

200200

200

200t CK

* Self refresh available in commercial and industrial temperatures only.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CHARACTERISTICS

Notes 1-5, 14-17, 33

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White Electronic Designs Corp. reserves the right to change products or speci? cations without notice.NOTES:

1. All voltages referenced to VSS.

2. Tests for AC timing, I CC , and electrical AC and DC characteristics may be

conducted at nominal reference/supply voltage levels, but the related speci? cations and device operation are guaranteed for the full voltage range speci? ed.3. Outputs measured with equivalent load:

4.

AC timing and I CC tests may use a V IL -to-V IH swing of up to 1.5V in the test

environment, but input timing is still referenced to V REF (or to the crossing point for CK/CK#), and parameter speci? cations are guaranteed for the speci? ed AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ns in the range between V IL (AC) and V IH (AC).5. The AC and DC input level speci? cations are as de? ned in the SSTL_2 Standard

(i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level).

6. V REF is expected to equal V CCQ/2 of the transmitting device and to track variations

in the DC level of the same. Peak-to-peak noise (noncommon mode) on V REF may not exceed ±2 percent of the DC value. Thus, from V CCQ/2, V REF is allowed ±25mV for DC error and an additional ±25mV for AC noise. This measurement is to be taken at the nearest V REF by-pass capacitor.

7. V TT is not applied directly to the device. V TT is a system supply for signal

termination resistors, is expected to be set equal to V REF and must track variations in the DC level of V REF .

8. V ID is the magnitude of the difference between the input level on CK and the input

level on CK#.

9. The value of V IX and V MP are expected to equal V CCQ/2 of the transmitting device

and must track variations in the DC level of the same.10. I CC is dependent on output loading and cycle rates. Speci? ed values are obtained

with minimum cycle time with the outputs open.11. Enables on-chip refresh and address counters.12. I CC speci? cations are tested after the device is properly initialized, and is averaged

at the de? ned cycle rate.

13. This parameter is not tested but guaranteed by design. t A = 25°C, F= 1 MHz

14. For slew rates less than 1V/ns and greater than or equal to 0.5 V.ns. If the slew

rate is less than 0.5V/ns, timing must be derated: t IS has an additional 50 ps per each 100mV/ns reduction in slew rate from the 500mV/ns. t IH has 0ps added, that is, it remains constant. If the slew rate exceeds 4.5V/ns, functionality is uncertain. 15. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at

which CK# and CK# cross; the input reference level for signals other than CK/CK# is V REF .

16. Inputs are not recognized as valid until V REF stabilizes. Once initialized, including

SELF REFRESH mode, V REF must be powered within speci? ed range. Exception: during the period before V REF stabilizes, CKE ≤ 0.3 x V CCQ is recognized as LOW.17. The output timing reference level, as measured at the timing reference point

indicated in Note 3, is V TT .

18. t HZ and t LZ transitions occur in the same access time windows as valid data

transitions. These parameters are not referenced to a speci? c voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ).19. The intent of the Don't Care state after completion of the postamble is the DQS-driven signal should either be high, low, or high-Z and that any signal transition within the input switching region must follow valid input requirements. That is, if DQS transitions high (above V IH DC(MIN) then it must not transition low (below V IH DC) prior to t DQSH (MIN).

20. This is not a device limit. The device will operate with a negative value, but system

performance could be degraded due to bus turnaround.

21. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE

command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on t DQSS .22. MIN (t RC or t RFC ) for I CC measurements is the smallest multiple of tCK that meets

the minimum absolute value for the respective parameter. t RAS (MAX) for I CC measurements is the largest multiple of t CK that meets the maximum absolute value for t RAS .

23. The refresh period 64ms. (32ms for Military grade) This equates to an average

refresh rate of 7.8125μs. However, an AUTO REFRESH command must be asserted at least once every 70.3μs; (35μs for Military grade) burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed.24. The I/O capacitance per DQS and DQ byte/group will not differ by more than this

maximum amount for any given device.

25. The valid data window is derived by achieving other speci? cations - t HP (t CK/2),

t DQSQ , and t QH (t QH = t HP - t QHS ). The data valid window derates directly porportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio. The data valid window derating curves are provided below for duty cycles ranging between 50/50 and 45/55.

160140120

100

80

60

40200

0.0 0.5 1.0 1.5 2.0 2.5

V OUT (V)I O U T (m A )

Maximum

Nominal high

Nominal low

Minimum

?

Output (V OUT )

FIGURE A – FULL DRIVE PULL-DOWN

CHARACTERISTICS

FIGURE B – FULL DRIVE PULL-UP

CHARACTERISTICS

0-20-40

-60-80-100-120-140-160

-180-200

0.0 0.5 1.0 1.5 2.0 2.5

V CCQ - V OUT (V)

I O U T (m A )

Maximum

Nominal high

Nominal low

Minimum 元器件交易网1196086acaaedd3383c4d31c

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White Electronic Designs Corp. reserves the right to change products or speci? cations without notice.26. Referenced to each output group: DQSL with DQ0-DQ7; and DQSH with DQ8-DQ15 of each chip.

27. This limit is actually a nominal value and does not result in a fail value. CKE is

HIGH during REFRESH command period (t RFC [MIN]) else CKE is LOW (i.e., during standby).

28. To maintain a valid level, the transitioning edge of the input must:

a) Sustain a constant slew rate from the current AC level through to the target AC

level, V IL (AC) or V IH (AC).

b) Reach at least the target AC level.

c) After the AC target level is reached, continue to maintain at least the target DC

level, V IL (DC) or V IH (DC).

29. The Input capacitance per pin group will not differ by more than this maximum

amount for any given device.

30. CK and CK# input slew rate must be ≤ 1V/ns (≤2V/ns differentially).

31. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the

DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to t DS and t DH for each 100mV/ns reduction in slew rate. If slew rate exceeds 4V/ns, functionality is uncertain.

32. V CC must not vary more than 4% if CKE is not active while any bank is active.33. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to

vary by the same amount.

34. t HP min is the lesser of t CL minimum and t CH minimum actually applied to the device

CK and CK# inputs, collectively during bank active.

35. READs and WRITEs with auto precharge are not allowed to be issued until

t RAS (MIN) can be satis? ed prior to the internal precharge command being issued.36. Any positive glitch must be less than 1/3 of the clock and not more than +400mV or

2.9 volts, whichever is less. Any negative glitch must be less than

1/3 of the clock cycle and not exceed either -300mV or 2.2 volts, whichever is more positive. The average cannot be below the 2.5V minimum.37. Normal Output Drive Curves:

a) The full variation in driver pull-down current from minimum to maximum

process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure A.

b) The variation in driver pull-down current within nominal limits of voltage and

temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure A.

c) The full variation in driver pull-up current from minimum to maximum process,

temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure B.

d) The variation in driver pull-up current within nominal limits of voltage and

temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure B.

e) The full variation in the ratio of the maximum to minimum pull-up and pull-down

current should be between .71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0 Volt, and at the same voltage and temperature.

f) The full variation in the ratio of the nominal pull-up to pull-down current should

be unity ±10%, for device drain-to-source voltages from 0.1V to 1.0 Volt.

38. Reduced Output Drive Curves:

a) The full variation in driver pull-down current from minimum to maximum

process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure C.

b) The variation in driver pull-down current within nominal limits of voltage and

temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure C.

c) The full variation in driver pull-up current from minimum to maximum process,

temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure D.

d) The variation in driver pull-up current within nominal limits of voltage and

temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure D.

e) The full variation in the ratio of the maximum to minimum pull-up and pull-down

current should be between .71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0 V, and at the same voltage and temperature.

f) The full variation in the ratio of the nominal pull-up to pull-down current should

be unity ±10%, for device drain-to-source voltages from 0.1V to 1.0 V.

39. The voltage levels used are derived from a minimum V CC level and the referenced

test load. In practice, the voltage levels obtained from a properly terminated bus will provide signi? cantly different voltage values.

40. V IH overshoot: V IH (MAX) = V CCQ +1.5V for a pulse width ≤ 3ns and the pulse width

can not be greater than 1/3 of the cycle rate. V IL undershoot: V IL (MIN) = -1.5V for a pulse width ≤ 3ns and the pulse width cannot be greater than 1/3 of the cycle rate.41. V CC and V CCQ must track each other.

42. t HZ (MAX) will prevail over t DQSCK (MAX) + t RPST (MAX) condition. t LZ (MIN) will

prevail over t DQSCK (MIN) + t RPRE (MAX) condition.

43. t RPST end point and t RPRE begin point are not referenced to a speci? c voltage level

but specify when the device output is no longer driving (t RPST ), or begins driving (t RPRE ).44. During initialization, V CCQ , V TT , and V REF must be equal to or less than V CC + 0.3V.

Alternatively, V TT may be 1.35V maximum during power up, even if V CC /V CCQ are 0 volts, provided a minimum of 42 ohms of series resistance is used between the V TT supply and the input pin.

45. The current part operates below the slowest JEDEC operating frequency of 83 MHz.

As such, future die may not re? ect this option.46. When an input signal is HIGH or LOW, it is de? ned as a steady state logic HIGH or

LOW.

FIGURE C – REDUCED DRIVE PULL-DOWN

CHARACTERISTICS

80

706050

4030

20100

0.0 0.5 1.0 1.5 2.0 2.5

V OUT (V)I O U T (m A )

Maximum

Nominal high

Nominal low

Minimum

FIGURE D – REDUCED DRIVE PULL-UP

CHARACTERISTICS

0.0 0.5 1.0 1.5 2.0 2.5

V CCQ - V OUT (V)

I O U T (m A )

Maximum

Nominal high

Nominal low

Minimum 0-10-20-30

-40-50-60-70

-80

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Rev. 2White Electronic Designs Corp. reserves the right to change products or speci? cations without notice.47. Random addressing changing: 50% of data changing at every transfer.

48. Random addressing changing: 100% of data changing at every transfer.

49. CKE must be active (high) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be

active at each rising clock edge, until t RFC has been satis? ed.

50. I CC2N speci? es the DQ, DQS, and DQM to be driven to a valid high or low logic

level. I CC2Q is similar to I CC2F except I CC2Q speci? es the address and control inputs

to remain stable. Although I CC2F , I CC2N , and I CC2Q are similar, I CC2F is “worst case.”

51. Whenever the operating frequency is altered, not including jitter, the DLL is

required to be reset followed by 200 clock cycles before any READ command.

52. This is the DC voltage supplied at the DRAM and is inclusive of all noise up to 20 MHz. Any noise above 20 MHz at the DRAM generated from any source other than

that of the DRAM itself may not exceed the DC coltage range of 2.6V ± 100mV.元器件交易网1196086acaaedd3383c4d31c

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Rev. 2White Electronic Designs Corp. reserves the right to change products or speci? cations without notice.All linear dimensions are millimeters and parenthetically in inches

PACKAGE DIMENSION: 219 PLASTIC BALL GRID ARRAY (PBGA)

元器件交易网1196086acaaedd3383c4d31c

W3E32M72S-XBX

18White Electronic Designs Corporation ? (602) 437-1520 ? 1196086acaaedd3383c4d31c White Electronic Designs

March 2006

Rev. 2White Electronic Designs Corp. reserves the right to change products or speci? cations without notice.ORDERING INFORMATION WHITE ELECTRONIC DESIGNS CORP .

DDR SDRAM

CONFIGURATION, 32M x 72

2.5V Power Supply

DATA RATE (Mbs/MHz)

200 = 200Mbs/100mHz

250 = 250Mbs/125mHz

266 = 266Mbs/133mHz

333 = 333Mbs/166mHz

PACKAGE:

B = 219 Plastic Ball Grid Array (PBGA)

DEVICE GRADE:

M = Military -55°C to +125°C

I = In d us t ri a l -40°C to +85°C

C = Com m er c ial 0°C to +70°C

W 3E 32M 72 S - XXX B X

元器件交易网1196086acaaedd3383c4d31c

W3E32M72S-XBX 19White Electronic Designs Corporation ? (602) 437-1520 ? 1196086acaaedd3383c4d31c White Electronic Designs

March 2006

Rev. 2White Electronic Designs Corp. reserves the right to change products or speci? cations without notice.Document Title

32M x 72 DDR SDRAM, 219 PBGA Multi-Chip Package, 25mm x 32mm Revision History

Rev #

History Release Date Status Rev 0

Initial Release May 2004Advanced Rev 1Changes (Pg. 1, 10, 18, 19)

1.1 Update capacitance table values

1.2 Update thermal resistance table values

1.3 Change max storage temperature to 125°C

1.4 Change package typical weight to 3.0g.January 2005Final

Rev 2Changes (Pg. All)

2.1 All 333Mbs option March 2006Final

元器件交易网1196086acaaedd3383c4d31c

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