VHDL复习题

VHDL期末复习题

例题：

1、74LS669是带先行进位的4位同步二进制可逆加减计数器，用VHDL描述74LS669的逻辑功能（updn是计数方式控制）。

LIBRARY IEEE；

USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; entity my74ls669 is

port (clk, clr, updn,cin: IN STD_LOGIC; qa,qb,qc,qd,co: OUT STD_LOGIC); end my74ls669;

architecture RTL of my74ls669 is

signal count_4: STD_LOGIC_VECTOR(3 downto 0); begin

qa<=count_4(0); qb<=count_4(1); qc<=count_4(2); qd<=count_4(3);

process (clk, clr, updn) --处理可逆计数 begin

if (clr=‘1’) then

count_4=“0000”

elsif (clk’event and clk=‘1’) then if (updn＝’1’）then

count_4<=count_4 +’1’; --加计数 else

count_4<=count_4 -’1’; --减计数 end if; end if; end process;

process(cin,count_4) --处理进位输出co； begin

if (cin=‘1’ and count_4=“1111”)then co<=‘1’ ; else

co<=‘0’ ; end if ; end process ; end rtl;

2、十进制计数器(模十计数器) 方法一

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY COUNT10 IS

PORT (CLK,RST,EN：IN STD_LOGIC;

CQ：OUT STD_LOGIC_VECTOR(3 DOWNTO 0); COUT：OUT STD_LOGIC ); END COUNT10;

ARCHITECTURE behave OF COUNT10 IS BEGIN

PROCESS(CLK, RST, EN)

VARIABLE CQI : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN

IF RST = '1' THEN CQI := (OTHERS =>'0') ;

ELSIF CLK'EVENT AND CLK='1' THEN IF EN = '1' THEN

IF CQI < 9 THEN CQI := CQI + 1; ELSE CQI := (OTHERS =>'0'); END IF; END IF; END IF;

IF CQI = 9 THEN COUT <= '1';

ELSE COUT <= '0'; END IF; CQ <= CQI; END PROCESS; END behave;

十进制计数器(模十计数器) 方法二

library IEEE;

use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity count10 is

Port (CLK: in std_logic; rst : in std_logic;

Q: out std_logic_vector(3 downto 0)); end count10;

architecture Behavioral of count10 is signal Qn: std_logic_vector(3 downto 0); begin

process(cp,rst) begin

if (rst='1') then qn<=\

elsif (CLK'event and CLK='1')then if (Qn=\Qn<=\else Qn<=Qn+1; end if; end if;

end process; Q<=Qn;

end Behavioral;

3、模三计数器（3进制计数器）

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter3 is

port(clk,reset,en:in std_logic; qa,qb:out std_logic); end counter3;

architecture behavior of counter3 is

signal count:std_logic_vector(1 downto 0); begin

process(reset,clk) begin

if reset='1'then

count(1 downto 0)<=\else

if(clk 'event and clk='1')then if(en='1')then if(count=\count<=\else

count<=count+1; end if; end if; end if; end if;

end process; qa<=count(0); qb<=count(1); end behavior;

4、计数器：带允许端的模12计数器VHDL设计

LIBRARY IEEE；

USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; entity COUNT12 is

port (clk,clr,en: IN STD_LOGIC;

qa,qb,qc,qd: OUT STD_LOGIC); End COUNT12 ;

Architecture RTL of COUNT12 is

Signal count_4 : STD_LOGIC_VECTOR(3 downto 0); Begin

qa<=count_4(0); qb<=count_4(1);

qc<=count_4(2); qd<=count_4(3); Process (clk,clr) begin

if (clr=‘1’) then coun_4<=“0000”;

elsif (clk’event and clk=‘1’) then if (en=‘1’) then

if (count_4=“1011” )then count_4<=“0000”; else

coun_4<=count_4+’1’; end if; end if; end if; end process; End rtl;

5、带有WHEN OTHERS项的3—8译码器的行为描述的例子，输出低电平有效。

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164; ENTITY decode_3to8 IS

PORT(a,b,c,G1,G2A,G2B:IN STD_LOGIC;

y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END decode_3to8;

ARCHITECTURE rtl OF decode_3to8 IS

SIGNAL indate:STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN

indate <=c & b & a;

PROCESS(indate,G1,G2A,G2B) BEGIN

IF (G1=111AND G2A=101AND G2B=101)THEN CASE indate IS

WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN OTHERS =>y<=\ END CASE; ELSE

y<=\

END IF; END PROCESS; END rtl;

6、10-2编码器。

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY encodey IS

PORT(input:IN STD_LOGIC_VECTOR(9 DOWNTO 0); y: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END encoder;

ARCHITECTURE rtl OF encoder IS BEGIN

PROCESS(input) BEGIN

CASE input IS

WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \

WHEN \

WHEN \ WHEN OTHERS=>y<=\ END CASE; END PROCESS; END rtl;

7、2-10译码器。

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY encoder IS

PORT(input:IN STD_LOGIC_VECTOR(3 DOWNTO 0); y: OUT STD_LOGIC_VECTOR(9 DOWNTO 0)); END encoder;

ARCHITECTURE rtl OF encoder IS BEGIN

PROCESS(input) BEGIN

CASE input IS

WHEN \ WHEN \

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