基于DSP28035的SPWM生成程序

#include \#include \//#include \

#define PWM1_INT_ENABLE 1 #define PWM2_INT_ENABLE 1 #define PWM3_INT_ENABLE 1 #define PWM4_INT_ENABLE 1 void InitEPwm1Example(void); void InitEPwm2Example(void); void InitEPwm3Example(void);

interrupt void epwm1_timer_isr(void); //interrupt void epwm2_timer_isr(void); //interrupt void epwm3_timer_isr(void);

Uint32 EPwm1TimerIntCount; Uint32 EPwm2TimerIntCount; Uint32 EPwm3TimerIntCount; Uint32 EPwm4TimerIntCount; Uint32 TonC1,TonC2; Uint16 k; float32 Tc,N;

#define PI 3.1415926 float32 M=0.8; float32 fz=20000; float32 fr=50; void main(void) {

InitSysCtrl(); InitEPwm1Gpio(); // InitEPwm2Gpio(); // InitEPwm3Gpio(); DINT; InitPieCtrl(); IER = 0x0000; IFR = 0x0000;

InitPieVectTable();

EALLOW; // This is needed to write to EALLOW protected registers PieVectTable.EPWM1_INT = &epwm1_timer_isr; // PieVectTable.EPWM2_INT = &epwm2_timer_isr; // PieVectTable.EPWM3_INT = &epwm3_timer_isr; EDIS;

EALLOW;

SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Stop all the TB clocks EDIS;

InitEPwm1Example(); // InitEPwm2Example(); // InitEPwm3Example();

EALLOW;

SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; EDIS;

EPwm1TimerIntCount = 0; EPwm2TimerIntCount = 0; EPwm3TimerIntCount = 0;

IER |= M_INT3;

PieCtrlRegs.PIEIER3.bit.INTx1 = PWM1_INT_ENABLE; // PieCtrlRegs.PIEIER3.bit.INTx2 = PWM2_INT_ENABLE; // PieCtrlRegs.PIEIER3.bit.INTx3 = PWM3_INT_ENABLE; EINT; // Enable Global interrupt INTM ERTM;

for(;;)

{

asm(\ NOP\ } }

void InitEPwm1Example() {

EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;//zhuyi EPwm1Regs.TBPRD = 1500; //载波周期=2*1500TBCLK EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0 EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW; EPwm1Regs.TBCTR = 0x0000;

EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up down EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading

EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;

EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO_PRD

EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD; EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD;

EPwm1Regs.CMPA.half.CMPA =1000;

EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Clear PWM1A on CAU EPwm1Regs.AQCTLA.bit.CAD = AQ_SET;

EPwm1Regs.AQCTLB.bit.CAU = AQ_SET; // SET PWM1B on CAU EPwm1Regs.AQCTLB.bit.CAD = AQ_CLEAR;

//set dead band

EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_PRDZERO; //? Select INT on Zero Prd event

EPwm1Regs.ETSEL.bit.INTEN = PWM1_INT_ENABLE; // Enable INT EPwm1Regs.ETPS.bit.INTPRD = ET_1ST; }

interrupt void epwm1_timer_isr(void) {

EPwm1TimerIntCount++;

if( EPwm1Regs.TBCTR==1500) { k=0; N=fz/fr;

Tc=1/fz;

TonC1=Tc/4*(1+M*sin(k*PI/N)); k+=2; if(k>(2*N-2)) { k=0; }

EPwm1Regs.CMPA.half.CMPA = TonC1;

// EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Clear PWM1A on CAU // EPwm1Regs.AQCTLA.bit.CAD = AQ_SET;

// EPwm1Regs.AQCTLB.bit.CAU = AQ_SET; // SET PWM1B on CAU // EPwm1Regs.AQCTLB.bit.CAD = AQ_CLEAR; } else { k=1; N=fz/fr; Tc=1/fz;

TonC2=Tc/4*(1+M*sin(k*PI/N)); k+=2; if(k>(2*N-1)) {

k=1; }

EPwm1Regs.CMPA.half.CMPA = TonC2;

// EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Clear PWM1A on CAU // EPwm1Regs.AQCTLA.bit.CAD = AQ_SET;

// EPwm1Regs.AQCTLB.bit.CAU = AQ_SET; // SET PWM1B on CAU // EPwm1Regs.AQCTLB.bit.CAD = AQ_CLEAR; }

// Clear INT flag for this timer EPwm1Regs.ETCLR.bit.INT = 1;

// Acknowledge this interrupt to receive more interrupts from group 3 PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; }

#include \\\Include File

#include \\\DSP280x Examples Include File

void InitePWM(void) {

EALLOW;

EPwm1Regs.TBPRD = 600; // Period = 601 TBCLK counts EPwm1Regs.CMPA = 350; // Compare A = 350 TBCLK counts EPwm1Regs.CMPB = 200; // Compare B = 200 TBCLK counts EPwm1Regs.TBPHS = 0; // Set Phase register to zero EPwm1Regs.TBCTR = 0; // clear TB counter EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;

EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Phase loading disabled

EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;

EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;

EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // TBCLK = SYSCLK EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1; EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR = Zero

EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR = Zero

EPwm1Regs.AQCTLA.bit.PRD = AQ_CLEAR; EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; EPwm1Regs.AQCTLB.bit.PRD = AQ_CLEAR;

本文来源：https://www.bwwdw.com/article/fzlv.html