Design_Spec_template

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I. Functional Description

(Algorithm overview and description; missions and tasks of the module)

II. Module Micro-architecture

(A very detailed section; put as many details as possible; should be a heavy section)

(A) Design Requirements

(B) Block Diagrams and Description

(Block diagram – in hierarchical form for complicate designs)

(Describe what each block does; and the thoughts how and why it is micro-architected so)

(C) State Machine Diagram and description

(Major state diagrams in your design, and describe/explain the states and branch conditions associated with them)

III. Register Map

(A) Address Range

(B) Register Description

IV. File Structure and Module Hierarchy

(Tabulate modules in each .v file and sub-smodule dependency for module hierarchy.) (Brief description of each module – what the module does.)

V. Top I/O Ports and Description

(A) Inputs

(Input pins including bit width and brief description)

(B) Outputs

(Output pins including bit width and brief description)

VI. Macrocell List and Flip-Flop Registers

(A list of all SRAM, RF, ROM cells, including information pertinent to the cells) (A list of all IPs licensed from outside, including information pertinent to the IPs) (Total number of flip-flop registers in each clock domain)

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VII. Timing Diagram

VIII. Functional Verification

(How is the test bench set up? – including how to clone external components used with your design in verification)

(What test cases need be verified? Description of test cases and verification status) (What is supposed to be verified and is not verified? Why?)

IX. Performance Related

(For example, how many cycles to process I, P, B frames? …. etc.) (Clock requirements: how fast is the clock?)

(Combinational, noncombinational, memory area report from synthesis – including synthesis library and environment setup)

Appendix A: Asynchronous design

(if applicable)

Appendix B: Built-in test logic

(if applicable)

I. Functional Description

I2S is a synchronous data transmission scheme for audio PCM. Each I2S channel carries 2 channels of audio data. The I2S signal is shown in Fig. I.1. It consists of 3 pins: bit clock, word clock, and data bit. Each bit clock cycle represents a data bit, and each word clock cycle signals two words each of which represents the PCM value of an audio channel.

The purpose of the module i2s is to capture the audio PCM data from the I2S input ports, and write the captured data to external SDRAM via an internal SDRAM controller. It will also interrupt an on-chip CPU every time when a programmable number of audio samples are captured. In addition to compliant I2S signaling (in Figure 1), the module i2s can also capture pseudo-I2S signal where word clock is deviated from the nominal by 1 bit clock cycle and/or data bit order is reversed (least significant bit first).

……….

II. Module Micro-architecture

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(A) Design Requirement

The audio sampling rate ranges from 32 kHz to 192 kHz, and the number of bits per sample (word) from 12 bits to 32 bits. Therefore the bit clock is as high as 192k x 32 x 2 = 12.288 MHz, and as low as 32k x 12 x 2 = 768 kHz. The i2s module is required to deal with all cases.

To facilitate audio processing after audio samples are captured, the audio samples are stored in separate left and right buffers in SDRAM where each sample (word) is 32 bits/word.

The module is required to begin to capture the next available complete left channel sample after it is notified by CPU. No incomplete audio sample is allowed to store in SDRAM.

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(B) Block Diagram and Description

The top-level block diagram is illustrated in Figure II.1. The i2s_capture is a block that captures the audio PCM data by using bit clock as the capturing clock and creates a control signal when a word is completely captured. The i2s_control is a block that performs cross clock domain synchronization of the control signal from i2s_capture and …….

The i2s_capture is described in Figure II.2. …………

The i2s_control is illustrated in Figure II.3 …………

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(C) State Machine Diagram and Description

Shown in Figure II.4 is the state diagram used for audio sample capture. The state is increased by 1 after capturing a bit. When the channel transition strobe is asserted, the state is back to initial state. …….

In module i2s_control, the state diagram that is used to process the SDRAM services into left and right channel buffers of the SDRAM is shown in Figure II.5. The state is out of idle state when the number of audio samples in the internal SRAM buffer reaches to ½ full………..

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III. Register Map

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(A) Address Range: 32’h00000000 – 32’h00000007 (8 addresses)

(B) Register Description

IV. File Structure and Module Hierarchy

The design consists of 7 files which contain the modules as follows:

i2s_top.v: i2s_top i2s_capture.v: i2s_capture i2s_control.v: i2s_control i2s_ramctl.v: i2s_ramrdctl i2s_ramwrctl i2s_ram.v: i2s_ram_wrap

RF2SH16x64

i2s_umacreq.v: i2s_umacreq i2s_cpuint.v: i2s_cpuint

The module i2s_top is the top module that instantiate all modules in the table as follows. The module i2s_capture captures the audio PCM data for both left and right channels. A bit is captured at the positive edge of the bit clock. When the number of audio samples reaches to a preset value, a signal flag is raised and passed to i2s_control for further processing in the system clock domain. The module i2s_control controls …….

The module hierarchy is shown in the following table:

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V. Top I/O Ports and Description

(A) Inputs clk // system clock reset_ // hard reset; low assertion bitclk // audio bit clock adatain // audio data bit wdclk // audio word clock [31:0] regaddr // address for registers

[31:0] regdatain // data input from register bus regwen // write enable for registers

umac_i2s_ack // acknowledgement from umac to i2s for DDR2 service cpu_i2s_ack // acknowledgement from cpu to i2s for interrupt service ……………

(B) Outputs i2s_cpu_interrupt // interrupt signaling from i2s to cpu [63:0] i2s_dram_data // write data from i2s to DDR2 i2s_umac_req // DDR2 service request from i2s to umac …………

VI. Macrocell list and Flip-Flop Registers

(A) Macrocells (B) Flip-Flop Registers

bitclk: 208 clk: 1099

VII. Timing Diagrams

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(Paste from your simulation waveforms)

VIII. Functional Verification

The test bench contains an instance of module i2s_top and a clone (i2s_master) of ADC that outputs bit clock, word clock, and data bit. Parameters can be set in the i2s_master to output various audio sampling frequencies, bits per word, and signal types for maximum verification coverage. A mechanism that automatically checks the audio PCM values when those samples are outputted to DDR2 data bus is built in. Necessary data files for verification are generated beforehand using a C-program. The testbench then reads the data files, creats input signals to i2s_top, and checks against the outputs from i2s_top at the appropriate cycle timings.

Test cases from all possible combinations of 12, 16, 20, 24, 32 bits/sample, 32, 44.1, 48, 96, 192 kHz sampling rate are created, resulting in a total of 50 cases. In each test case, the number of samples is equal to 2**min{bits/sample, 24} for each left and right channels. The values in the adjacent samples are incremented or decremented in a systematic way. The simulation results show that the design can deal with all these test cases correctly; there is no mismatch at the check points.

In the test bench, the register values which suppose to be set by CPU are forced to desired ones. The true interface functions with CPU are not verified until it is integrated with CPU and firmware. Nevertheless, a simple separate test shows that the read and write mechanism functions correctly when register address values over the register address bus belong to the module.

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IX. Performance Related

From the simulation, the cycle count (based on the clk) per capture of 8 samples is xxx.

The design is synthesized with clk=250 MHz, bitclk=500 kHz, clk uncertainty=0.2 ns, bitclk uncertainty=5ns, using the UMC 90 nm library XXXXX and ARM memory compiler YYYY. The resulting combinational and non-combinational areas are xxxx and yyyy, respectively. The memory area for the two register files in the design is zzzz. …….

Appendix A: Asynchronous design

There are two clocks in the design; one is bitclk and the other clk. A control signal xxxx is created based on bitclk in the i2s_capture module. The control signal is then synchronized with 3 stages of flip-flops in clk domain. A one clk cycle long strobe yyyy is then created and used for all functions in clk domain as shown in Figure A.1.

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……….

Appendix B: Built-in test logic

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