王曦英文翻译最终版

沈阳航空工业学院毕业设计论文

PROGRAMMABLE LOGIC CONTROLLER

ABSTRACT

Industrial automation is the now vital for its prosperity, since it reduces the production cost many folds and also increases productivity. For this purpose WLC (i.e. Wired Logic Controller) was introduced in 60s-70s. It was the first step in the industrial automation. Later on microcontrollers were introduced which had the advantage of greater flexibility over the WLC. With the evolution of technology, a very sophisticated version of a controller was introduced with a very large I/O handling capability and extreme flexibility called the Programmable Logic Controller, commonly called the PLC.

The PLCs are not alien to the industries of Pakistan. They have been around for quite a long period and are being employed extensively. Even though the demand of this product is considerable here, there has been no effort to develop it indigenously. Since there had been no development in this field in our country and being a requisite of the nation, so as an exercise of Logic Design, Digital Electronics, Interfacing and Software Engineering. As part of our coursework, we have to undertake a project in the final semester. This article describes the design and implementation process of a Programmable Logic Controller (PLC), in that connection. The task was undertaken as an exercise in digital circuit design, microcontroller application and interface since we already had taken up projects related to power and analog electronics in preceding semesters.

Keywords: Programmable Logic Controller (PLC), Automation, Microcontroller Applications, Industrial Electronics, Digital Control, On-Off Control, Digital Electronics

1. INTRODUCTION

1.1 PROBLEM DESCRIPTION

We all know that industrial automation is the backbone of a nation for its prosperity since, it reduces the production cost many folds and also increases productivity. For this purpose WLC (i.e. Wired Logic Controller) was introduced. It was the first step in the industrial automation. Later on microcontrollers were introduced which had the advantage of greater flexibility over the WLC.

Eventually, a very sophisticated version of a controller was introduced with a very large I/O handling capability and extreme flexibility called the Programmable Logic Controller, commonly called the PLC. Siemens introduced many series of controllers with different capabilities. One of the first series was the SIMATIC? 5 Controllers. The PLC available to us is the S5-100U-100. Later on Siemens introduced the SIMATIC? 7 series of controllers and now, we also have the S7-314IFM PLC.

The PLCs are not alien to the industries of Pakistan. They have been around for quite a long period and are being employed extensively. Even though the demand of this product is

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沈阳航空工业学院毕业设计论文

considerable here, there has been no effort to develop it indigenously. Since there had been no development in this field in our country and being a requisite of the nation, so as an exercise of Logic Design, Digital Electronics, Interfacing and Software Engineering, we undertook this task of making a PLC better than the S5 controllers and comparable to some extent to the S7 controllers. The PLC that we have designed can also be upgraded to support Remote Data Acquisition.

1.2 BLOCK DIAGRAM AND BRIEF DESCRIPTION

The complete general block diagram of the PLC is depicted in Fig.1-1. Just like the SIMATIC? 5 systems, our PLC can also be broadly classified into three distinct units:

a. CPU

b. Bus unit, and

c. Modules (I/O and function)

Fig.1-1 Block diagram of the PLC

Each unit can be discussed as follows:

1.2.1 CPU

The CPU, as the name suggests, is the brain of the PLC system. Without its brain, the PLC

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沈阳航空工业学院毕业设计论文

simply cannot function.

In our system, the CPU comprises of two ATMEL? 89C52 microcontrollers. As in every multi processor system, one is the master and the other is the slave. The functions performed by the master or the controlling unit (Fig.1-1) can be summarized as follows:

??Monitor and control the operating modes of the PLC using the operation controls. ??Configure the PLC modules.

??Check program integrity by monitoring scan cycles.

The slave microcontroller (executing unit, Fig.1-1) functions to run the user program. It is responsible for:

??Taking the appropriate actions during startup.

??Issuing the CONVsignal at the start of every scan cycle and the subsequent addressing and transaction of data with the modules. ??Handling the counters and timers.

The CPU section also has the responsibility of communicating the programming device i.e. the computer through a serial port. The communication channel works according to the semaphore algorithm (commonly known as token algorithm). It is to be noted here that the communication link currently does not function, as mentioned earlier, because it was a part of the planned GUI, which has not been implemented due to the constraint of time.

1.2.2 BUS UNIT

The bus unit functions similar to the motherboard in a computer. The bus unit that we have constructed holds up to 4 modules and the CPU; we named it the main bus unit. Moreover, the bus unit also carries the extension connector by which other bus units can be cascaded to increase the I/O handling capability of the PLC. The bus units that will be cascaded will not have a slot for connecting the CPU; only modules can be connected.

The main function of the bus unit is to buffer all the signals i.e. the data buses, address buses, and the control signals, to eliminate the loading of the CPU. This function is also performed by the main bus unit but this also performs an extra function during the configuration stage. The bus unit controller, see Fig.1-1, selects each slot one at a time so that it can be configured for the module connected in it and also sends a signal to the controlling unit when all the slots have been selected and configured once.

1.2.3 MODULES

The modules serve to provide the interface of the PLC with the plant to be controlled. The modules, which we had designed were digital input, digital output, analog input and analog output modules (verified using OrCAD? PSpice). But we only managed to manufacture the digital input and output modules, each capable of handling 16 devices. The standards of the modules are similar to that of commercially available modules.

The modules are equipped with an address decoder circuit, which is common in all the modules, as the circuit has been designed to support auto configuration.

1.3 POSSIBLE SOLUTIONS

Now that the overview of the project is present before us, we will take a look into the

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沈阳航空工业学院毕业设计论文

possible solutions that came to our mind when we commenced brainstorming. The ideas can be listed as follows along with their supporting and disagreement comments.

??Use of a single processor/microcontroller was the first idea that came to mind

because it was most simple and easy to implement. The problem with such an idea was that we were striving for a good scan time due to which we needed a fast processor (which was unavailable) or had to go for multiple processors.

??The use of microprocessor instead of a microcontroller was also among the options because we have been taught the assembly language of this processor and we were well aware of it. The drawback of such a selection was that in a PLC, bit operations are plenty while the microprocessor instruction is not very powerful for such operations.

??Using a 16-bit microcontroller for ease of work was a great idea but its materialization was not possible as it was not available here.

??After all these options, we were left only with the option of using two microcontrollers in tandem to achieve our desired task.

1.4 REASONS FOR SELECTION

Of all the above solutions mentioned above, we decided to implement the multi processor CPU with the bus unit scheme for connecting the modules. The advantages, which also form the reasons for the selection of this design, are enumerated below.

??This solution was the first seemingly feasible solution that came to our minds. During the course of work, many more came but then it was too late.

??The design was based on equipment and technology easily available in our city.

??The use of microcontroller instead of a microprocessor is justified by the fact that the microprocessor is incapable of bit operations, which are numerous in a PLC.

??A fast microcontroller was unavailable hence we decided to distribute the work load and run tasks simultaneously by using two controllers so that the speed is not compromised.

??The auto configuration feature allows the design of the modules to be quite generic as the address decoding section is identical hence ensuring ease of manufacture.

??The use of the bus unit allows cost effectiveness as specialized circuits in each module are not required as found in the SIMATIC? 7 controllers.

2. ANALYSIS AND SIMULATION

Since our system is a digital system based on microcontrollers, it was not possible to obtain its mathematical model. Instead, we have simulated our circuit design with all the real life limitations in OrCAD? 9.1 PSpice. The computer hardware simulation results and their analysis are discussed below.

2.1 COMPUTER SIMULATIONS - HARDWARE

The simulations were carried in different stages; the auto configuration process, in which the control word is read and then the appropriate address, is assigned to the module. Once this was tested, the complete sequence of reading data from a digital input module was tested. Similarly, the sequence of writing to a digital output module was also tested.

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沈阳航空工业学院毕业设计论文

Before discussing the processes, one thing that must be stressed is that the signals used for testing the performance of the circuits were constructed using actual timing delays that would be introduced by the microcontrollers. All the propagation delays, pulse widths, etc. have been carefully implemented so that our simulations are as near to practical results as possible.

2.1.1 THE AUTO CONFIGURATION PROCESS

The configuration cycle is handled purely and solely by the second microcontroller. It is the job of this controller to read the control words of the various modules and then assign addresses to each. The process is carried out as follows.

Whenever the PLC is switched ON, the microcontroller will carry out the configuration cycle. To initiate this cycle, the microcontroller sends an active low signal PSENpulse. At the first rising edge of the CLK, this low state is transferred to P0, the signal for selecting the module at the first slot. Meanwhile, PSENnow goes back high. Now the microcontroller sends out A1A0=00, which causes the control word to be addressed. Hence when the RDsignal goes low, the control word of the module at the first slot is read and stored in the RAM of the microcontroller. Now the next module is selected on the next rising edge of the clock. Similarly, its control word is read and stored. Once a bus unit has been completely checked, it raises a flag bit. This flag bit of each bus unit is ANDed with the flag bit from the next bus unit (i.e. NBUS) and the output of the AND gate goes to the input of the preceding bus unit. This chain continues until the output of the final AND gate goes to the microcontroller. This output goes high when all the modules have been selected once and their control words have been read.

Figure 2.1

The timing diagram shown below depicts the sequential selection of each module and the reading of their control words. Also note that the BU_END signal goes high when all the modules have been read.

Now the microcontroller reads all the stored control words and overwrites them with proper addresses, each 16-bit long. Once all the control words are converted to addresses, these are to be transferred to the modules. Hence, once again, the PSENgoes low and on the first rising edge of the clock, the first module is selected. However, this time the microcontroller sends out A1A0=10, which indicates that the lower byte of the address latch is being pointed to. Then the lower byte of the address appears on the data bus of the microcontroller and when the WRsignal goes low, the address latch latches the data. Once lower byte has been written, the microcontroller sends out A1A0=11, which shows that the high byte is being addressed. Again, the high byte is transferred to the address latch when WRgoes low. This completes the auto configuration for one module. In a similar manner, all the remaining modules are configured, as

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沈阳航空工业学院毕业设计论文

each is selected one by one on successive rising edges of the clock. The addressing assigning process is depicted in the following timing diagram.

Figure 2.2

2.1.2 CONTROL WORD

To implement this feature, it was necessary that the modules were able to ?tell? who they are. This was done by using unique 8-bit control words for each module. These control words are constant for a given type of module and built into the modules during their creation. The bit format of the control word is given below.

By reading this control word, the microcontroller is able to recognize the module and then assign an address to it. The control word for any module can be constructed using the following table.

Table 2.1: Configuration control word

2.1.3 ADDRESSING THE MODULES

Since the addressing of each module will be the same, this section has been separated, as it will be common to all the modules.

The addressing of the modules will begin once the configuration cycle has been completed and the user program has been downloaded to the main microcontroller. It will be this microcontroller, which will be responsible for addressing the modules and making them perform according to the user program. Moreover, the user need not be worried about the addresses of the modules because the addresses will be handled by the microcontroller; he will simply have to use the normal syntax, as in other PLCs.

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沈阳航空工业学院毕业设计论文

Any module is addressed in one machine cycle using the microcontroller?s external memory mode. When the address is completely placed on the address bus, the 16-bit equality comparators of each of the modules compare this address with their assigned address. If it matches their address, a CSsignal goes low and access to the remaining module is permitted.

The timing waveform shown below shows a digital input module being decoded at 13Eh –13Fh address.

Figure 2.3

2.1.4 DIGITAL INPUT MODULE

As illustrated by the control words, a digital input module could have eight, sixteen or thirty-two inputs. The module that we simulated is a 16- input module. The input voltage standards are maintained from those of the industry i.e. 13-24 V represents logic high. The industry standards are converted to TTL levels by the use of optoisolators, which also isolate the following circuits from the high voltage side.

Accessing the Module

The address of the module is decided in the auto configuration stage after reading the control word and the user need not be worried about it.

Figure 2.4

The 16- input module is decoded at two addresses; one for the lower byte and the other for the higher byte. The CONVsignal, from the main microcontroller causes the two latches at the input stage to latch the present status of the inputs simultaneously. Now when we read from the lower address (i.e. A0=0), we are reading the lower eight inputs while reading from the next address (i.e. A0=1), we get the status of the higher eight inputs. So a digital module with 16 inputs is read in two cycles while a module with 32 inputs would require four cycles.

2.1.5 DIGITAL OUTPUT MODULE

Similar to the input module, a digital output module could have eight, sixteen or thirty-two outputs. The module that we simulated is a 16-output module. The output voltage standards are once again maintained from those of the industry i.e. 24 V represents logic high. The module is isolated from the plant by the use of opto- isolators at the outputs and the industry standard is obtained by the use of opto- isolators.

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Accessing the Module

Once again, the 16-output module is decoded at two addresses; one for the lower byte and the other for the higher byte. However, here the sequence of events is the reverse of what it was for the input module.

Figure 2.5

After the decisions have been taken according to the user program, the logic states are transferred to the output module in two cycles. First the lower byte is written to the output latch by using the lower address and then the higher byte is written to the latch. Once this has been done, the CONVsignal appears and all the states are transferred to the output latches simultaneously. This cycle is repeated in every scan cycle monotonously.

2.1.6 ANALOG INPUT MODULE

The analog module that we simulated is an 8-channel 12-bit signed output module. The MAX120 ADC used for converting the analog voltages to digital provides 500 kilo samples per second and hence a conversion time of 2 μsec including tracking time. It has an internal–5.0 V reference.

The differential input voltage is limited to ± 5V by the use of a voltage divider at every input, as this is the limit of the ADC. The input voltages and their respective references are multiplexed using analog multiplexers. The differential inputs to be converted are selected by a sequential circuit (implemented in a PLD) and are applied to the two inputs of a unity gain differential amplifier. The differential output voltage is passed to the MAX120 for conversion.

Accessing the Module

When a user program is downloaded to the main microcontroller, in which analog inputs are being used, the microcontroller first figures out which inputs are to be converted and according to it, it creates a control word that would be sent to the analog module. This control word is written to address, which was assigned to the module. The sequential circuit interprets the control word, selects and converts the proper input and transfers it to latches from where it is read by the microcontroller.

Although we did manage to successfully simulate the module but constraint of time and facilities forced us to give up its implementation.

2.1.7 ANALOG OUTPUT MODULE

The analog output designed by us is also an 8-channel 12-bit signed module. The MX7547DAC used at the output provides a good conversion time of 2 μsec. The output of each channel is equipped with a track and hold buffer circuit to prevent loading of the DAC.

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沈阳航空工业学院毕业设计论文

Accessing the Module

Just like a control word was required to access the analog input module, a similar control word generated by the microcontroller is required for accessing the output module. This control word will be used by a sequential circuit to determine which outputs are to receive the following data.

Once this control word is send at the beginning of the user program, on its turn, the address of the output module is sent out. Then the data for the various channels is sent one after the other. The channel to which the data goes is governed by the logic circuit implemented in the PLD. The logic circuit works as a controlled FIFO, as it transfers the incoming data to the outputs starting at the first and proceeding to the last. However, the data goes only to those channels, which were referred to in the control word. As the DAC is very fast, there are no

serious timing problems.

Although we did manage to successfully simulate the module but constraint of time and facilities forced us to give up its implementation.

3. CONCLUSION

In a nut shell, the whole exercise of designing the PLC and then implementing it was a thorough learning experience, although one with a heavy price tag. There is no denying that the project was too long to be taken as a final year project and our teachers should have prevented us from taking such a task but, alls well that ends well. There were many positives to come out of this whole exercise which may be enlisted as follows:

1. The enormity of the project taught us the art of dividing a big task into several small ones so that it becomes easier to meet targets.

2. The use of OrCAD? Pspice? and Layout for simulation and artwork design became

known to us.

3. Designing of complex state machines and cumbersome combinational logics in PLDs was also something new. 4. By designing the PLC according to the computer?s design, we gained a brief insight into how computers are designed.

5. The project the served the purpose of teaching how to work as a team.

6. Our skills of recognizing bugs and then troub leshooting them came to the fore when we worked on the circuits.

7. The development of this PLC would certainly open doors for work to begin in this area to make our country self- reliant in this respect.

These were some of the many benefits that we gained out this coursework. But the project itself does not end here. Just like the commercially available PLCs, this one too has many prospective improvements and enhancements which can be taken up by succeeding batches. For example, the analog modules can be manufactured by someone as it has already been designed, and the instruction set can be made even more powerful by working on it. Hence the setup of this project can easily come in handy to encourage work in this direction.

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沈阳航空工业学院毕业设计论文

REFERENCES

Books Referred

??Siemens Statement List (STL) For S7-300 and S7-400 Programming Reference Manual

?Digital Fundamentals by Thomas L. Floyd ??Digital Design by Morris Mano

??Microprocessor and Interfacing by Douglas V. Hall

??Op-Amps and Linear Integrated Circuits by Ramakant A. Gayakwad ??Operational Amplifier Characteristics and Applications by Robert G. Irvine ??The 8051 Microcontroller by I. Scott McKenzie Web Sites Visited ??www.8052.com ??www.laticesemi.com ??www.atmel.com ??www.maxim.com

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可编程序逻辑控制器

摘要

在目前，工业自动化对工业的繁荣是极其重要的，因为它减少了许多生产成本折扣并且提高了生产率。出于这个理由，在60、70年代 WLC （即布线逻辑控制器）被引进，这是工业自动化的起步。后来，微控制器的引用，使微控制器在更大的适应性方面占有更大的优势。随着技术的发展，一种更先进的控制器被采用，它具有强大的I/O处理能力和很大的灵活性，它就是可编程序逻辑控制器，通常成为PLC。

PLC对于巴基斯坦的工业并不是陌生。这已经是很长一段时间了，现在它在被广泛的应用。尽管这个产品的需求在这里相当可观，但是它在本土的发展并没有得到很大成就。之后，在我国这个领域PLC并没有很好的发展，而现在它作为逻辑设计、数字电子学、接口设备和软件工程的实训正成为国民的必须品。作为我们课程工作的一部分，我们不得不承担一个最后学期的项目。在这方面，本文描述一种可编程序逻辑控制器（可编程逻辑控制器）的设计和实现过程。任务是承担一个在数字电路设计，微控制器应用和接口设备，因为在学期之前，我们已经开始学习了与这个项目相关的功率和模拟电子学。

关键字：可编程序控制器（PLC），自动化，微控制器应用，工业电子学，数字控制，开关控制，数字电子学

1. 绪论

1.1 问题描述

我们知道，工业自动化是一个国家工业支柱，因为它的繁荣减少了生产成本许多折扣并且提高了生产率。由于这个原因， wlc（即布线逻辑控制器）被引进。后来，微控制器被引用，它与布线逻辑控制器相比强大的适应性使它占有更大的优势。随着技术的发展，一种更先进的控制器被采用，它有强大的I/O处理能力和很大的灵活性，它就是可编程序逻辑控制器，通常成为PLC。西门子推出许多具有不同的能力的系列控制器。第一个系列是SIMATIC?5控制器。我们现有的可编程控制器是S5-100U-100，后来，西门子推出了SIMATIC?7系列可编程控制器，现在我们使用S7-314IFM PLC。

PLC对于巴基斯坦的工业并不是陌生。这已经是很长一段时间了，现在被广泛的应用。尽管这个产品的需求在这里相当可观，但是它在本土的发展并没有得到很大成就。之后，在我国这个领域并没有很好的发展，而现在PLC作为逻辑设计、数字电子学、接口设备和软件工程的实训正成为国民的必须品。我们承担开发一种可编程控制器的任务，这种可编程序控制器要比SIMATIC?5控制器更好，可与SIMATIC?7控制器相媲美。我们设计的PLC也可以提高到支持远程数据采集。

1.2 结构图和摘要描述

图1-1是完整的、综合的PLC结构图。正像SIMATIC?5系统，我们的可编程逻辑控制器可以大致地分为三性质不同的单元： a.CPU（中央处理器） b.总线单元

c. 功能块(I/O和功能)

图1-1 可编程序控制器方框图

各个单元可以被描述如下:

1.2.1 CPU

CPU,正像它的名字表露的,是PLC系统的大脑,没有了大脑PLC不能执行简单的功能。在我们的系统中，CPU是由两个ATMEL?89C52微控制器组成。正如在每个多处理系统中，一个是主控制器，另一个是从属控制器。主控部分或者是控制单元（图1-1）形成的功能可以概括如下：

·利用操作控制监视与控制可编程逻辑控制器的工况

·配置可编程逻辑控制器功能块

·由监视器扫描循环数检查程序的完整性从属控制器（执行单元，图1-1）是执行 用户程序。它主要负责：

·在启动期间做适当的动作

·在每个扫描周期开始，提供转换器信号以及连续的地址和具有功能块的处理数据

·处理计数器和时间继电器

中央处理器部分也有通讯编程装置的能力，例如：计算机通过串行端口。通信通道的工作是按照信号量算法（通常称为标记算法）。当前通讯连接没有起作用将被标记在这，如前述，因为它过去是计划的图形用户界面的一部分，由于时间的限制它没有实现。

1.2.2 总线单元

总线单元功能类似于一个电脑的主板。总线单元有支持4个功能块组合和中央处理器；我们称为主要总线单元。此外，总线单元也承担着连接器的扩充，通过它其他的总线单元可以增加PLC的I/O处理能力。总线单元对于连接中央处理器不是一个小口；只有功能块可以连接。

总线单元的主要作用是缓冲全部信号，比如：数据总线、地址总线，以及控制信号，消除 CPU的承载。这些功能不但被主总线单元执行，而且在配置阶段也执行一个额外的功能。图1-1，总线控制器，每次只选一个口以便能够使模块连接在上边，也可以在所有的口被选择和配置的时候发一个信号到控制单元。

1.2.3 功能块模块

功能块模块是用来提供PLC人机接口设备。我们设计的功能块具有数字输入、数字输出、模拟输入和模拟输出功能块模块（用CAD?Pspice）。但是，我们只能够制造数字输入、数字输出功能块每个都可以处理16位装置。功能块的规格标准类似于市场上可以买到的组件。

这些功能块模块是具备地址译码器的电路，它在所有功能块中是很常见的，因为这个电路已经设计成为支持自动化的结构。

1.3 合理的解决

既然项目概况在之前已经介绍了，现在看一下我们想到的独创性合理解决方案，这些思想和他们的支持和意见不同的评论。

·使用单个信息处理机／微控制器是出现在我脑海里的最初想法，因为它能很简单、容易地完成。这个想法的问题是因为我们需要一个更快的处理器努力谋求一个好的扫描时间（它是不能利用的）或者是一个多处理系统。

·微处理器代替微控制器也是任意选择的，因为我们之前已经学习过汇编语言，而且有很好的了解。这种选择的缺点在于PLC，位操作会很多，而这时微处理机指令对于这样的操作并不是很强大。

·利用16位微控制器考虑便于工作，这是一个很好的想法，但是在实际中并

不能可以利用。

·最终，在这些选择中保留的是利用两个微控制器一前一后地完成我们的要求任务。

1.4 选择的理由

正如上述提及的解决办法，我们决定实施多信息处理机中央处理器具有的总

线单元策划连接功能块。下边列举了优点，也是形成选择这个设计的理由。

·这个解决办法是我们首先想到的似乎合理的办法。在工作过程中，也有很多想法产生，但那时已经很迟了。

·这个设计是基于我们城市可以很容易利用的技术和设备。

·微处理器代替微控制器的应用证明微处理器不能解决二进制运算，这些在PLC中有很多。 ·单个处理速度很快的微处理器是不可以用的，因此，我们由两个控制器同时地分配工作负荷和支配任务，避免牺牲处理速度。 ·自动化的结构特点允许功能块的设计相当普通。

·总线单元的使用考虑到成本效益特别是作为每个功能块的专业化模块，而在SIMATIC?7控制器中找到的并不是需要的。

2. 分析和仿真

因为我们的系统是一个以微控制器为基础的数字系统，获得它的数学模型不

是不可能的。相反，我们已经模拟我们的电路设计，尽管现实寿命限制在OrCAD?9.1PSpice。计算机硬件仿真结果和他们的分析将在下文中论述。

2.1 计算机仿真——硬件

计算机这个仿真分几个不同阶段；在自动化配置过程过程中，控制字的读入和恰当的地址被分配到模块中。一旦这个经过试验，来自数字输入模块读出数据的完全结果是被试验过的。同样的，数字输出模块读出的数据也是被试验过。之前讨论的方法，有一点必须强调，用于测试线路性能的信号具备实际的定时延时，这可能被微控制器所采用。全部的传播延迟、脉冲宽度等等已经密切地实现,以便我们的仿真尽可能达到实际效果。

2.1.1 自动化配置过程

配置周期是由第二个微控制器完全的、单独的操控。这个模块的作用是读不同模块的控制字，然后给每个控制字分配地址。这个过程执行如下：

每当可编程逻辑控制器接通电源，微控制器将执行控制周期。为初始化这个周期，微控制器发送一个低电平有效的PSEN脉冲。开始的时候上升沿CLK时钟信号，这个低状态转移到P0，这个信号为了选择模块的第一个口。同时，PSEN回到高电平。现在微控制器发送A1A0=00，它使控制字到指定地址。因此当RD处于低电平，模块第一个口的控制字被读入，储存在微控制器的RAM中。在下

一个模块在下一个时钟的上升沿。与前者相同，这个控制字也被读进并且保存，一旦总线单元完成检查，它是一个标志位。每个总线单元的标志位与来自下一个总线单元（例如：NBUS）的标志位相“与”，“与门”的输出转到之前的总线单元的输入。这个连锁一直延续直到最后“与门\的输出到微控制器。一旦模块被选通的时候，这个输出将是高电平并且读入控制字。

图 2-1

如下显示的时序图描绘了个功能模块的选择顺序和它们控制字的读入。也要注意一点，但所有模块被读入BU_END信号变为高点平。

现在微控制器读取了所有存储的控制字并且改写了它们本身每个16位的地址。一旦所有的控制字转换成地址，它们将转到模块上。从此，PSEN脉冲再一次成为低电平并且在第一个时钟信号CLK的上升沿，第一个模块被选中。然而，这次微控制器发出A1A0=10，这个表明正在指向地址锁存器的低字节。然后，在微控制器的数据总线出现了低字节地址，此时WR信号为低电平，地址锁存器锁存数据。只要写入低字节，微控制器发出A1A0=11，这表明是在高字节地址。再一次，当WR信号为低电平高字节转到地址锁存器。这完成了一个模块的自动化结构配置。可以按类似方式，当连续的上升沿时钟信号选通每个模块，这样所有的模块都进行了装配。下面时序图是地址分配的过程，

图 2-2

2.1.2 控制字

要实现这个作用，模块应该能够“通知”它们是什么形式。每个模块采用独特地8位控制字。对于一个给定的功能模块，控制字是不变的，在这些控制字形成期间嵌入到模块中。控制字位格式如下图：

通过控制字的读取，微控制器可以识别模块并且分配地址。任何一个控制字都可

以利用下表形成，

表2-1控制字结构

2.1.3 地址模块

由于每个模块的地址是相同的，本部分单独说明，这对所有模块是共通的。一旦，配置周期完成，地址模块就开始工作，此时用户程序将加载在主微控制器上。这个微控制器将负责地址模块以及通过用户程序形成地址模块。而且，用户不必担心模块的地址，因为这个地址将会被控制器处理；它将会有简单的、正常的顺序列，也可以看作在别的PLC中。

在一个机器的工作周期中，任何一个模块利用微控制器的外部存储形式指定地址。当地址完全置在地址总线，每个模块的16位比较器对照这些地址给他们赋以地址。如果地址匹配，CS将为低电平并且可以通过余下模块。 下图所示时序波形是数字输入模块被译码在地址为：13Eh-13Fh处。

图 2-3

2.1.4 数字量输入模块

像控制字说明的那样，数字量输入模块可以是8位，16位，32位输入。在这里我们模拟16位输入模块。输入电压规格标准维持在工业的电压（例如：13-24V），它表示逻辑高电压。通过光电隔离把工业标准转换成晶体管-晶体管逻辑标准，也隔离了高电压一侧的电路。

入口模块

模块的地址是读入控制字之后，在自动配置阶段决定的，用户没有必要担心

这一点。16位输入模块被译码在二个地址，一个是高字节地址，另一个是低字节地址。来自主控制器的CONV信号，使输入阶段的两个锁存器同时锁存当前的输入状态。现在，当我们读来自低字节地址（例：A0?0），我们读低八位输入的同时读来自下一个输入的地址（例：A0?1），我们会得到高八位输入的状态。因此，一个16位的输入模块需要2个周期，而一个32位的输入模块需要4个周期。

2.1.5 数字输出模块

与数字输入模块一样，数字输入可以是8位，16位，32位。我们模拟模块的是16为输出模块。输出电压的标准是工业上（例如：24V）电压，它代表高电平。模块是通过输入端的光电隔离器隔离，标准电压是通过光电隔离器获得的。

入口模块

每次16输出模块被译码在二个地址，一个是高字节地址，另一个是低字节地址，然而，在这里产生的先后和输入模块的不一样。

图 2-4

我们设置好用户程序之后，在两个周期内逻辑状态转到输出模块。利用低地址把低字节锁存到输出锁存器，之后是高字节锁存。一旦锁存成功，CONV信号使输出阶段的两个锁存器同时锁存当前的输出状态。这个周期在每个扫描周期被单调地重复。

2.1.6 模拟量输入模块

我们模拟的模拟量模块是8通道、12位输出。MAX120 ADC用在输入端，它把模拟电压转换为数字量，提供每秒500K的采样，由此转换时间是2μs，它包括跟踪时间。它有内部-5V的参考电压。

利用一个分压器在每个输入端将电压限制在±5V，这是ADC要求的。输入电压和他们的各自的参考是利用模拟多路复用器多路传递的。被转换的微分输入是由一个时序电路（在一个可编程逻辑电路中实现）和被用于单位增益差动放大器的两输入端。微分输入电压达到了用与转换的MAX120。

入口模块

当用户将程序下载在主控制器上，采用模拟输入，微控制器首先算出转换和通过的输入值，创建一个可以发送到模拟量模块的控制字，选择转换一个恰当的输入，然后传到需要微控制器需要度读取的锁存器。

尽管我们想试着成功地完成这个模块，但是时间和设备迫使我们放弃它的完成。

2.1.7 模拟量输出模块

模拟量输出被设计成8通道、12位输出的模块。MX7547用在输出端，转换时间是2μs，每个输出通道配备一个保持缓冲电路是避免DAC的负荷大。

入口模块

正如，控制字在模拟量输入模块的要求，要想进入输出模块必须要微控制器产生一个相似的控制字。这个控制字通过一个时序电路决定哪个控制器接收数据。在用户程序的开始发送控制字，这样转下去，输入模块的地址被发送，来自各个通道的数据从一个地址传到另一个地址。

尽管我们想试着成功地完成这个模块，但是时间和设备迫使我们放弃它的完成。

3. 结论

简言之，尽管我们耗费了很多资金，但PLC整体设计与实现的作业是一个彻底学习的经验。不可否认此设计被看作是最后一年最长时间的设计，老师本该阻止我们的冒险，但是我们从开始坚持到了最后。整个练习过程中，收获了不少积极的东西，在下面列出：

1.巨大的工程教会了我们将大工程分割成一些小块，以便更容易地达到我们的目标。

2.对于仿真和图形设计，CAD?Pspice的运用和布局已经让我们所了解。

3.在可编程逻辑电路中，复杂的机器状况和笨重的逻辑组合的设计是新鲜的。 4.依据计算机设计的这个PLC使我们对如何设计计算机也有了简单地深入。 5.这个工程也教会我们了如何作为一个团队去工作。

6.这个PLC的研制，可能打开了我们在这个领域工作的大门，使我们可以在国家这个领域得心应手。

以上是我在这次课程任务中受益的方面，而不是工程本身。正如市场上可以买到的PLC一样，对于下一批次的PLC我们将开始进行预期的改善和提高。例如：模拟量模块会按照预期的设计大量生产，此外，指令系统会更加强大以便更好的辅助工作。

参考

参考书目

西门子S7-300 、S7-400编程手册 Thomas L. Floyd著.数字原理 Morris Mano著.数字设计

Douglas V. Hall著. 微处理器与接口设备 Ramakant A. Gayakwad著.放大器和线性集成电路 Robert G. Irvine著. 运算放大器特性和运用 I.Scott McKenzie著.8051控制器 访问过的网站 www.8052.com www.laticesemi.com

www.atmel.com www.maxim.com

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