DAC0832连接FPGA用查表法输出正弦波verilog程序

DAC0832

连接FPGA用查表法输出正弦波verilog 程序

module DAC0832(clk, data); input clk;

output [7:0]data; reg [7:0]data;

reg [17:0]count_10us; reg [1:0]delay; reg clk_10us; reg [5:0] n;

initial begin count_10us=16'd0; data=8'b00000001; delay=2'b00; n<=8'b0000000; end

always @(posedge clk) begin count_10us<=count_10us+1'b1; if (count_10us>18'd500) begin count_10us<=18'd0; clk_10us<=~clk_10us; end end

always @(posedge clk_10us) begin delay<=delay+1'b1; if (delay==2'b00) begin case (n) 6'b000000: 6'b000001: 6'b000010: 6'b000011: 6'b000100: 6'b000101: 6'b000110: 6'b000111: 6'b001000: 6'b001001: 6'b001010: 6'b001011: 6'b001100: 6'b001101: 6'b001110: 6'b001111: 6'b010000: 6'b010001: 6'b010010:

Page | 1/2 //64 point counter

//10us; The speed of DAC0832 is 1us

data<=8'h80;

data<=8'h8c; data<=8'h98; data<=8'ha5; data<=8'hb0; data<=8'hbc; data<=8'hc7; data<=8'hd1; data<=8'hda; data<=8'he2; data<=8'hea; data<=8'hf0; data<=8'hf6; data<=8'hfa; data<=8'hfd; data<=8'hff; data<=8'hff; data<=8'hff; data<=8'hfd;

end

endmodule

6'b010011: data<=8'hfa; 6'b010100: data<=8'hf6; 6'b010101: data<=8'hf0; 6'b010110: data<=8'hea; 6'b010111: data<=8'he3; 6'b011000: data<=8'hda; 6'b011001: data<=8'hd1; 6'b011010: data<=8'hc7; Page | 2/2 6'b011011: data<=8'hbc; 6'b011100: data<=8'hb1; 6'b011101: data<=8'ha5; 6'b011110: data<=8'h99; 6'b011111: data<=8'h8c; 6'b100000: data<=8'h80; 6'b100001: data<=8'h73; 6'b100010: data<=8'h67; 6'b100011: data<=8'h5b; 6'b100100: data<=8'h4f; 6'b100101: data<=8'h43; 6'b100110: data<=8'h39; 6'b100111: data<=8'h2e; 6'b101000: data<=8'h25; 6'b101001: data<=8'h1d; 6'b101010: data<=8'h15; 6'b101011: data<=8'h0f; 6'b101100: data<=8'h09; 6'b101101: data<=8'h05; 6'b101110: data<=8'h02; 6'b101111: data<=8'h00; 6'b110000: data<=8'h00; 6'b110001: data<=8'h00; 6'b110010: data<=8'h02; 6'b110011: data<=8'h05; 6'b110100: data<=8'h09; 6'b110101: data<=8'h0e; 6'b110110: data<=8'h15; 6'b110111: data<=8'h1c; 6'b111000: data<=8'h25; 6'b111001: data<=8'h2e; 6'b111010: data<=8'h38; 6'b111011: data<=8'h43; 6'b111100: data<=8'h4e; 6'b111101: data<=8'h5a; 6'b111110: data<=8'h66; 6'b111111: data<=8'h73;

endcase

n<=n+1'b1;

end

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