基于VHDL的交通灯设计与实现

华中科技大学

基于xilinx FPGA的VHDL交通

灯控制器的设计

--基于Spartan3E开发板

专业： 电子信息工程

一. 任务设计要求

① 设计一个十字路口交通信号灯的定时控制电路。要求红、绿灯按一定的规律亮和灭，

并在亮灯期间进行倒计时，并将运行时间用数码管/液晶显示出来。

②绿灯亮时，为该车道允许通行信号，红灯亮时，为该车道禁止通行信号。要求主干道每次通行时间为99秒，支干道每次通行时间为30秒。每次变换运行车道前绿灯闪烁，持续时间为5秒。即车道要由主干道转换为支干道时，主干道在通行时间只剩下5秒钟时，绿灯闪烁显示，支干道仍为红灯，以便主干道上已过停车线的车继续通行，未过停车线的车停止通行。同理，当车道由支干道转换为主干道时，支干道绿灯闪烁显示5秒钟，主干道仍为红灯。

③ 对红、绿灯的运行时间要能比较方便的进行重新设置。

④ 对器件进行在系统编程和实验验证。

⑤用VHDL语言对设计进行描述，设计一个测试方案，通过ISE对设计进行仿真验证。并能够下载到实验板上调试成功。

任务扩展：

在原设计的基础上加入指示方向的功能。

二. 系统设计

1.系统原理图与说明

由系统设计原理图，我以清楚地将系统分为六个模块：分频模块，时间设置模块，状态转换模块，时间计算模块，LED流水灯模块，LCD显示模块。 1）分频模块

分频模块其作用为：由于Spartan3E板上提供的时钟信号为50MHz，而设计所需时钟信号为1Hz，故使用分频模块将50MHz信号分频为1Hz信号。

2）时间置数模块

由于任务设计要求可以对主干道，支干道上左转、绿灯运行的时间进行重新设置调整，所以要对系统进行参数化设计。首先引入一组参数，main_gh，main_gl，main_lh,main_ll,branch_gh，branch_gl，branch_lh,branch_ll(下划线后面的字母分别取green,left,high,low首字母).需要置数时，首先选择对主干道还是支干道时间置数，这里设置一个main_or_branch参数，当main_or_branch为高时设置支干道时间，为低时设置主干道时间。置数时，通过s_set_button,l_set_button对时间进行设置，具体方法参见代码。为了置数方便，引入一个add_or_decent参数，低电平时按下button可以增计数，高电平时按下可以减计数。 3）状态转换模块

状态转化模块是整个系统的核心模块它控制整个交通灯系统的状态变化,整个过程划分为四个基本状态：主干道绿灯、主干道左转、支干道绿灯、支干道左转，用state、s_or_l为00、01、10、11来代表。每当一个状态的计数器为00时，state、s_or_l发生改变，以实现状态间的转换，进而控制交通灯的变化。 4）时间计算模块

这次设计中扩展了左转向的功能，因此红灯时间不仅仅是另一干道的直行时间，而是直行时间和左转时间之和。 5）LCD显示模块

Spartan3E板上只有LCD显示模块，所以采用此模块显示当前亮灯的剩余时间和设置时间模块的时间显示。通过输入

counterplay_1l,counterplay_1h,counterplay_2l,counterplay_2h四位二进制数，加上0011显示成十进制数，分别代表两位数的低位和高位

6）LED显示模块

由输入信号state、s_or_l、flash,分别取000，001，010，011，100,101,110,111所得到的main_green，main_left,main_red,branch_left,

branch_green,branch_red的不同值，来控制主干道，支干道红绿左转灯的亮灭。

其中 1表示亮，0表示灭。如表3-1 所示。

由上表可得到： main_green <= NOT(state) AND NOT(s_or_l) AND (NOT((flash AND clk))); main_left <= NOT(state) AND s_or_l AND (NOT((flash AND clk))); main_red <= state;

branch_green <= state AND NOT(s_or_l) AND (NOT((flash AND clk))); branch_left <= state AND s_or_l AND (NOT((flash AND clk))); branch_red <= NOT(state);

2.输入输出设计

任务设计开发板基于Spartan3E板，具体输入输出设定如下： 1）输入：

开关：main_or_branch：设置主干道还是支干道 EN： 使能信号 run_or_set： 设置运行模式还是时间设置模式 add_or_decent： 置数模式：增加或者减少 按键：s_set_button： 直行时间设置按键 l_set_button： 左转时间设置按钮 时钟：clk 2）输出：

LCD显示屏：分别显示当前亮灯的剩余秒数 LED灯：main_green,main_red,main_left

branch_left,branch_green,branch_red

3、状态转换图

S0状态：主干道绿灯、支干道红灯 S1状态：主干道左转、支干道红灯 S2状态：支干道绿灯、主干道红灯 S3状态：支干道左转、主干道红灯

S0Y时间为0？NN时间为0？S3YS1Y时间为0？NN

时间为0？YS2

三．各模块代码以及仿真波形

? 分频模块代码

波形仿真

分别给主干道，支干道个颜色灯持续时间赋值，再给定，当前亮灯的剩余时间，然后又进行仿真，结果符合预期

? LED模块代码

波形仿真

分别给予输入不同周期的高低点评，相互叠加的结果符合预期。

? LCD模块代码

library IEEE;

use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity LCD is port( clk : in STD_LOGIC; rst_n : in STD_LOGIC; counter_play1h, counter_play1l : in STD_LOGIC_VECTOR(3 downto 0); counter_play2h, counter_play2l : in STD_LOGIC_VECTOR(3 downto 0);

--degree1, degree2 : in STD_LOGIC_VECTOR(3 downto 0); SF_D : out STD_LOGIC_VECTOR(3 downto 0); LCD_E, LCD_RS, LCD_RW: out STD_LOGIC ); end LCD;

architecture behavior of LCD is type tx_sequence is (high_setup, high_hold, oneus, low_setup, low_hold, fortyus, done);

signal tx_state : tx_sequence := done; signal tx_byte : std_logic_vector(7 downto 0); signal tx_init : std_logic := '0'; type init_sequence is (idle, fifteenms, one, two, three, four, five, six, seven, eight, done);

signal init_state : init_sequence := idle; signal init_init, init_done : std_logic := '0'; signal i : integer range 0 to 750000 := 0; signal i2 : integer range 0 to 2000 := 0; signal i3 : integer range 0 to 82000 := 0; signal SF_D0, SF_D1 : std_logic_vector(3 downto 0); signal LCD_E0, LCD_E1 : std_logic; signal mux : std_logic;--???? type display_state is (init, function_set, entry_set, set_display, clr_display, pause, set_addr,

max_degree_1,max_degree_2,temperature_1,temperature_2,degree_1,degree_2,blank1,blank2,blank3);

signal cur_state : display_state := init; begin --LED <= tx_byte; --for diagnostic purposes --SF_CE0 <= '1'; --disable intel strataflash LCD_RW <= '0'; --write only --The following \ --when to transmit a command/data and when not to with cur_state select tx_init <= '0' when init | pause , '1' when others; --control the bus with cur_state select

mux <= '1' when init, '0' when others;

--control the initialization sequence with cur_state select init_init <= '1' when init,

'0' when others; --register select with cur_state select

LCD_RS <= '0' when function_set|entry_set|set_display|clr_display|set_addr, '1' when others; --what byte to transmit to lcd

--refer to datasheet for an explanation of these values

with cur_state select

tx_byte <= \ -- ??????? \ \ \ \ \ \ \ \ \ \ \ \ \ \ --main state machine

display: process(clk, rst_n) begin if(rst_n='0') then cur_state <= function_set; elsif(clk='1' and clk'event) then case cur_state is --refer to intialize state machine below when init => if(init_done = '1') then cur_state <= function_set; else cur_state <= init; end if; --every other state but pause uses the transmit state machine

when function_set => if(i2 = 2000) then cur_state <= entry_set; else cur_state <= function_set; end if;

when entry_set => if(i2 = 2000) then cur_state <= set_display; else cur_state <= entry_set; end if;

when set_display => if(i2 = 2000) then cur_state <= clr_display; else cur_state <= set_display; end if;

when clr_display => i3 <= 0; if(i2 = 2000) then cur_state <= pause; else cur_state <= clr_display; end if; when pause => if(i3 = 82000) then cur_state <= set_addr; i3 <= 0; else cur_state <= pause; i3 <= i3 + 1; end if;

when set_addr => if(i2 = 2000) then cur_state <= max_degree_1; else cur_state <= set_addr; end if;

when max_degree_1 => if(i2 = 2000) then cur_state <= max_degree_2; else

cur_state <= max_degree_1; end if;

when max_degree_2 => if(i2 = 2000) then cur_state <= blank1; else cur_state <= max_degree_2; end if; when blank1 => if(i2 = 2000) then cur_state <= temperature_1; else cur_state <= blank1; end if;

when temperature_1 => if(i2 = 2000) then cur_state <= temperature_2; else cur_state <= temperature_1; end if;

when temperature_2 => if(i2 = 2000) then cur_state <= blank2; else cur_state <= temperature_2; end if; when blank2 => if(i2 = 2000) then cur_state <= degree_1; else cur_state <= blank2; end if;

when degree_1 => if(i2 = 2000) then cur_state <= degree_2; else cur_state <= degree_1; end if;

when degree_2 => if(i2 = 2000) then cur_state <= blank3; else cur_state <= degree_2; end if;

when blank3 => if(i2 = 2000) then cur_state <=set_addr ; else cur_state <= blank3; end if; end case; end if; end process display; with mux select SF_D <= SF_D0 when '0', --transmit SF_D1 when others; --initialize with mux select LCD_E <= LCD_E0 when '0', --transmit LCD_E1 when others; --initialize --specified by datasheet transmit : process(clk, rst_n, tx_init) begin if(rst_n='0') then tx_state <= done; elsif(clk='1' and clk'event) then case tx_state is when high_setup => --40ns LCD_E0 <= '0'; SF_D0 <= tx_byte(7 downto 4); if(i2 = 2) then tx_state <= high_hold; i2 <= 0; else tx_state <= high_setup; i2 <= i2 + 1; end if; when high_hold => --230ns LCD_E0 <= '1'; SF_D0 <= tx_byte(7 downto 4); if(i2 = 12) then tx_state <= oneus; i2 <= 0; else tx_state <= high_hold; i2 <= i2 + 1; end if; when oneus => LCD_E0 <= '0';

if(i2 = 50) then tx_state <= low_setup; i2 <= 0; else tx_state <= oneus; i2 <= i2 + 1; end if;

when low_setup => LCD_E0 <= '0'; SF_D0 <= tx_byte(3 downto 0); if(i2 = 2) then tx_state <= low_hold; i2 <= 0; else tx_state <= low_setup; i2 <= i2 + 1; end if;

when low_hold => LCD_E0 <= '1'; SF_D0 <= tx_byte(3 downto 0); if(i2 = 12) then tx_state <= fortyus; i2 <= 0; else tx_state <= low_hold; i2 <= i2 + 1; end if;

when fortyus => LCD_E0 <= '0'; if(i2 = 2000) then tx_state <= done; i2 <= 0; else tx_state <= fortyus; i2 <= i2 + 1; end if; when done => LCD_E0 <= '0'; if(tx_init = '1') then tx_state <= high_setup; i2 <= 0; else tx_state <= done; i2 <= 0;

end if; end case; end if;

end process transmit; --specified by datasheet

power_on_initialize: process(clk, rst_n, init_init) --power on initialization sequence begin if(rst_n='0') then init_state <= idle; init_done <= '0'; elsif(clk='1' and clk'event) then case init_state is when idle => init_done <= '0'; if(init_init = '1') then init_state <= fifteenms; i <= 0; else init_state <= idle; i <= i + 1; end if; when fifteenms => init_done <= '0'; if(i = 750000) then init_state <= one; i <= 0; else init_state <= fifteenms; i <= i + 1; end if; when one => SF_D1 <= \ LCD_E1 <= '1'; init_done <= '0'; if(i = 11) then init_state<=two; i <= 0; else init_state<=one; i <= i + 1; end if; when two => LCD_E1 <= '0'; init_done <= '0';

if(i = 205000) then init_state<=three; i <= 0; else init_state<=two; i <= i + 1; end if; when three => SF_D1 <= \ LCD_E1 <= '1'; init_done <= '0'; if(i = 11) then init_state<=four; i <= 0; else init_state<=three; i <= i + 1; end if; when four => LCD_E1 <= '0'; init_done <= '0'; if(i = 5000) then init_state<=five; i <= 0; else init_state<=four; i <= i + 1; end if; when five => SF_D1 <= \ LCD_E1 <= '1'; init_done <= '0'; if(i = 11) then init_state<=six; i <= 0; else init_state<=five; i <= i + 1; end if; when six => LCD_E1 <= '0'; init_done <= '0'; if(i = 2000) then init_state<=seven;

i <= 0; else init_state<=six; i <= i + 1; end if; when seven => SF_D1 <= \ LCD_E1 <= '1'; init_done <= '0'; if(i = 11) then init_state<=eight; i <= 0; else init_state<=seven; i <= i + 1; end if; when eight => LCD_E1 <= '0'; init_done <= '0'; if(i = 2000) then init_state<=done; i <= 0; else init_state<=eight; i <= i + 1; end if; when done => init_state <= done; init_done <= '1'; end case; end if; end process power_on_initialize; end behavior;

因为LCD模块无法仿真，故在此不做仿真

四、实验总结

1、心得体会

此次设计实验是对本课程的一次总结，通过此次实验大大提高了自己的动手能力，对VHDL这门语言以及对FPGA的开发油了更加深入的了解

在动手设计实验的过程中，也遇到了很多问题，比如计数器工作不正常，LED

灯非正常闪烁，也用了了很大的功夫才把BUG解决。

课程设计给了我们把知识转化为能力的机会，这次电子技术课程设计更是让我受益良多。

其次本次试验也存在很多不足之处，如按键抖动的问题，还有红灯的计算模块都有欠缺考虑之处。还需要改进。

本文来源：https://www.bwwdw.com/article/dl25.html