代码1 功能1

代码1 功能:通过sw控制LED灯 module test001(SW,LEDR,LEDG); input[17:0] SW;//sw[17] output[17:0] LEDR; output reg[7:0] LEDG; //assign LEDRG[7:3]=5'B00000; assign LEDR=SW; always@(SW) begin

case(SW[17:15]) 3'b000:LEDG=SW[2:0]; 3'b001:LEDG=SW[5:3]; 3'b010:LEDG=SW[8:6]; 3'b011:LEDG=SW[11:9]; 3'b100:LEDG=SW[14:12]; default:LEDG=8'B00000000; endcase end endmodule

代码2: sw输入两个8位数,乘积在7段管上显示

module test004(SW,HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7); input[17:0] SW;

output[6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7; wire[15:0] mult;

assign mult=SW[15:8]*SW[7:0]; assign

{HEX7,HEX6,HEX5,HEX4}={decodeout(SW[7:4]),decodeout(SW[3:0]),decodeout(SW[15:12]),decodeout(SW[11:8])};

assign

{HEX3,HEX2,HEX1,HEX0}={decodeout(mult[15:12]),decodeout(mult[11:8]),decodeout(mult[7:4]),decodeout(mult[3:0])};

function[6:0] decodeout;

input[3:0] ina; case(ina)

4'b0000:decodeout=7'b1000000;//0 4'b0001:decodeout=7'b1111001; 4'b0010:decodeout=7'b0100100; 4'b0011:decodeout=7'b0110000; 4'b0100:decodeout=7'b0011001; 4'b0101:decodeout=7'b0010010; 4'b0110:decodeout=7'b0000010; 4'b0111:decodeout=7'b1111000; 4'b1000:decodeout=7'b0000000; 4'b1001:decodeout=7'b0010000;//9 4'b1010:decodeout=7'b0001000;//a 4'b1011:decodeout=7'b0000011;//b 4'b1100:decodeout=7'b1000110;//c 4'b1101:decodeout=7'b0100001;//d 4'b1110:decodeout=7'b0000110;//e 4'b1111:decodeout=7'b0001110;//f default:decodeout=7'b1111111; endcase endfunction endmodule

代码3:sw输入16位数,以十进制在7段管上显示

module test003(SW,HEX7,HEX6,HEX5,HEX4,HEX3,HEX2,HEX1,HEX0); input[17:0] SW;

output[6:0] HEX7,HEX6,HEX5,HEX4,HEX3,HEX2,HEX1,HEX0; assign HEX0=decodeout(SW'd10); assign HEX1=decodeout((SW/18'd10)'d10); assign HEX2=decodeout((SW/18'd100)'d10); assign HEX3=decodeout((SW/18'd1000)'d10); assign HEX4=decodeout((SW/18'd10000)'d10); assign HEX5=decodeout((SW/18'd100000)'d10);

assign HEX6=decodeout((SW/28'd1000000)'d10); assign HEX7=decodeout((SW/28'd10000000)'d10); function[6:0] decodeout; input[3:0] indec;

case(indec) //用case语句进行译码 4'd0:decodeout=7'b1000000; 4'd1:decodeout=7'b1111001; 4'd2:decodeout=7'b0100100; 4'd3:decodeout=7'b0110000; 4'd4:decodeout=7'b0011001; 4'd5:decodeout=7'b0010010; 4'd6:decodeout=7'b0000010; 4'd7:decodeout=7'b1111000; 4'd8:decodeout=7'b0000000; 4'd9:decodeout=7'b0010000; default: decodeout=7'b1111111; endcase endfunction endmodule

代码4:sw控制hello显示

module test002(SW,HEX0,HEX1,HEX2,HEX3,HEX4); input[17:0] SW;

output reg[6:0] HEX0,HEX1,HEX2,HEX3,HEX4; always@(SW) begin

case(SW[17:15])

3'b000:{HEX4,HEX3,HEX2,HEX1,HEX0}=35'B0001001_0000110_1000111_1000111_1000000;

3'b001:{HEX4,HEX3,HEX2,HEX1,HEX0}=35'B0000110_1000111_1000111_1000000_0001001;

3'b010:{HEX4,HEX3,HEX2,HEX1,HEX0}=35'B1000111_1000111_1000000_0001001_0000110;

3'b011:{HEX4,HEX3,HEX2,HEX1,HEX0}=35'B1000111_1000000_0001001_0000110_1000111;

3'b100:{HEX4,HEX3,HEX2,HEX1,HEX0}=35'B1000000_0001001_0000110_1000111_1000111;

default:{HEX4,HEX3,HEX2,HEX1,HEX0}=35'B1111111_1111111_1111111_1111111_1111111;

endcase end endmodule

代码5:状态机检测101序列,注意此代码使用3个状态实现,与课本上四状态有区别 module test0002(clk,clr,x,z); input clk,clr,x; output reg z;

reg[1:0] state,next_state;

parameter s0=2'b00,s1=2'b01,s2=2'b10; always@(posedge clk or posedge clr) begin

if(clr) state<=s0; else state<=next_state; end

always@(state or x) begin case(state)

s0:if(x) next_state<=s1;else next_state<=s0; s1:if(x) next_state<=s1;else next_state<=s2; s2:if(x) next_state<=s1;else next_state<=s0; endcase end

always@(state or x) begin case(state)

s2:if(x) z=1;else z=0; default:z=0;

endcase //else // case(state)

// s0:begin if(x) state<=s1;else state<=s0;z=0; end // s1:begin if(x) state<=s1;else state<=s2;z=0; end

// s2:begin if(x) begin state<=s1;z=1;end else begin state<=s0;z=0;end end // default:begin state<=s0;z=0; end // endcase end endmodule

代码6:运算器任务方式实现 module alutask(opcode,a,b,c); input[1:0] opcode; input[7:0] a,b; output reg[8:0] c; always@(a or b or opcode) begin//always case(opcode) 2'b00:my_and(a,b,c); 2'b01:c=a|b; 2'b10:c=a-b; 2'b11:c=a+b; default:c=9'bx; endcase end//always

task my_and; input[7:0] my_a,my_b; output[7:0] my_c; integer i; for(i=0;i<=7;i=i+1)

my_c[i]=my_a[i]&my_b[i]; endtask

endmodule 代码7:83编码器 module code_83(din,dout); input[7:0] din; output[2:0] dout;

function[2:0] code; input[7:0] din; casex (din)

8'b1xxx_xxxx : code = 3'h7; 8'b01xx_xxxx : code = 3'h6; 8'b001x_xxxx : code = 3'h5; 8'b0001_xxxx : code = 3'h4; 8'b0000_1xxx : code = 3'h3; 8'b0000_01xx : code = 3'h2; 8'b0000_001x : code = 3'h1; 8'b0000_000x : code = 3'h0; default: code = 3'hx; endcase endfunction

assign dout = code(din) ; endmodule

代码8:函数实现非波拉切序列

module funct(clk,n,result,reset); output[31:0] result; input[3:0] n; input reset,clk; reg[31:0] result;

always @(posedge clk) begin

if(!reset) result<=0; else begin

result <= 2 * factorial(n); end end

function[31:0] factorial; input[3:0] opa; reg[3:0] i; begin

factorial = opa ? 1 : 0; for(i=2;i<=opa;i=i+1) factorial = i* factorial; end endfunction

代码9:3过程实现101检测,fsm module TEST101(CLOCK_50,HEX0,KEY); input CLOCK_50; input[1:0] KEY; output[6:0] HEX0; reg[1:0] state,next_state; reg[3:0] count;

reg[32:0] temp=33'b000101010101001010101; parameter s0=2'b00,s1=2'b01,s2=2'b11,s3=2'b10; div_clock_1hz(CLOCK_50,CLK_1); de_16to7seg(count,HEX0);

always@(posedge CLK_1 or negedge KEY[0]) begin

if(!KEY[0]) temp<=11'b01001010101; else temp<=temp>>1; end

always@(posedge CLK_1 or negedge KEY[0])

begin

if(!KEY[0]) state<=s0; else state<=next_state; end

always@(state or temp[0]) begin case(state)

s0:if(temp[0])next_state<=s1; else next_state<=s0; s1:if(temp[0])next_state<=s1; else next_state<=s2; s2:if(temp[0])next_state<=s3; else next_state<=s0; s3:if(temp[0])next_state<=s1; else next_state<=s2; default:next_state<=s0; endcase end

always@(state) begin case(state)

s3:count<=count+1; endcase end

endmodule

代码10: 三种速度的hello显示

module test100(KEY,CLOCK_50,HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7,LEDR); input[1:0] KEY; input CLOCK_50; output[3:0] LEDR;

output[6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7; reg[55:0]

temp=56'B1111111_1111111_11111111_0001001_0000110_1000111_1000111_1000000;

reg[1:0] j;

assign LEDR={2'B00,j}; clock_1hz(CLOCK_50,CLK_1);

clock_025hz(CLOCK_50,CLK_025); clock_4hz(CLOCK_50,CLK_4);

assign clock=(j==0)?CLK_1:((j==2)?CLK_4:CLK_025);

assign {HEX7,HEX6,HEX5,HEX4,HEX3,HEX2,HEX1,HEX0}=temp; always@( KEY[0] or KEY[1]) begin

if(!KEY[0]) j=1;else j=0; if(!KEY[1]) j=2; else j=0; end

always@(posedge clock) begin

temp={temp,temp[55:49]}; end endmodule

module clock_1hz(clock_in,clock_out); input clock_in; output reg clock_out; integer i;

always@(posedge clock_in) begin

if(i==25000000) begin clock_out<=~clock_out; i<=0;end else i<=i+1; end

endmodule

module clock_025hz(clock_in,clock_out); input clock_in; output reg clock_out; integer i;

always@(posedge clock_in) begin

if(i==6250000) begin clock_out<=~clock_out; i<=0;end else i<=i+1;

end

endmodule

module clock_4hz(clock_in,clock_out); input clock_in; output reg clock_out; integer i;

always@(posedge clock_in) begin

if(i==100000000) begin clock_out<=~clock_out; i<=0;end else i<=i+1; end

endmodule

代码11:函数实现hello显示

module test002(SW,HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7); input[17:0] SW;

output reg[6:0] HEX0,HEX1,HEX2,HEX3,HEX4; output[6:0] HEX5,HEX6,HEX7;

assign {HEX5,HEX6,HEX7}=21'B1111111_1111111_11111111; always@(SW) begin

case(SW[17:15])

3'b000:{HEX0,HEX1,HEX2,HEX3,HEX4}={decout(SW[2:0]),decout(SW[5:3]),decout(SW[8:6]),decout(SW[11:9]),decout(SW[14:12])};

3'b001:{HEX0,HEX1,HEX2,HEX3,HEX4}={decout(SW[5:3]),decout(SW[8:6]),decout(SW[11:9]),decout(SW[14:12]),decout(SW[2:0])};

3'b010:{HEX0,HEX1,HEX2,HEX3,HEX4}={decout(SW[8:6]),decout(SW[11:9]),decout(SW[14:12]),decout(SW[2:0]),decout(SW[5:3])};

3'b011:{HEX0,HEX1,HEX2,HEX3,HEX4}={decout(SW[11:9]),decout(SW[14:12]),decout(SW[2:0]),decout(SW[5:3]),decout(SW[8:6])};

3'b100:{HEX0,HEX1,HEX2,HEX3,HEX4}={decout(SW[14:12]),decout(SW[2:0]),decout(SW[5:3]),decout(SW[8:6]),decout(SW[11:9])};

default:{HEX4,HEX3,HEX2,HEX1,HEX0}=35'B1111111_1111111_1111111_1111111_1111111;

endcase end

function[6:0] decout; input[2:0] ina; case(ina)

3'b000:decout=7'b0001001; 3'b001:decout=7'b0000110; 3'b010:decout=7'b1000111; 3'b011:decout=7'b1000000; 3'b100:decout=7'b1111111; default:decout=7'b0001111; endcase endfunction endmodule

代码12:sw输入两个16位数,在2组7段管上显示 (1) 两个数在特定位置上显示

module test_sx_0010(KEY,SW,HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7); input[15:0] SW; input[1:0] KEY;

output[6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7; reg[31:0] temp; reg state1;

de_16to7seg A1(temp[31:28],HEX7); de_16to7seg A2(temp[27:24],HEX6);

de_16to7seg A3(temp[23:20],HEX5); de_16to7seg A4(temp[19:16],HEX4); de_16to7seg A5(temp[15:12],HEX3); de_16to7seg A6(temp[11:8],HEX2); de_16to7seg A7(temp[7:4],HEX1); de_16to7seg A8(temp[3:0],HEX0);

always@(negedge KEY[1] or negedge KEY[0]) begin

if(!KEY[0]) temp<=32'B0; else if(!state1) temp[31:16]<=SW; else temp[15:0]<=SW; end

always@(negedge KEY[1] or negedge KEY[0]) begin

if(!KEY[0]) state1<=0; else state1<=state1+1'b1; end endmodule (2)移位方式显示

module test_sx_001(KEY,SW,HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7); input[15:0] SW; input[1:0] KEY;

output[6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7; reg[31:0] temp; //reg state1;

de_16to7seg A1(temp[31:28],HEX7); de_16to7seg A2(temp[27:24],HEX6); de_16to7seg A3(temp[23:20],HEX5); de_16to7seg A4(temp[19:16],HEX4); de_16to7seg A5(temp[15:12],HEX3); de_16to7seg A6(temp[11:8],HEX2);

de_16to7seg A7(temp[7:4],HEX1); de_16to7seg A8(temp[3:0],HEX0);

always@(negedge KEY[1] or negedge KEY[0]) begin

if(!KEY[0]) temp<=32'B0; else temp<={temp,SW}; end endmodule 7段管译码模块

module de_16to7seg(ina,decodeout); input[3:0] ina;

output reg[6:0] decodeout; always@(ina) case(ina)

4'b0000:decodeout=7'b1000000;//0 4'b0001:decodeout=7'b1111001; 4'b0010:decodeout=7'b0100100; 4'b0011:decodeout=7'b0110000; 4'b0100:decodeout=7'b0011001; 4'b0101:decodeout=7'b0010010; 4'b0110:decodeout=7'b0000010; 4'b0111:decodeout=7'b1111000; 4'b1000:decodeout=7'b0000000; 4'b1001:decodeout=7'b0010000;//9 4'b1010:decodeout=7'b0001000;//a 4'b1011:decodeout=7'b0000011;//b 4'b1100:decodeout=7'b1000110;//c 4'b1101:decodeout=7'b0100001;//d 4'b1110:decodeout=7'b0000110;//e 4'b1111:decodeout=7'b0001110;//f default:decodeout=7'b1111111; endcase

endmodule

代码13:999计数

module test_sx_002_1(CLOCK_50,HEX0,HEX2,HEX1,HEX3,HEX4,HEX5,HEX6,HEX7,SW);//二进制计数器

input CLOCK_50; input[1:0] SW;

output[6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7; reg[9:0] temp;

assign {HEX3,HEX4,HEX5,HEX6,HEX7}=35'HFFFFFFFFF; div_clock_1hz c1(CLOCK_50,clock_1,SW[0]); de_16to7seg d1((temp/100),HEX2); de_16to7seg d2((temp/10),HEX1); de_16to7seg d3(temp,HEX0);

always@(posedge clock_1 or posedge SW[0]) begin

if(SW[0]) temp<=10'b0; else if(SW[1]) begin

if(temp==10'd999) temp<=10'd0; else temp<=temp+1'b1; end else begin

if(temp==10'd0) temp<=10'd999; else temp<=temp-1'b1; end end endmodule

module test_sx_002(CLOCK_50,HEX0,HEX2,HEX1,SW);//采用bcd码 input CLOCK_50; input[1:0] SW;

output[6:0] HEX0,HEX1,HEX2; reg[11:0] temp;

div_clock_1hz c1(CLOCK_50,clock_1,SW[0]); de_16to7seg d1(temp[11:8],HEX2); de_16to7seg d2(temp[7:4],HEX1); de_16to7seg d3(temp[3:0],HEX0);

always@(posedge clock_1 or posedge SW[0]) begin

if(SW[0]) temp<=12'b0; else if(SW[1])

begin //tag 1_top if(temp[3:0]==4'd9) begin temp[3:0]<=4'b0; if(temp[7:4]==4'd9) begin

temp[7:4]<=4'b0; if(temp[11:8]==4'd9) begin

temp[11:8]<=4'b0; end

else temp[11:8]<=temp[11:8]+1'b1; end

else temp[7:4]<=temp[7:4]+1'b1; end

else temp[3:0]<=temp[3:0]+1'b1; end//tag 1_bottom else//SW[1]=0 begin

if(temp[3:0]==4'b0) begin

temp[3:0]<=4'd9; if(temp[7:4]==4'b0) begin

temp[7:4]<=4'd9;

if(temp[11:8]==4'b0) begin

temp[11:8]<=4'd9; end

else temp[11:8]<=temp[11:8]-1'b1; end

else temp[7:4]<=temp[7:4]-1'b1; end

else temp[3:0]<=temp[3:0]-1'b1; end end endmodule

module div_clock_1hz(clock_in,clock_out,clr);//1hz分频 input clock_in,clr; output reg clock_out; integer i;

always@(posedge clock_in or posedge clr) begin if(clr) i<=0;

else if(i==25000000) begin clock_out<=~clock_out; i<=0;end else i<=i+1; end

endmodule

代码14:时钟控制下的hello循环显示

module test003_sx_1(CLOCK_50,HEX7,HEX6,HEX5,HEX4,HEX3,HEX2,HEX1,HEX0,KEY); input CLOCK_50; input[1:0] KEY;

output[6:0] HEX7,HEX6,HEX5,HEX4,HEX3,HEX2,HEX1,HEX0; reg[31:0] temp;

div_clock_1hz(CLOCK_50,clock_1,KEY[0]); de_16to7seg(temp[31:28],HEX7); de_16to7seg(temp[27:24],HEX6); de_16to7seg(temp[23:20],HEX5);

de_16to7seg(temp[19:16],HEX4); de_16to7seg(temp[15:12],HEX3); de_16to7seg(temp[11:8],HEX2); de_16to7seg(temp[7:4],HEX1); de_16to7seg(temp[3:0],HEX0);

always@(posedge clock_1 or negedge KEY[0]) begin

if(!KEY[0]) temp<=32'H44401223; else begin

temp<={temp,temp[31:28]}; end end endmodule

代码15:模60计数,bcd码方式,此题目为时分秒计数,只考虑秒计时, module test004(CLOCK_50,KEY,HEX0,HEX1,HEX2,HEX3,HEX4,HEX5); input CLOCK_50; input[1:0] KEY;

output[6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5; reg[5:0] sec,min,hour;

div_clock_1hz (CLOCK_50,clock_1); de_16to7seg a1((hour/10),HEX5); de_16to7seg a2(hour,HEX4); de_16to7seg a3((min/10),HEX3); de_16to7seg a4(min,HEX2); de_16to7seg a5((sec/10),HEX1); de_16to7seg a6(sec,HEX0); always@(posedge clock_1 ) begin

if(sec==6'd59) begin sec<=6'd0; if(min==6'd59) begin

if(hour==6'd59) hour<=6'd0; else hour<=hour+1'b1; end

else min<=min+1'b1; end

else sec<=sec+1'b1; end endmodule

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