嵌入式系统软件教程答案

An Embedded Software Primer

Answers to Problems A.Answers to Selected Problems

Copyright ? Addison Wesley Longman, 1999

This file contains answers to some of the problems that appear at the end of the chapters in the text.

A.1 Chapter 1

Chapter 1 contains no problems.

A.2 Chapter 2

1. The program for an intelligent VCR should probably be stored in masked ROM. That form of memory is the cheapest, which will probably be the most important consideration of product of which you hope to sell this many copies.

A user-configurable name for a network printer should remember even if the power fails probably be stored either in flash memory or in EEROM. Both of these

memories will remember the data when the power is turned off. Since is unlikely that the user will change in the name more can be a few dozen times, the limitations on writing to flash memory will probably not be a problem. Particularly if the program for the microprocessor in the printer is in flash memory anyway, flash might be a good choice.

The program for a beta version of almost anything should probably be either in

PROM, EPROM, or flash memory. The likelihood is that you will want to change the program, and these forms of memory make that possible. Most beta tests require few enough units that cost should not be an issue.

The data that your program just received from the network has to be in RAM. Your program is probably allowed to forget this data if the power fails, and the ability to read and write this data quickly is probably the most important concern.

2. The output for a three-input AND gate is high if the three inputs are high and low otherwise. Therefore the truth table looks like this:

Input 1 Input 2 Input 3 Output High High High High High High Low Low High Low High Low

Page A-1 An Embedded Software Primer

Answers to Problems High Low Low Low Low High High Low Low High Low Low Low Low High Low Low

Low Low Low 3. No answer provided.

4. The engineer would run the HARDWARE_FINISHED/ and

SOFTWARE_NOT_WORKING signals through inverters and then route the outputs of the inverters along with the NO_BUGS signal into a three-input NAND gate.

5. No answer provided.

6. This circuit acts as an inverter; its output is always the opposite of its input. The most likely reason that an engineer might do this is that he needs to invert a signal and that his design has a spare NAND gate on it (they are typically packaged in sets of four) and no spare inverter.

7. The problem is that the capacitor is on the wrong side of the switch. As the circuit is drawn, when the switch is first closed, allowing current to flow into the right hand side of the circuit, the current will not only have to power the right-hand side of the circuit but also charge the capacitor. This will cause a momentary brownout for the parts on the left-hand side of the circuit as well. If the capacitor were on the left-hand side of the switch, then when the switch closed, the capacitor would already be

charged, and it would be able to give up some of its charge to prevent the brownout.

8. Each inverter in the lower left-hand corner of the circuit only has to drive a portion of the parts in the rest of the circuit; therefore, neither inverter has to drive too much. The advantage of this second method is that both parts of the circuit get the signal at the same time; in the first method, the right hand side of the circuit gets the signal a little bit later, later by the amount of propagation delay in the driver. In especially time-critical circuits, this might make the difference.

9. The timing diagram for the read cycle for a static RAM is identical to the timing diagram for the read cycle from a ROM. The write cycle is similar, except that the write enable signal will pulse instead of the read enable signal, and the data is likely to appear on the bus at the same time as the address, since the microprocessor will drive both at the same time.

Page A-2

An Embedded Software Primer

Answers to Problems A0-An

D0-Dn

CE/

WE/

A.3 Chapter 3

1. The first thing to notice in addressing this problem is that the highest-order address line, A19, is low in the addresses that belong to the ROM chips and high in the addresses that belong to the RAM chips. Therefore, one or the other of the ROM chips should be enabled when A19 is low, and one or the other of the RAM chips should be enabled when A19 is high. Since the first of the ROM chips should be enabled as long as the address is less than 0x1ffff, it should therefore be enabled when A17 is low. The second ROM ship should be enabled when A17 is high. Similarly, the first RAM chip should be enabled when A16 is low, and the second should be enabled when A16 is high.

Assuming that the chip enable lines on both the ROM and the RAM chips are active low, one possible design that implements the comments in the above paragraph is as follows:

Page A-3 An Embedded Software Primer Answers to Problems ROM chips A19 A17 CE/ CE/ CE/ CE/ A16 RAM chips 2. No answer provided.

3. The most common reason for connecting more than one I/O device to the same

interrupt pin on the microprocessor is that you have more I/O devices than interrupt pins. This mechanism allows you to deal with this situation. The disadvantage is that software will have to have some way of figuring out which of the two devices is causing the interrupt or if both are. Since both devices are connected to the same interrupt signal, the microprocessor will go to the same interrupt routine when either of the devices interrupts. This will also mean that the software will respond to these devices a little more slowly, since it will take a little bit of time to figure out which device needs service.

4. The advantage of the edge-triggered interrupt is that the device that is requesting the interrupt need not continue signaling it; the microprocessor will recognize the edge of the signal even if it is just a pulse. The disadvantage is that if the device wants to signal two interrupts, it must ensure that it stops asserting its interrupt signal for a short time between the two so that the second interrupt will cause an edge and be recognized by the microprocessor.

5. No answer provided.

6. You would certainly find a power pin and a ground pin on any UART. Many UARTs

also have output pins that allow them to signal a DMA channel to transfer data into or

out of the memory. Finally, since timing is very important to UARTs, many of them have several kinds of input and output clock pins.

Page A-4 An Embedded Software Primer

Answers to Problems 7. A FIFO for received bytes is useful because it allows a certain number of bytes to pile up in the UART while the microprocessor is busy doing other things. A UART that has no FIFO can only remember one received byte at a time; this means that the microprocessor must read each byte from the UART before the next one is received. On a fast serial line, the microprocessor might not be able to keep up if it had to stop what it is doing and execute an interrupt routine each time a single character came in. Even if the microprocessor could keep up, getting into and out of interrupt routines would use up a lot of extra processor cycles. With a FIFO, the microprocessor can wait until several bytes have come in and then transfer them to the memory all at once.

8. There are in the number of ways to do this. One straightforward way to do it is to attach the LED to one of the outputs of a D flip flop. Attach the D input to the D0 data signal, and build some circuitry that pulses the CLK input whenever the

microprocessor writes to some particular address. Then the microprocessor can turn the LED on by writing the value 1 to the chosen address and turn it off by writing the value 0 (or vice versa, depending upon exactly how you acquire it up).

Another popular way to control LEDs is to find some unused output on a UART (for example, RTS on a system that does not use RTS) and attach the LED to that. The microprocessor then instructs the UART whether to signal RTS high or low (typically by writing to a register within the UART) and thereby controls the LED.

9. No answer provided.

10. It is a serial, one-bit-at-a-time device. To write to it, you assert EEENABLE/ and EEWRITE/. Then you put bits on the EEDATA signal, lower the EECLK signal, and raise the EECLK signal. The EEROM will treat the first half dozen bits as an address into which to write the next eight bits as data. The mechanism for reading data is similar, except that you do not assert EEWRITE/and that the EEROM will drive the EEDATA with the data whenever you lower EECLK. A partial timing diagram

showing how to write to the EEROM is below, showing the beginning of the address and the end of the data being sent to the EEROM.

Page A-5

本文来源：https://www.bwwdw.com/article/cyid.html