Low-Microwave Loss Coplanar Waveguides Fabricated on High-Re

第27卷　第1期2006年1月

半　导　体　学　报

CHIN ESE J OURNAL OF SEMICONDUCTORS

Vol.27　No.1

J an.,2006

3Project supported by t he State Key Development Program for Basic Research of China (No.G2000068301),t he National High Technology

R &D Program of China (No.2002AA312150,)and t he National Natural Science Foundation of China (Nos.90101023,60176023,60476009)

Corresponding aut hor.Email :yanghua @368c0e7b31b765ce0508149a

　Received 15August 2005,revised manuscript received 21September 2005

ν2006Chinese Institute of Electronics

Low 2Microw ave Loss Coplanar W aveguides F abricated

on High 2R esistivity Silicon Substrate 3

Yang Hua ,Zhu Hongliang ,Xie Hongyun ,Zhao Lingjuan ,Zhou Fan ,and Wang Wei

(I nstit ute of S emiconductors ,Chinese A cadem y of S ciences ,B ei j ing 　100083,China )

Abstract :Three kinds of coplanar waveguides (CPWs )are designed and fabricated on different silicon sub 2

strates ———common low 2resistivity silicon substrate (L RS ),L RS with a 3

μm 2thick silicon oxide interlayer ,and high 2resistivity silicon (HRS )substrate.The results show that the microwave loss of a CPW on L RS is too high to be used ,but it can be greatly reduced by adding a thick interlayer of silicon oxide between the CPW transmission lines and the L RS.A CPW directly on HRS shows a loss lower than 2dB/cm in the range of 0～26GHz and the process is simple ,so HRS is a more suitable CPW substrate.

K ey w ords :copla nar waveguides ;high 2resistivity silicon ;microwave loss ;high f reque ncy ;op t oelect ronic p ack 2

aging

EEACC :1310;1305;0710J C LC number :TN248　　　Document code :A 　　　Article ID :025324177(2006)0120001204

1　Introduction

Wit h t he rapid develop ment of t he internet and wireless communication ,t here has been a great demand for low 2lo ss ,low 2cost ,and small 2size radio f requency (RF )and microwave circuit s ,which are necessary for supplying t he devices and modules wit h high speed drive during t he course of optoe 2lect ronic and microelect ronic packaging.In micro 2wave circuit s ,t he coplanar waveguide (CPW )is one of t he mo st pop ular microwave component s.A qualified CPW should have low lo ss ,high t ransmis 2sion power ,wide working bandwidt h ,and low co st.

Silicon has been t he preferred subst rate mate 2rial for CPWs because of it s many advantages ,such as mat ure technology ,good t hermal conduc 2tivity ,easy integration wit h t he microelect ro nic de 2vices ,and low cost [1～4].However ,transmission lines and passive component s on standard low 2re 2sistivity silicon subst rate have high loss because of it s semiconductor characteristics.To overcome t his p roblem ,many approaches have been used.One is

to use a material wit h a low dielect ric constant ,such as silicon oxide or polyimide ,as t he interlayer between t he transmission lines and silicon sub 2strate to reduce t he attenuation [5,6].Though it has been approved as an effective way ,it makes t he p rocess more complicated and is incompatible wit h ot her processes.The ot her st raightforward ap 2proach t hat directly fabricates microwave transmis 2sion lines on t he high 2resistivity silicon (HRS )subst rate is p referable because t he p rocess is sim 2ple ,and t he price of HRS is comparable wit h standard low 2resistivity silicon now ,which is a 2round ＄15for a 100mm wafer wit h a resistivity of around 4000Ω?cm.According to Ref s.[7,8],a resistivity of over 2500Ω?cm is enough for t he de 2mand of low loss at high f requencies for transmis 2sion line.

In t his paper ,t hree kinds of CPWs were made on high 2resistivity silicon subst rate ,standard low 2resistivity silicon (L RS )subst rate ,and L RS sub 2strate wit h a silicon oxide interlayer.The design and fabrication of CPWs are int roduced.

半　导　体　学　报第27卷

2　Design

In t he packaging of optoelectronic devices ,

CPWs wit h an impedance of 50Ωare very pop ular for meeting t he impedance match.The common CPW st ruct ure is shown in Fig.1(a ),in which t he impedance of t he CPW is related to t he parameters W ,G,T ,and H .In t his paper ,microwave office software was used to determine t hese parameters wit h t he existing CPW model to make sure t he im 2pedance of t he CPW is 50Ω.Also taking t he con 2venience of measurement s into consideration ,t he

parameters were determined to be W =120

μm ,G =75

μm ,H =500μm ,and T =2μm.The st ruct ure of t he CPW on t he subst rate wit h t he interlayer is shown in Fig.1(b )

.

Fig.1　(a )Cross section geometries of the standard

CPW ;(b )Cross section geometries of the CPW with an interlayer

3　F abrication

In t he experiment ,we fabricated t he CPW t ransmission lines on L RS ,L RS wit h a silicon ox 2ide interlayer ,and HRS.The t hree kinds of sample

substrates used in t he experiment s were all 500

μm t hick ,t he resistivity of t he HRS used was around 4000Ω?cm ,t he L RS was 3～5Ω?cm ,and t he sili 2con o xide interlayer between t he t ransmission lines

and t he L RS substrate was 3

μm t hick ,which was obtained t hrough t hermal oxidation in t he L RS wa 2fer.The same fabrication process was used for all samples.First ,a 300nm t hick CrAu was depo sited

on t he wafers t hrough evaporation.Then t he resist was coated.After exposure and wet etching ,t he

CPW pattern was formed.Finally ,a 2

μm of Au was elect roplated onto t he CPW transmission lines.

4　R esults and discussion

The measurement s were taken on wafers using an H P 8510C network analyzer and high f requency coplanar p robes.The S parameters S 21and S 11of t hree kinds of CPWs were obtained and are shown in Figs.2and 3.The attenuation was calculated and is plotted ,see Fig.

4.

Fig.2　S 21of the CPWs on HRS ,L RS ,and L RS with a 3

μm

interlayer Fig.3　S 11of the CPWs on HRS ,L RS ,and L RS with a 3

μm interlayer From t he figures ,we can see t hat t he perform 2ance of t he CPW on t he L RS subst rate is very poor because of t he low resistivity ,which leads to “t hrough state ”between t he signal and gro und lines at high f requencies.The lo ss is more t han 200dB/cm ,which is too high for use as a CPW sub 2strate.When a 3μm silicon oxide interlayer is add 2

2

第1期Yang Hua et al.:　Low 2Microwave Loss Coplanar Waveguides Fabricated on High 2Resistivity

…

Fig.4　Loss of the CPWs on HRS ,L RS ,and L RS with a 3

μm interlayer ed between t he t ransmission lines and t he L RS ,be 2

cause of it s insulating character ,t he performance is improved greatly and t he lo ss is reduced to less t han 100dB/cm in t he f requency range of 0～26GHz ,but it is still too high for practical use.A t hicker silicon oxide layer is needed ,which means a longer oxidation time.Not only does t his increase t he cost ,but a t hick silicon oxide layer would be an obstacle for ot her processes.The CPWs on HRS show good performance because of t he limit of measurement s.They demonst rated a loss lower t han 2dB/cm in t he f requency range of 0～26GHz ,which we p redict will be still lower at higher fre 2quencies.The HRS is t herefore a more suitable low microwave lo ss subst rate for CPWs.

5　Conclusion

In t his paper ,t hree kinds of CPWs were made on HRS subst rate ,standard L RS subst rate ,and L RS subst rate wit h a silicon oxide interlayer.The result s show t hat t he L RS is unsuitable for high f requency coplanar waveguides because of t he high microwave lo ss.Adding a silicon oxide interlayer between t he coplanar waveguide t ransmission lines and t he L RS substrate ,t he lo ss can be greatly re 2duced ,but a t hick silicon oxide layer is necessary ,which will increase t he cost and com 2plicate ot her processes.The coplanar waveguide

made directly on HRS has a very low loss at high f requencies ,p roving to be an effective way to ob 2tain a high f requency and low loss coplanar waveguide.R eferences

[1]　Reyes A C ,El 2Ghazaly S M ,Dorn S ,et al.Coplanar

waveguides and microwave inductors on silicon substrates.IEEE Trans Microw Theory Tech ,1995,43(9):2016

[2]　Reyes C ,El 2Ghazaly S M ,Dorn S ,et al.Silicon as a microwave

substrate.IEEE MIT 2S International Microwave Symposium Digest ,1994,3:1759

[3]　Xiong B ,Wang J ,Cai P F ,et al.Novel low 2cost wideband Si 2

based submount for 40Gb/s optoelectronic devices.Micro 2wave and Optical Technology Letters ,2005,45:90

[4]　Xiong B ,Wang J ,Cai P F ,et al.Novel low 2cost wideband Si 2

based submount for 40Gb/s optoelect ronic devices.Chinese Journal of Semiconductors ,2005,26(10):2001(in Chinese )

[熊兵,王健,蔡鹏飞,等.用于40Gb/s 光电子器件的新型低成本硅基过渡热沉.半导体学报,2005,26(10):2001]

[5]

　Ponchak G E ,Margomenos A ,Katchi L P B.Low 2loss CPW on low 2resistivity Si substrates wit h a micro machined polyim 2ide interface layer for RFIC interconnect s.IEEE Trans Mi 2crow Theory Tech ,2001,49(5):866

[6]

　Wu Y H ,Gamble H S ,Armstrong B M ,et al.SiO 2Interface layer effect s on microwave loss of high 2resistivity CPW line.IEEE Microw Guided Wave Lett ,1999,9:10[7]　Luy F ,Strohm K M ,Sasse H E ,et al.Si/Si Ge MMICs.IEEE Trans Microw Theory Tech ,1995,43(4):705

[8]

　Rich S ,Lu L H ,Bhattacharya L P ,et al.X 2and Ku 2band am 2plifiers based on Si/Si Ge HB T ’s and micromachined lumped component s.IEEE Trans Microw Theory Tech ,1998,46(5):685

3

半　导　体　学　报第27卷4

在高阻硅衬底上制备低微波损耗的共面波导3

杨　华 　朱洪亮　谢红云　赵玲娟　周　帆　王　圩

(中国科学院半导体研究所光电子研究发展中心,北京　100083)

摘要:分别在普通的低阻硅衬底、带有3μm厚氧化硅介质层的低阻硅衬底和高阻硅衬底上设计并制备了微波传输共面波导.结果表明,低阻硅衬底导致过高的微波损耗从而不能使用,通过加氧化硅介质层,微波损耗可以大大减少,但是需要较厚的氧化硅厚度.直接制备在高阻硅衬底上的共面波导在所测试的26GHz的频率范围内获得低于2dB/cm的微波损耗,而且工艺十分简单.

关键词:共面波导;高阻硅;微波损耗;高频;光电子封装

EEACC:1310;1305;0710J

中图分类号:TN248　　　文献标识码:A　　　文章编号:025324177(2006)0120001204

3国家重点基础研究发展规划(批准号:G2000068301),国家高技术研究发展计划(批准号:2002AA312150)和国家自然科学基金(批准号: 90101023,60176023,60476009)资助项目

通信作者.Email:yanghua@368c0e7b31b765ce0508149a

　2005208215收到,2005209221定稿ν2006中国电子学会

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