Synthesizable Verilog HDL Reference Manual - by Synopsys

FPGA Compiler II / FPGA Express

V erilog HDL Reference Manual

Version 1999.05, May 1999 Comments?

E-mail your comments about Synopsys documentation to doc@335c91ed856a561252d36f7a

Copyright Notice and Proprietary Information

Copyright ? 1999 Synopsys, Inc. All rights reserved. This software and documentation are owned by Synopsys, Inc., and furnished under a license agreement. The software and documentation may be used or copied only in accordance with the terms of the license agreement. No part of the software and documentation may be reproduced, transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without prior written permission of Synopsys, Inc., or as expressly provided by the license agreement.

Right to Copy Documentation

The license agreement with Synopsys permits licensee to make copies of the documentation for its internal use only. Each copy shall include all copyrights, trademarks, service marks, and proprietary rights notices, if any. Licensee must assign sequential numbers to all copies. These copies shall contain the following legend on the cover page:“This document is duplicated with the permission of Synopsys, Inc., for the exclusive use of

__________________________________________ and its employees. This is copy number

__________.”

Destination Control Statement

All technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader’s responsibility to determine the applicable regulations and to comply with them.

Disclaimer

SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MA TERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANT ABILITY AND FITNESS FOR A P ARTICULAR PURPOSE.

Registered Trademarks

Synopsys, the Synopsys logo, BiNMOS-CBA, CMOS-CBA, COSSAP, DESIGN (ARROWS), DesignPower, DesignWare, dont_use, Eagle Design Automation, ExpressModel, in-Sync, LM-1000, LM-1200, Logic Modeling, Logic Modeling (logo), Memory Architect, ModelAccess, ModelT ools, PathMill, PL debug, Powerview, Retargeter, SmartLicense, SmartLogic, SmartModel, SmartModels, SNUG, SOL V-IT!, SourceModel Library, Stream Driven Simulator_, Synopsys, Synopsys (logo), Synopsys VHDL Compiler, Synthetic Designs, Synthetic Libraries, T estBench Manager, TimeMill, ViewBase, ViewData, ViewDoc, ViewDraw, ViewFault, ViewFlow, VIEWFPGA, ViewGen, Viewlogic, ViewPlace, ViewPLD, ViewScript, ViewSim, ViewState, ViewSynthesis, ViewT ext, Workview, Workview Office, and Workview Plus are registered trademarks of Synopsys, Inc.

Trademarks

3-D Debugging, AC/Grade, AMPS, Arcadia, Arkos, Aurora, BCView, BOA, BRT, CBA Design System, CBA-Frame, characterize, Chip Architect, Chronologic, Compiler Designs, Core Network, Core Store, Cyclone, Data Path Express, DataPath Architect, DC Expert, DC Expert Plus, DC Professional, Delay Mill, Design Advisor, Design Analyzer_proposed, Design Exchange, Design Source, DesignTime, DesignWare Developer, Direct RTL, Direct Silicon Access, dont_touch, dont_touch_network, DW 8051, DWPCI, DxDataBook, DxDataManager, Eagle, Eagle i, Eagle V, Embedded System Prototype, Floorplan Manager, Formality, FoundryModel, FPGA Compiler II, FPGA Express, Fusion, FusionHDL, General Purpose Post-Processor, GPP, HDL Advisor, HTX, Integrator, IntelliFlow, Interactive Waveform Viewer, ISIS, ISIS PreVUE, LM-1400, LM-700, LM-family, Logic Model, ModelSource, ModelWare, MOTIVE, MS-3200, MS-3400, PathBlazer, PDQ, POET, PowerArc, PowerCODE, PowerGate, PowerMill, PreVUE, PrimeTime, Protocol Compiler, QUIET, QUIET Expert, RailMill, RTL Analyzer, Shadow Debugger, Silicon Architects, SimuBus, SmartCircuit, SmartModel Windows, Source-Level Design, SourceModel, SpeedWave, SWIFT, SWIFT interface, Synopsys Behavioral Compiler, Synopsys Design Compiler, Synopsys ECL Compiler, Synopsys ECO Compiler, Synopsys FPGA Compiler, Synopsys Frame Compiler, Synopsys Graphical Environment, Synopsys HDL Compiler, Synopsys Library Compiler, Synopsys ModelFactory, Synopsys Module Compiler, Synopsys Power Compiler, Synopsys T est Compiler, Synopsys T est Compiler Plus, T AP-in, T est Manager, T estGen, T estGen Expert Plus, T estSim, Timing Annotator, TLC, T race-On-Demand, VCS, DCS Express, VCSi, VHDL System Simulator, ViewAnalog, ViewDatabook, ViewDRC, ViewLibrarian, ViewLibrary, ViewProject, ViewSymbol, ViewT race, Visualyze, Vivace, VMD, VSS Expert, VSS Professional VWaves, XFX, XNS, and XTK are trademarks of Synopsys, Inc. Service Marks

SolvNET is a service mark of Synopsys, Inc.

All other product or company names may be trademarks of their respective owners.

Printed in the U.S.A.

FPGA Compiler II / FPGA Express Verilog HDL Reference Manual, Version 1999.05

ii

About This Manual

This manual describes the Verilog portion of Synopsys FPGA

Compiler II / FPGA Express application, part of the Synopsys suite

of synthesis tools. FPGA Compiler II / FPGA Express reads an RTL

Verilog HDL model of a discrete electronic system and synthesizes

this description into a gate-level netlist.

FPGA Compiler II / FPGA Express supports v1.6 of the Verilog

language. Deviations from the definition of the Verilog language are

explicitly noted. Constructs added in versions subsequent to Verilog

1.6 might not be supported. Aspects of the Verilog language that are

not supported are listed in Appendix B.

Audience

This manual is written for logic designers and electronic engineers

who are familiar with Synopsys synthesis products. Knowledge of the

Verilog language is required, and knowledge of a high-level

programming language is helpful.

iii

Other Sources of Information

The resources in the following sections provide additional information:

?Related Publications

?SolvNET Online Help

?Customer Support

Related Publications

These Synopsys documents supply additional information:

?FPGA Compiler II / FPGA Express Getting Started Manual

?Design Compiler Command-Line Interface Guide

?Design Compiler Reference Manual: Constraints and Timing

?Design Compiler Reference Manual: Optimization and Timing Analysis

?Design Compiler T utorial

?Design Compiler User Guide

?DesignWare Developer Guide

?VSS User Guide

Man Pages

Y ou can view man pages from fc2_shell / fe_shell environment. From

the shell prompt, enter:

iv

fc2_shell> help command_name

or

fe_shell> help command_name

SolvNET Online Help

SOL V-IT! is the Synopsys electronic knowledge base. It contains information about Synopsys and its tools and is updated daily.

Access SOL V-IT! through e-mail or through the World Wide Web (WWW). For more information about SOL V-IT!, send e-mail to

solvitfb@335c91ed856a561252d36f7a

or view the Synopsys Web page at

335c91ed856a561252d36f7a

Customer Support

If you have problems, questions, or suggestions, contact the Synopsys T echnical Support Center in one of the following ways:?Send e-mail to

support_center@335c91ed856a561252d36f7a

?Call (650) 584-4200 outside the continental United States or call (800) 245-8005 inside the continental United States, from 7 a.m.

to 5:30 p.m. Pacific time, Monday through Friday.

?Send a fax to (650) 584-2539.

v

Conventions

The following conventions are used in Synopsys documentation.

Convention Description

courier Indicates command syntax.

In command syntax and examples, shows

system prompts, text from files, error

messages, and reports printed by the

system.

courier italic Indicates a user specification, such as

object_name

courier bold In command syntax and examples, indicates

user input (text the user types verbatim).

[ ]Denotes optional parameters, such as pin1

[pin2, . . pinN]

|Indicates a choice among alternatives, such

as

low | medium | high

This example indicates that you can enter

one of three possible values for an option:

low, medium, or high.

_Connects two terms that are read as a single

term by the system. For example,

design_space.

(Ctrl-c)Indicates a keyboard combination, such as

holding down the Ctrl key and pressing c.

\Indicates a continuation of a command line.

/Indicates levels of directory structure.

Edit > Copy Shows a menu selection. Edit is the menu

name and Copy is the item on the menu.

vi

T able of Contents

About This Manual

1.FPGA Compiler II / FPGA Express with Verilog HDL

Hardware Description Languages. . . . . . . . . . . . . . . . . . . . . . . . . .1-2 FPGA Compiler II / FPGA Express and the Design Process . . . . .1-4 Using FPGA Compiler II / FPGA Express to Compile a Verilog HDL Design 1-5

Design Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6 2.Description Styles

Design Hierarchy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2 Structural Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3 Functional Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3 Mixing Structural and Functional Descriptions . . . . . . . . . . . . . . . .2-4 Design Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6 Description Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6 Language Constructs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6

vii

Register Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7 Asynchronous Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8 3.Structural Descriptions

Modules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2 Macromodules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3 Port Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-4

Port Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-5 Renaming Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-6 Module Statements and Constructs . . . . . . . . . . . . . . . . . . . . . . . .3-7

Structural Data T ypes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-8 parameter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-8

wire. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-9

wand. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-10

wor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-11

tri . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-12

supply0 and supply1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-13

reg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-13 Port Declarations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-14 input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-14

output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-14

inout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-15 Continuous Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-15 Module Instantiations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-17 Named and Positional Notation . . . . . . . . . . . . . . . . . . . . . . . . .3-18 Parameterized Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-19

viii

Gate-Level Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-20 Three-State Buffer Instantiation. . . . . . . . . . . . . . . . . . . . . . . . .3-22

4.Expressions

Constant-Valued Expressions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2 Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3 Arithmetic Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4 Relational Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5 Equality Operators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-6 Handling Comparisons to X or Z . . . . . . . . . . . . . . . . . . . . . . . .4-7 Logical Operators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-8 Bitwise Operators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-9 Reduction Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-10 Shift Operators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-11 Conditional Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-12 Concatenation Operators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-13 Operator Precedence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-15 Operands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-16 Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-16 Wires and Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-17 Bit-Selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-17

Part-Selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-18 Function Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-18 Concatenation of Operands. . . . . . . . . . . . . . . . . . . . . . . . . . . .4-19 Expression Bit-Widths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-19

ix

5.Functional Descriptions

Sequential Constructs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-2 Function Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-3 Input Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-5 Output From a Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-5 Register Declarations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-6 Memory Declarations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-7 Parameter Declarations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-8 Integer Declarations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-9 Function Statements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-9 Procedural Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-10 RTL Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-11 begin...end Block Statements . . . . . . . . . . . . . . . . . . . . . . . . . .5-14 if...else Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-15 Conditional Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-18 case Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-18 Full Case and Parallel Case. . . . . . . . . . . . . . . . . . . . . . . . . . . .5-20 casex Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-22 casez Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-25 for Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-27 while Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-29 forever Loops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-30 disable Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-31 task Statements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-32 always Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-34

x

Event Expression. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-34 Incomplete Event Specification . . . . . . . . . . . . . . . . . . . . . . . . .5-37

6.Register and Three-State Inference

Register Inference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1 The Inference Report. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-2 Latch Inference Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-4 Controlling Register Inference. . . . . . . . . . . . . . . . . . . . . . . . . .6-4 Attributes That Control Register Inference. . . . . . . . . . . . . .6-4 Inferring Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-7 Inferring SR Latches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-7

Inferring D Latches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-9

Understanding the Limitations of D Latch Inference . . . . . .6-19

Inferring Master-Slave Latches. . . . . . . . . . . . . . . . . . . . . . .6-19 Inferring Flip-Flops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-21 Inferring D Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-21

Understanding the Limitations of D Flip-Flop Inference. . . .6-35

Inferring JK Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-37

Inferring T oggle Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . .6-41

Getting the Best Results. . . . . . . . . . . . . . . . . . . . . . . . . . . .6-46 Understanding Limitations of Register Inference. . . . . . . . . . . .6-50 Three-State Inference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-51 Reporting Three-State Inference. . . . . . . . . . . . . . . . . . . . . . . .6-51 Controlling Three-State Inference . . . . . . . . . . . . . . . . . . . . . . .6-51 Inferring Three-State Drivers. . . . . . . . . . . . . . . . . . . . . . . . . . .6-52 Simple Three-State Driver . . . . . . . . . . . . . . . . . . . . . . . . . .6-52

Registered Three-State Drivers . . . . . . . . . . . . . . . . . . . . . .6-57

xi

Understanding the Limitations of Three-State Inference. . . . . .6-60 7.Writing Circuit Descriptions

How Statements Are Mapped to Logic . . . . . . . . . . . . . . . . . . . . . .7-2 Design Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-3 Using Design Knowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-7 Optimizing Arithmetic Expressions . . . . . . . . . . . . . . . . . . . . . .7-7 Arranging Expression T rees for Minimum Delay. . . . . . . . . .7-7

Sharing Common Subexpressions. . . . . . . . . . . . . . . . . . . .7-12 Using Operator Bit-Width Efficiently. . . . . . . . . . . . . . . . . . . . . .7-15 Using State Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-16 Describing State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-19 Minimizing Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-24 Separating Sequential and Combinational Assignments. . . . . .7-27 Don’t Care Inference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-28 Limitations of Using Don’t Care Values . . . . . . . . . . . . . . . . . . .7-29 Differences Between Simulation and Synthesis. . . . . . . . . . . . .7-29 Propagating Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-31 Synthesis Issues. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-31 Feedback Paths and Latches. . . . . . . . . . . . . . . . . . . . . . . . . . .7-32 Synthesizing Asynchronous Designs. . . . . . . . . . . . . . . . . . . . .7-32 Designing for Overall Efficiency. . . . . . . . . . . . . . . . . . . . . . . . . . . .7-34 Describing Random Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-35 Sharing Complex Operators . . . . . . . . . . . . . . . . . . . . . . . . . . .7-35

xii

8.FPGA Compiler II / FPGA Express Directives

Notation for FPGA Compiler II / FPGA Express Directives. . . . . . .8-2 translate_off and translate_on Directives . . . . . . . . . . . . . . . . . . . .8-2 parallel_case Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-4 full_case Directive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-5 state_vector Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-8 enum Directive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-10 Component Implication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-16 A.Examples

Count Zeros—Combinational Version. . . . . . . . . . . . . . . . . . . . . . .A-2 Count Zeros—Sequential Version. . . . . . . . . . . . . . . . . . . . . . . . . .A-5 Drink Machine—State Machine Version . . . . . . . . . . . . . . . . . . . . .A-7 Drink Machine—Count Nickels Version. . . . . . . . . . . . . . . . . . . . . .A-10 Carry-Lookahead Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-12 B.Verilog Syntax

Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-1 BNF Syntax Formalism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-2 BNF Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-3 Lexical Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-12 White Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-13 Comments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-13

xiii

Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-13 Identifiers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-15 Operators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-15 Macro Substitution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-16 include Construct. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-17 Simulation Directives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-18 Verilog System Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-18 Verilog Keywords. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-19 Unsupported Verilog Language Constructs. . . . . . . . . . . . . . . . . . .B-20

xiv

xv

xvi

List of Figures

Figure 1-1FPGA Compiler II / FPGA Express Design Process. . . .1-4 Figure 1-2Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6 Figure 3-1Structural Parts of a Module. . . . . . . . . . . . . . . . . . . . . .3-2 Figure 5-1Schematic of RTL Nonblocking Assignments. . . . . . . . .5-13 Figure 5-2Schematic of Blocking Assignment. . . . . . . . . . . . . . . . .5-14 Figure 6-1SR Latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-9 Figure 6-2 D Latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-13 Figure 6-3 D Latch With Asynchronous Set. . . . . . . . . . . . . . . . . . .6-15 Figure 6-4 D Latch With Asynchronous Reset. . . . . . . . . . . . . . . . .6-16 Figure 6-5 D Latch With Asynchronous Set and Reset . . . . . . . . . .6-18 Figure 6-6T wo-Phase Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-20 Figure 6-7Positive Edge-T riggered D Flip-Flop. . . . . . . . . . . . . . . .6-23 Figure 6-8Negative Edge-T riggered D Flip-Flop . . . . . . . . . . . . . . .6-24 Figure 6-9 D Flip-Flop With Asynchronous Set . . . . . . . . . . . . . . . .6-25 Figure 6-10 D Flip-Flop With Asynchronous Reset . . . . . . . . . . . . . .6-26 Figure 6-11 D Flip-Flop With Asynchronous Set and Reset . . . . . . .6-28

xvii

Figure 6-12 D Flip-Flop With Synchronous Set . . . . . . . . . . . . . . . . .6-30 Figure 6-13 D Flip-Flop With Synchronous Reset . . . . . . . . . . . . . . .6-31 Figure 6-14 D Flip-Flop With Synchronous and Asynchronous Load6-33 Figure 6-15Multiple F lip-Flops W ith A synchronous a nd S ynchronous C ontrols 6-35

Figure 6-16JK Flip-Flop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-39 Figure 6-17JK Flip-Flop With Asynchronous Set and Reset. . . . . . .6-41 Figure 6-18T oggle Flip-Flop With Asynchronous Set . . . . . . . . . . . .6-43 Figure 6-19T oggle Flip-Flop With Asynchronous Reset . . . . . . . . . .6-44 Figure 6-20T oggle Flip-Flop With Enable and Asynchronous Reset.6-46 Figure 6-21Schematic of Simple Three-State Driver . . . . . . . . . . . .6-53 Figure 6-22One Three-State Driver Inferred From a Single Block . .6-55 Figure 6-23T wo Three-State Drivers Inferred From Separate Blocks6-57 Figure 6-24Three-State Driver With Registered Enable . . . . . . . . . .6-58 Figure 6-25Three-State Driver Without Registered Enable. . . . . . . .6-60 Figure 7-1Ripple Carry Chain Implementation . . . . . . . . . . . . . . . .7-4 Figure 7-2Carry-Lookahead Chain Implementation . . . . . . . . . . . .7-5 Figure 7-3Default Expression T ree . . . . . . . . . . . . . . . . . . . . . . . . .7-8 Figure 7-4Balanced Adder T ree (Same Arrival Times for All Signals)7-9 Figure 7-5Expression T ree With Minimum Delay (Signal A Arrives Last) 7-9

Figure 7-6Expression T ree With Subexpressions Dictated by Parentheses 7-10

Figure 7-7Default Expression T ree With 4-Bit T emporary Variable.7-11 Figure 7-8Expression T ree With 5-Bit Intermediate Result. . . . . . .7-12

xviii

Figure 7-9Synthesized Circuit With Six Implied Registers . . . . . . .7-25 Figure 7-10Synthesized Circuit With Three Implied Registers . . . . .7-26 Figure 7-11Mealy Machine Schematic . . . . . . . . . . . . . . . . . . . . . . .7-28 Figure 7-12Circuit Schematic With T wo Array Indexes . . . . . . . . . . .7-37 Figure 7-13Circuit Schematic With One Array Index. . . . . . . . . . . . .7-39 Figure A-1Count Zeros—Combinational Version Block Diagram . .A-4 Figure A-2Count Zeros—Sequential Version Block Diagram . . . . .A-7 Figure A-3Drink Machine—State Machine Version Block Diagram.A-10 Figure A-4Drink Machine—Count Nickels Version Block Diagram .A-12 Figure A-5Carry-Lookahead Adder Block Diagram. . . . . . . . . . . . .A-14

xix

xx

List of T ables

T able 4-1Verilog O perators S upported b y F PGA C ompiler I I /F PGA E xpress 4-3

T able 4-2Operator Precedence . . . . . . . . . . . . . . . . . . . . . . . . . .4-15 T able 4-3Expression Bit-Widths . . . . . . . . . . . . . . . . . . . . . . . . . .4-20 T able 6-1SR Latch T ruth T able (Nand T ype) . . . . . . . . . . . . . . . . .6-8 T able 6-2T ruth T able for JK Flip-Flop. . . . . . . . . . . . . . . . . . . . . . .6-38 T able B-1Verilog Radices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-14 T able B-2Verilog Keywords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-19

xxi

本文来源：https://www.bwwdw.com/article/ctze.html