FPGA可编程逻辑器件芯片XC2VP20-7FFG1152I中文规格书

Spartan-6 FPGA Configuration User Guide

UG380 (v2.11) March 22, 2019

Chapter 5:Configuration Details

Each logical bit of the FUSE_KEY and FUSE_CNTL registers consists of two eFUSE cells (primary and redundant), a flip-flop, and common logic elements for data multiplexing.

eFUSE Registers

A Spartan-6 FPGA has a total of three eFUSE registers. Table 5-18 lists the eFUSE registers in Spartan-6 devices with their sizes and usage. The eFUSE bits are addressed so that the LS

B is shifted in/out first and MSB is last.

eFUSE Control Register (FUSE_CNTL)

This register contains six user programmable bits. These bits are used to select AES key usage and set the read/write protection for eFUSE registers, as detailed in Table 5-19. Bit 0 is shifted in or out first.

The eFUSE bits are one-time programmable (OTP). Once programmed, they cannot be unprogrammed. For example, if access to a register is disabled, it cannot be re-enabled.Table 5-18:

eFUSE Registers

Register Name Size (Bits)Contents

Description

FUSE_KEY (1)

256

Bitstream encryption key

[0:255]

(bit 255 shifted first)

Stores key for use by AES bitstream decryptor. The eFUSE key can be used instead of the key stored in battery-backed SRAM. The AES key is used by the Spartan-6 FPGA decryption engine to load encrypted bitstreams. Depending on the read/write access bits in the CNTL register, the AES key can be programmed and read through the JTAG port.

FUSE_ID 57Device DNA [0:56]

(bit 56 shifted first)

Stores device DNA, a read-only register that is accessed through the JTAG port or the DNA_PORT primitive.FUSE_CNTL (1)

32Control Bits CNTL [31:0](bit 0 shifted first)

Controls key use and read/write access to eFUSE registers. This register can be programmed and read through the JTAG port.

Notes:

1.FUSE_KEY and FUSE_CNTL are only available on 6SLX75/T, 6SLX100/T, and 6SLX150/T devices.

Table 5-19:eFUSE CNTL Register Bits Bit #Name Description

Comments

0:7--Reserved

8

CNTL Security Disable read and write of

the CNTL registers. Redundant with CNTL[12].

The user must program this bit after programming and verifying AES and CNTL registers to prevent any manipulation or readback of these registers.9--

Reserved

10

Key Security

Disables read and write of KEY register. Redundant with CNTL[14].The user must program this bit after programming and verifying AES registers to prevent manipulation or

readback of these registers.11-

-Reserved

Spartan-6 FPGA Configuration User Guide UG380 (v2.11) March 22, 2019

eFUSE

If CNTL[17] is NOT programmed:?Encryption can be enabled or disabled via the BitGen options.

?

The AES key stored in eFUSE or battery-backed SRAM can be selected via the BitGen options.

Once CNTL[17] is programmed, only bitstreams encrypted with the eFUSE key can be used to configure the FPGA.

Configuration memory is blocked after initial configuration if CNTL[16] is programmed. The only way to reconfigure the device is to issue a JTAG JPROG instruction, cycle power, or pulse the PROGRAM_B pin.

12

CNTL Security Disable read and write of

the CNTL registers. Redundant with CNTL[8].

The user must program this bit after programming and verifying AES and CNTL registers to prevent

manipulation or readback of these registers.13--

Reserved

14

Key Security

Disables read and write of KEY register. Redundant with CNTL[10].The user must program this bit after programming and verifying AES registers to prevent manipulation or

readback of these registers.15-

-Reserved

16

aes_exclusive D isables partial

reconfiguration.

This bit requires the FPGA contents to be cleared prior to reconfiguration by issuing a JPROG JTAG instruction, pulsing the PROGRAM_B pin, or cycling power to the FPGA.

Caution!If this bit is programmed,

Return Material Authorization

(RMA) device analysis and debug is limited. An alternative that does not limit RMA analysis is Security Level3.

17cfg_aes_only

The FPGA can only be configured using the AES key stored in the eFUSE KEY register after this bit is programmed.

The FPGA can only be configured by a bitstream that was encrypted with the AES key stored in the eFUSE AES register.

Caution!If this bit is programmed,

the device cannot be used unless the AES key is known. Return Material Authorization (RMA)

returns cannot be accepted if this bit is programmed.

18:31--Reserved

Table 5-19:eFUSE CNTL Register Bits (Cont’d)Bit #Name

Description

Comments

Spartan-6 FPGA Configuration User Guide UG380 (v2.11) March 22, 2019Chapter 6:

Readback and Configuration Verification

Required Data Spacing between MultiBoot Images

Spartan-6 FPGA Configuration User Guide

UG380 (v2.11) March 22, 2019

Spartan-6 FPGA Configuration User Guide UG380 (v2.11) March 22, 2019Chapter 10:Advanced JTAG Configurations

Table 10-3 shows the instruction capture values loaded into the IR as part of an instruction scan sequence.

BYPASS Register

The other standard data register is the single flip-flop BYPASS register. It passes data serially from the TDI pin to the TDO pin during a bypass instruction. This register is initialized to zero when the TAP controller is in the CAPTURE-DR state.

Identification (IDCODE) Register

Spartan-6 devices have a 32-bit identification register called the IDCODE register. The IDCODE is based on IEEE Std 1149.1 and is a fixed, vendor-assigned value that is used to identify electrically the manufacturer and the type of device that is being addressed. This register allows easy identification of the part being tested or programmed by

boundary-scan, and it can be shifted out for examination by using the IDCODE instruction.

The last bit of the IDCODE is always 1 (based on JTAG IEEE 1149.1). The last three hex digits appear as 0x093. IDCODEs assigned to Spartan-6 FPGAs are shown in Table 5-13.JTAG Configuration Register

The JTAG Configuration register is a 16-bit register. This register allows access to the configuration bus and readback operations.

USERCODE Register

The USERCODE instruction is supported in the Spartan-6 family. This register allows a user to specify a design-specific identification code. The USERCODE can be programmed into the device and can be read back for verification later. The USERCODE is embedded into the bitstream during bitstream generation (BitGen -g UserID option) and is valid only after configuration. If the device is blank or the USERCODE was not programmed, the USERCODE register contains 0xFFFFFFFF .BYPASS

111111Enables BYPASS. RESERVE D All other codes

Xilinx reserved instructions.

Table 10-3:

Instruction Capture Values TDI → IR[5] IR[4] IR[3] IR[2] IR[1:0] →TDO

D ON

E INIT(1) ISC_ENABLE

D ISC_D ON

E 0 1 Table 10-2:Spartan-6 FPGA Boundary-Scan Instructions (Cont’d)

Boundary-Scan Command Instruction

Description

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