AD8348-EVALZ;AD8348ARUZ;AD8348ARUZ-REEL7;AD8348ARU-REEL7;AD8

50 MHz to 1000 MHz

Quadrature Demodulator

AD8348 Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 8e355a482f60ddccda38a0ca Fax: 781.461.3113 ?2006 Analog Devices, Inc. All rights reserved.

FEATURES

Integrated I/Q demodulator with IF VGA amplifier Operating IF frequency 50 MHz to 1000 MHz

(3 dB IF BW of 500 MHz driven from R S = 200 Ω) Demodulation bandwidth 75 MHz

Linear-in-decibel AGC range 44 dB

Third-order intercept

IIP3 +28 dBm @ minimum gain (F IF = 380 MHz) IIP3 ?8 dBm @ maximum gain (F IF = 380 MHz) Quadrature demodulation accuracy

Phase accuracy 0.5°

Amplitude balance 0.25 dB

Noise figure 11 dB @ maximum gain (F IF = 380 MHz) LO input ?10 dBm

Single supply 2.7 V to 5.5 V

Power-down mode

Compact, 28-lead TSSOP package

APPLICATIONS

QAM/QPSK demodulator

W-CDMA/CDMA/GSM/NADC

Wireless local loop

LMDS FUNCTIONAL BLOCK DIAGRAM

3

6

7

8

-

1

Figure 1.

GENERAL DESCRIPTION

The AD8348 is a broadband quadrature demodulator with an integrated intermediate frequency (IF), variable gain amplifier (VGA), and integrated baseband amplifiers. It is suitable for use in communications receivers, performing quadrature demodulation from IF directly to baseband frequencies. The baseband amplifiers are designed to interface directly with dual-channel ADCs, such as the AD9201, AD9283, and AD9218, for digitizing and post-processing.

The IF input signal is fed into two Gilbert cell mixers through an X-AMP? VGA. The IF VGA provides 44 dB of gain control.

A precision gain control circuit sets a linear-in-decibel gain char-acteristic for the VGA and provides temperature compensation. The LO quadrature phase splitter employs a pide-by-2 frequency pider to achieve high quadrature accuracy and amplitude balance over the entire operating frequency range.

Optionally, the IF VGA can be disabled and bypassed. In this mode, the IF signal is applied directly to the quadrature mixer inputs via the MXIP and MXIN pins. Separate I- and Q-channel baseband amplifiers follow the baseband outputs of the mixers. The voltage applied to the VCMO pin sets the dc common-mode voltage level at the baseband outputs. Typically, VCMO is connected to the internal VREF voltage, but it can also be connected to an external voltage. This flexibility allows the user to maximize the input dynamic range to the ADC. Connecting a bypass capacitor at each offset compensation input (IOFS and QOFS) nulls dc offsets produced in the mixer. Offset compensation can be overridden by applying an external voltage at the offset compensation inputs.

The mixers’ outputs are brought off-chip for optional filtering before final amplification. Inserting a channel selection filter before each baseband amplifier increases the baseband amplifiers’ signal handling range by reducing the amplitude of high level, out-of-channel interferers before the baseband signal is fed into the I/Q baseband amplifiers. The single-ended mixer output is amplified and converted to a differential signal for driving ADCs.

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TABLE OF CONTENTS

Features..............................................................................................1 Applications.......................................................................................1 Functional Block Diagram..............................................................1 General Description.........................................................................1 Revision History...............................................................................2 Specifications.....................................................................................3 Absolute Maximum Ratings............................................................6 ESD Caution..................................................................................6 Pin Configuration and Function Descriptions.............................7 Equivalent Circuits...........................................................................9 Typical Performance Characteristics...........................................11 VGA and Demodulator.............................................................11 Demodulator Using MXIP and MXIN....................................14 Final Baseband Amplifiers........................................................15 VGA/Demodulator and Baseband Amplifier.........................16 Theory of Operation......................................................................18 VGA..............................................................................................18 Downconversion Mixers...........................................................18 Phase Splitter...............................................................................18 I/Q Baseband Amplifiers...........................................................18 Enable...........................................................................................18 Baseband Offset Cancellation...................................................18 Applications.....................................................................................20 Basic Connections......................................................................20 Power Supply...............................................................................20 Device Enable.............................................................................20 VGA Enable................................................................................20 Gain Control...............................................................................20 LO Inputs.....................................................................................20 IF Inputs......................................................................................20 MX Inputs...................................................................................20 Baseband Outputs......................................................................21 Output DC Bias Level................................................................21 Interfacing to Detector for AGC Operation...............................21 Baseband Filters..........................................................................22 LO Generation............................................................................23 Evaluation Board........................................................................23 Outline Dimensions.......................................................................28 Ordering Guide.. (28)

REVISION HISTORY

4/06—Rev. 0 to Rev. A

Updated Format..................................................................Universal Changes to Specifications................................................................3 Changes to IF Inputs Section........................................................20 Changes to Evaluation Board Section..........................................23 Changes to Table 6..........................................................................27 Changes to Ordering Guide..........................................................28 8/03—Revision 0: Initial Version

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SPECIFICATIONS

V S = 5 V , T A = 25o C, F LO = 380 MHz, F IF = 381 MHz, P LO = ?10 dBm, R S (LO) = 50 Ω, R S (IFIP and MXIP/MXIN) = 200 Ω, unless otherwise noted. Table 1.

Parameter Conditions Min Typ Max Unit OPERATING CONDITIONS LO Frequency Range External input = 2 × LO frequency 100 2000 MHz IF Frequency Range 50 1000 MHz Baseband Bandwidth 75 MHz LO Input Level 50 Ω source ?12 ?10 0 dBm V SUPPLY (V S ) 2.7 5.5 V Temperature Range ?40 +85 °C IF FRONT END WITH VGA IFIP to IMXO (QMXO), ENVG = 5 V, IMXO/QMXO load = 1.5 kΩ Input Impedance Measured differentially across MXIP/MXIN 200||1.1 Ω||pF Gain Control Range 44 dB Maximum Conversion Voltage Gain VGIN = 0.2 V (maximum voltage gain) 25.5 dB Minimum Conversion Voltage Gain VGIN = 1.2 V (minimum voltage gain) ?18.5 dB 3 dB Bandwidth 500 MHz Gain Control Linearity VGIN = 0.4 V (+21 dB) to 1.1 V (?14 dB) ±0.5 dB IF Gain Flatness F IF = 380 MHz ± 5% (VGIN = 1.2 V) 0.1 dB p-p F IF = 900 MHz ± 5% (VGIN = 1.2 V) 1.3 dB p-p Input 1 dB Compression Point (P1dB) VGIN = 0.2 V (maximum gain) ?22 dBm

VGIN = 1.2 V (maximum gain) +13 dBm Second-Order Input Intercept (IIP2) IF1 = 385 MHz, IF2 = 386 MHz

+3 dBm each tone from 200 Ω source, 65 dBm VGIN = 1.2 V (minimum gain)

?42 dBm each tone from 200 Ω source, 18 dBm

VGIN = 0.2 V (maximum gain) Third-Order Input Intercept (IIP3) IF1 = 381 MHz, IF2 = 381.02 MHz Each tone 10 dB below P1dB from 200 Ω source,

28 dBm VGIN = 1.2 V (minimum gain)

Each tone 10 dB below P1dB from 200 Ω source,

?8 dBm

VGIN = 0.2 V (maximum gain)

LO Leakage Measured at IFIP , IFIN ?80 dBm Measured at IMXO/QMXO (LO = 50 MHz) ?60 dBm Demodulation Bandwidth Small signal 3 dB bandwidth 75 MHz Quadrature Phase Error 1LO = 380 MHz (LOIP/LOIN 760 MHz) ?0.7 ±0.1 +0.7 Degrees vs. temperature ?0.0032 °/°C vs. baseband frequency (dc to 30 MHz) +0.01 °/MHz

I/Q Amplitude Imbalance 1

?0.3 ±0.05 +0.3 dB vs. temperature 0 dB/°C vs. baseband frequency (dc to 30 MHz) ±0.0125 dB Noise Figure (Double Sideband) Maximum gain, from 200 Ω source,

F IF = 380 MHz

10.75 dB Mixer Output Impedance 40 Ω Capacitive Load Shunt from IMXO, QMXO to VCMO 0 10 pF Resistive Load

Shunt from IMXO, QMXO to VCMO 200 1.5 kΩ Mixer Peak Output Current 2.5 mA

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Parameter Conditions Min Typ Max Unit IF FRONT END WITHOUT VGA From MXIP , MXIN to IMXO (QMXO),

ENVG = 0 V, IMXO/QMXO load = 1.5 kΩ

Input Impedance Measured differentially across MXIP/MXIN 200||1.5 Ω||pF

Conversion voltage Gain 10.5 dB

3 dB Output Bandwidth 75 MHz

IF Gain Flatness F IF = 380 MHZ ± 5% 0.1 dB p-p

F IF = 900 MHZ ± 5% 0.15 dB p-p

Input 1 dB Compression Point (P1dB) ?4 dBm

Third-Order Input Intercept (IIP3) IF1 = 381 MHz, IF2 = 381.02 MHz 14 dBm

Each tone 10 dB below P1dB from

200 Ω source

LO Leakage Measured at MXIP/MXIN ?70 dBm

Measured at IMXO, QMXO ?60 dBm

Demodulation Bandwidth Small signal 3 dB bandwidth 75 MHz

Quadrature Phase Error LO = 380 MHz (LOIP/LOIN 760 MHz,

single-ended)

?2 ±0.5 +2 Degrees I/Q Amplitude Imbalance 0.25 dB

Noise Figure (Double Sideband) From 200 Ω source, F IF = 380 MHz 21 dB

I/Q BASEBAND AMPLIFIER From IAIN to IOPP/IOPN and QAIN to QOPP/

QOPN, R LOAD = 2 kΩ, single-ended to ground

Gain 20 dB Bandwidth 10 pF differential load 125 MHz

Output DC Offset (Differential) LO leakage offset corrected using 500 pF

capacitor on IOFS, QOFS (V IOPP ? V IOPN )

?50 ±12 +50 mV Output Common-Mode Offset (V IOPP + V IOPN )/2 ? VCMO ?75 ±35 +75 mV

Group Delay Flatness 0 MHz to 50 MHz 3 ns p-p

Input-Referred Noise Voltage Frequency = 1 MHz 8 nV/√Hz

Output Swing Limit (Upper) V S ?1 V

Output Swing Limit (Lower) 0.5 V

Peak Output Current 1 mA

Input Impedance 50||1 kΩ||pF

Input Bias Current 2 μA

RESPONSE FROM IF AND MX INPUTS TO BASEBAND AMPLIFIER OUTPUT IMXO and QMXO connected directly to

IAIN and QAIN, respectively

Gain From MX I P/MX I N 30.5 dB From IFIP/IFIN, VGIN = 0.2 V 45.5 dB

From IFIP/IFIN, VGIN = 1.2 V 1.5 dB

CONTROL INPUT/OUTPUTS

VCMO Input Range V S = 5 V 0.5 1 4 V

V S = 2.7 V 0.5 1 1.7 V

VREF Output Voltage 0.95 1 1.05 V

Gain Control Voltage Range VGIN 0.2 1.2 V

Gain Slope ?55 ?50 ?45 dB/V

Gain Intercept Linear extrapolation back to theoretical

gain at VGIN = 0 V

55 61 67 dB Gain Control Input Bias Current 1 μA

LO INPUTS

LOIP Input Return Loss LOIN ac-coupled to ground

(760 MHz applied to LOIP)

?6 dB

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Parameter Conditions Min Typ Max Unit POWER-UP CONTROL

ENBL Threshold Low Low = standby 0 V S /2 1 V

ENBL Threshold High High = enable V S ? 1 V S /2 V S V

Input Bias Current 2 μA

Power-Up Time Time for final baseband amplifiers to be

within 90% of final amplitude

45 μs Power-Down Time Time for supply current to be <10% of

enabled value

700 ns POWER SUPPLIES VPOS1, VPOS2, VPOS3

Voltage 2.7 5.5 V Current (Enabled) V S = 5 V, V ENBL = 5 V 38 48 58 mA

Current (Standby) V S = 5 V, V ENBL = 0 V 75 μA

1 These parameters are guaranteed but not tested in production. Limits are ±6 Σ from the mean.

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ABSOLUTE MAXIMUM RATINGS

Table 2. Parameter Rating Supply Voltage on VPOS1, VPOS2, VPOS3 Pins 5.5 V LO Input Power 10 dBm (re: 50 Ω) IF Input Power 18 dBm (re: 200 Ω) Internal Power Dissipation 450 mW θJA 68°C/W

Maximum Junction Temperature 150°C Operating Temperature Range ?40°C to +85°C

Storage Temperature Range ?65°C to +125°C Lead Temperature (Soldering, 60 sec) 300°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

LOIP

VPOS1

IOPN IOPP VCMO IAIN COM3IMXO COM2IFIN IFIP VPOS2IOFS VREF 03678-002

Figure 2. 28-Lead TSSOP Pin Configuration

Table 3. Pin Function Descriptions—28-Lead TSSOP

Pin No. Mnemonic Description

Equivalent Circuit 1, 28

LOIP , LOIN

LO Inputs. For optimum performance, these inputs should be ac-coupled and driven differentially. Differential drive from single-ended sources can be achieved via a balun. To obtain a broadband 50 Ω input impedance, connect a 60.4 Ω shunt resistor between LOIP and LOIN. Typical input drive level is equal to ?10 dBm.

A

2, 12, 20 VPOS1, VPOS2, VPOS3 Positive Supply for LO, IF, and Biasing and Baseband Sections, Respectively. These pins

should be decoupled with 0.1 μF and 100 pF capacitors.

3, 4, 25, 26 IOPN, IOPP , QOPP , QOPN I- and Q-Channel Differential Baseband Outputs. Typical output swing is equal to 2 V p-p

differential. The dc common-mode voltage level on these pins is set by the voltage on VCMO.

B 5 VCMO Baseband D

C Common-Mode Voltage. The voltage applied to this pin sets the dc

common-mode levels for all the baseband outputs and inputs (IMXO, QMXO, IOPP , IOPN, QOPP , QOPN, IAIN, and QAIN). This pin can be connected either to VREF or to a reference voltage from another device (typically an ADC).

C

6, 23 IAIN, QAIN I- and Q-Channel Baseband Amplifier Inputs. The single-ended signals on these pins are

referenced to VCMO and must have a dc bias equal to the dc voltage on the VCMO pin. If IMXO (QMXO) is dc-coupled to IAIN (QAIN), biasing will be provided by IMXO (QMXO). If an ac-coupled filter is placed between IMXO and IAIN, these pins can be biased from the source driving VCMO through a 1 kΩ resistor. The gain from IAIN/QAIN to the differential outputs (IOPP/IOPN and QOPP/QOPN) is 20 dB.

D

7, 22 COM3 Ground for Biasing and Baseband Sections. 8, 21 IMXO, QMXO I- and Q-Channel Mixer Baseband Outputs. These are low impedance (40 Ω) outputs whose

bias levels are set by the voltage applied to the VCMO pin. These pins are typically connected to IAIN and QAIN, respectively, either directly or through a filter. Each output can drive a maximum current of 2.5 mA.

H

9 COM2 IF Section Ground. 10, 11 IFIN, IFIP IF Inputs. IFIN should be ac-coupled to ground. The single-ended IF input signal should

be ac-coupled into IFIP . The nominal differential input impedance of these pins is 200 Ω. For a broadband 50 Ω input impedance, a minimum-loss L pad should be used; R SERIES = 174 Ω, R SHUNT = 57.6 Ω. This provides a 200 Ω source impedance to the IF input. However, the AD8348 does not necessarily require a 200 Ω source impedance, and a single shunt 66.7 Ω resistor can be placed between IFIP and IFIN.

E

13, 16 IOFS, QOFS I- and Q-Channel Offset Nulling Inputs. DC offsets on the I-channel mixer output (IMXO)

can be nulled by connecting a 0.1 μF capacitor from IOFS to ground. Driving IOFS with a fixed voltage (typically a DAC calibrated such that the offset at IOPP/IOPN is nulled) can extend the operating frequency range to include dc. The QOFS pin can likewise be used to null offsets on the Q-channel mixer output (QMXO).

F

14 VREF Reference Voltage Output. This output voltage (1 V) is the main bias level for the device

and can be used to externally bias the inputs and outputs of the baseband amplifiers. The typical maximum drive current for this output is 2 mA.

G

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Pin No. Mnemonic Description Equivalent

Circuit 15 ENBL Chip Enable Input. Active high. Threshold is equal to V S /2. D 17 VG I N Gain Control Input. The voltage on this pin controls the gain on the IF VGA. The gain control voltage range is from 0.2 V to 1.2 V and corresponds to a conversion gain range

from +25.5 dB to ?18.5 dB. This is the gain to the output of the mixers (that is, IMXO and

QMXO). There is an additional 20 dB of fixed gain in the final baseband amplifiers (IAIN to

IOPP/IOPN and QAIN to QOPP/QOPN). Note that the gain control function has a negative

sense (that is, increasing voltage decreases gain).

D

18, 19 MXIP , MXIN Auxiliary Mixer Inputs. If ENVG is low, the IFIP and IFIN inputs are disabled and MXIP and MXIN are enabled, allowing the VGA to be bypassed. The auxiliary mixer inputs are fully

differential inputs that should be ac-coupled to the signal source.

I

24 ENVG Active High VGA Enable. When ENVG is high, IFIP and IFIN inputs are enabled and MXIP and MXIN inputs are disabled. When ENVG is low, MXIP and MXIN inputs are enabled and

IFIP and IFIN inputs are disabled.

D

27 COM1 LO Section Ground.

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EQUIVALENT CIRCUITS

LOIN LOIP

03678-003

Figure 3. Circuit A VCMO

VPOS3

IOPP , IOPN,QOPP , QOPN 03678-004

Figure 4. Circuit B

VCMO

03678-005

Figure 5. Circuit C 03678-006

Figure 6. Circuit D

VPOS2

IFIP

IFIN

03678

-007

Figure 7. Circuit E

03678-008

Figure 8. Circuit F

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03678-009

Figure 9. Circuit G

03678-010

Figure 10. Circuit H

03678-011

Figure 11. Circuit I

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