MSP430与TLC549 TL1549模数转换器的连接

MSP430单片机的程序设计

Application Report

SLAA112 – November 2000

Interfacing the MSP430 and TLC549/1549 A/D ConvertersMark Buccini

ABSTRACT

This application report describes how to interface an MSP430 mixed-signalmicrocontroller with TLC549 and TLV1549 3-volt A/D converters. This report is written forthe MSP430x11x(1) family, but can be adapted to any MSP430 derivative.

Mixed Signal Controllers

Figure 1. TLC549 – MSP430 Demonstration Circuit

1

MSP430单片机的程序设计

SLAA112

Principle of Operation

Using three digital I/O pins, the MSP430F1121 drives the TLC549 A/D conversion using asynchronous serial interface. In this application report, MSP430 I/O pins P2.0 and P2.1 areconfigured as outputs using the P2 direction register (P2DIR) and set/reset using the P2 outputregister (P2OUT). Pin P2.0 interfaces with the TLC549 chip select (CS) pin P2.1 with the

TLC549 input-output clock (I/O CLK). Conversion data from the TLC549 data out (DO) are readon pin P2.3. The choice between P2.0, P2.1, and P2.3 is arbitrary. Any MSP430 I/O pin can beused to drive the TLC549.When CS is high, DO is in a high-impedance state and I/O CLK inactive. To begin theconversion, the MSP430 brings CS low. To drive a complete conversion, the MSP430generates a total of eight clock pulses on P2.1 which are applied to the TLC549 I/O CLK. AfterCS has been brought low, the most significant bit (MSB) from the previous conversion appearson DO. The MSP430 reads the conversion data on DO on pin P2.3 and serially shifts the datainto a register ADCDATA (R11). The falling edge of the first four clock pulses shift out the

second, third, and fourth most significant bits of the previous conversion. The falling edge of thefourth clock begins the sample function of the analog signal present at the analog terminal of theTLC549. Three more clock pulses are applied to I/O CLK shifting out the least three most-significant bits from the previous conversion. The falling edge of the final (eighth) clock pulseterminates the TLC549 sample function and the hold and conversion cycle begins. The

conversion cycle is timed internally by the TLC549 internal oscillator independent of any externalclocking, and the conversion is complete in 17uS. CS is brought high during the conversionprocess, and DO returns to a high impedance state. At least 17µs must be allowed before thenext conversion sequence or the TLC549 conversion code will be corrupted.

A complete MSP430F1121–TLC549 software example, fet_549.s43, is provided. As coded, thesubroutine MEAS_549 requires 150 MCLK cycles and 31 bytes of assembler code including thesubroutine call. The entire example requires 60 bytes of code. In the included example, thewatchdog is disabled and the stack pointer and MSP430 I/Os after system reset are initialized.The subroutine MEAS_549 is called to drive a TLC549 conversion sequence with the 8-bitconversion code returned in ADCDATA. A register Counter (R12) is also temporarily used tocount data bits during the subroutine call. The register definitions for ADCDATA and Counter arearbitrary; any CPU registers, RAM bytes, or even the stack can be used for these registers.Important: Please review the current MSP430x11x1 and TLC549 datasheets and MSP430Users Guide for device electrical and timing specifications.

Modification for Use With TLV1549

If greater resolution is required, a pin-compatible TLV1549 10-bit converter can be used. Oneline of the subroutine source MEAS_549 must be modified to support a 10-bit converter. A totalof 10 clock pulses are needed and 10 bits of data are shifted into ADCDATA.

mov.w #10,Counter ; 10 data bits

2Interfacing the MSP430 and TLC549/1549 A/D Converters

MSP430单片机的程序设计

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1. MSP430x11x1 Datasheet (SLAS241)

2. MSP430x1xx Users Guide (SLAU049)

3. TLC548, TLC549 Datasheet (SLAS067)

Interfacing the MSP430 and TLC549/1549 A/D Converters3References

MSP430单片机的程序设计

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Source code for FET_549.s43 Example

4Interfacing the MSP430 and TLC549/1549 A/D Converters

MSP430单片机的程序设计

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Interfacing the MSP430 and TLC549/1549 A/D Converters5

MSP430单片机的程序设计

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