SOFIA 3G-R Display开发说明文档V1.1

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SOFIA 3G-R Display Development Guide

（技术部，图形显示组）

文件状态： [ ] 正在修改 [√] 正式发布当前版本：作者：完成日期：审核：完成日期： V1.1 zwl 2016-01-06 方赛鸿 2016-01-13

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Fuzhou Rockchips Semiconductor Co . , Ltd

(版本所有,翻版必究)

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版本历史

版本号 V1.0 V1.1 作者 zwl zwl 修改日期 2015-04-01 2016-01-06 初始版本修改说明备注 1.新增hdmi配置及调试节点说明注意这些新2.新增multiple panel使用和配置说明功能是基于2015.12.073.新增regulator控制panel power 发布的on/power off的使用说明 4.更新agold backlight配置 5.更新及新增一些其他新功能的配置说明

SDK代码 2

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目录 ...................................................................................................................................................................... 3 1 LCD硬件原理 .................................................................................................................................................. 5 2 显示驱动代码框架 .......................................................................................................................................... 9 2.1 CODE STRUCTURE ....................................................................................................................................... 9 2.2 SOURCE CODE DESCRIPTION ..................................................................................................................... 10 3 DTS配置说明 ................................................................................................................................................ 11 3.1 FB NODE .................................................................................................................................................... 11 3.2 SCREEN NODE ............................................................................................................................................ 12 3.3 LCD PANEL DTSI ....................................................................................................................................... 14 3.3.1 MIPI DSI Parameter ...................................................................................................................... 16 3.3.2 Display-timings ................................................................................................................................. 17 3.3.3 Panel Power On/Off Sequence ...................................................................................................... 20 3.3.4 Panel Initial Command Sequence ................................................................................................ 23 3.3.5 Panel-detect .................................................................................................................................... 24 3.4 VOP NODE .................................................................................................................................................. 26 3.5 MIPI/LVDS NODE ........................................................................................................................................ 29 3.6 BACKLIGHT NODE ...................................................................................................................................... 29 3.6.1 XGOLD PWM ................................................................................................................................... 29 3.6.2 AGOLD PWM ................................................................................................................................... 31 3.7 HDMI DTS配置说明 ................................................................................................................................ 32 3.7.1 RK616 HDMI .................................................................................................................................... 32 3.7.2 ITE66121 HDMI ............................................................................................................................... 34

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3.8 MULTIPLE PANEL配置说明 ...................................................................................................................... 34 3.9 USE REGULATOR POWER CONTROL .......................................................................................................... 40 3.10 DELAY BEFORE BACKLIGHT .................................................................................................................... 41 4 更换开机LOGO及充电动画 ...................................................................................................................... 42 4.1 LOADER LOGO ........................................................................................................................................... 42 4.2 LOADER 充电动画 ................................................................................................................................... 42 4.3 KERNEL LOGO ............................................................................................................................................ 43 4.4 ANDROID充电动画 .................................................................................................................................. 43 5 调试节点说明 ................................................................................................................................................ 44

5.1.1 fb节点 .............................................................................................................................................. 44 5.1.2 hdmi节点 ......................................................................................................................................... 46 附录： ................................................................................................................................................................ 48 A1 LVDS FORMAT的选择 ............................................................................................................................ 48 A2 利用LUT功能改善显示效果 ................................................................................................................... 50

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1 LCD硬件原理

图（1）给出了TFT 屏的典型时序。时序图中的VCLK、HSYNC 和VSYNC 分别为像素时钟信号（用于锁存图像数据的像素时钟）、行同步信号和帧同步信号，VDEN 为数据有效标志信号，VD 为图像的数据信号。

图（1）行场控制的LCD 时序图

上图的VSYNC是帧同步信号，每发出一个脉冲，都意味着新的一屏图像数据开始发送。HSYNC是行同步信号，每发出一个脉冲都表明新的一行图像资料开始发送。在帧同步以及行同步的头尾都必须留有回扫时间。

图（2）给出了LCD 控制器中应该设置的TFT屏的时序参数，其中的上边界(upper margin，vertical back porch)和下边界(low margin，vertical front porch)即为帧切换的回扫时间，左边界(left margin，horizontal back porch)和右边界(right margin，horizontal front porch)即为行切换的回扫时间，水平同步(hsync，horizontal pulse width)和垂直同步(vsync，vertical pulse width)分别是行和帧同步本身需要的时间。横向分辨率（xres，Horizontal valid data）和纵向分辨率（yres，vertical valid data）。

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Vsync len Upper margin Left margin Xres 横向分辨率 Right margin Hsync Yres 纵向分辨率 Lower margin 图（2）LCD中的时序参数

图（3）是一个典型的LCD的timing characteristics：

图（3）timing characteristics

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从表中我们可以得到如下参数：

Left_margin = HBP（Horizontal Back Porch） = 16; Right_margin = HFP（Horizontal Front Porch） = 210; Hsync = HPW（Horizontal Pulse Width ）= 30; Xres = HVD(Horizontal Valid) = 800; Upper_margin = VBP（Vertical Back Porch） = 10; low_margin = VFP（Vertical Front Porch） = 22; Vsync = VPW（Vertical Pulse Width） = 13; Yres = VVD（Vertical Valid） = 480;

而且这些参数满足如下公式：

Left_margin + right_margin + hsync + xres = horizontal period Upper_margin + low_margin + vsync + yres = vertical period

这些参数都要写入相应的LCDC 寄存器里面。

在LCD驱动中，还有一个重要的参数----点时钟，即dot clock，在LCD的data sheet里面一般是MHZ，名称为PCLK或者DCLK。例如，如果为28.37516 MHz，那么画1个像素需要35242 ps（皮秒）：

1/(28.37516E6 Hz) = 35.242E-9 s

如果屏幕的分辨率是640×480，显示一行需要的时间是：

640*35.242E-9 s = 22.555E-6 s

每条扫描线是640，但是水平回扫和水平同步也需要时间，假设水平回扫同步需要272 个像素时钟，因此，画一条扫描线完整的时间是：

(640+272)*35.242E-9 s = 32.141E-6 s 可以计算出水平扫描率大约是31kHz： 1/(32.141E-6 s) = 31.113E3 Hz

完整的屏幕有480 线，但是垂直回扫和垂直同步也需要时间，假设垂直回扫和垂直同步需要49 个象素时钟，因此，画一个完整的屏幕的时间是：

(480+49)*32.141E-6 s = 17.002E-3 s 可以计算出垂直扫描率大约是59kHz： 1/(17.002E-3 s) = 58.815 Hz

这意味着屏幕数据每秒钟大约刷新59 次。

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由此可以得到如下公式：

刷新率 =dotclock/(（xres+left_margin+right_margin+hsync）*(yres+upper_margin+low_margin+vsync))

在linux frame buffer 子系统中，还有用到一个参数---像素时钟即pixclock。 Pixclock = 1/dotclock

对于LCDC驱动来说，就是要根据屏幕的这些时序参数（DCLK、HSYNC、HBP、HVD、HFP、VSYNC、VBP、VVD、VFP）送出符合要求的信号。

这里需要说明的一点是，Android的最高刷新频率为60fps，所以我们最好保证LCDC的刷新频率也为60fps，根据文档第一部分介绍的LCDC的刷新频率计算公式可以知道，LCDC的刷新频率和DCLK成正比，和水平方向与垂直方向参数之和的乘积成反比。根据屏幕的datasheet我们可以看出，对于一款屏幕H_VD/V_VD对应屏幕的分辨率，这两个数值是固定的不能修改，BP、FP、PW的值都有一个最大值和最小值的取值范围，所以当我们的DCLK分配不到想要的频率的时候，可以适当的调整BP、FP、PW，使得LCDC的刷新率尽可能的接近60FPS。

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2 显示驱动代码框架

2.1 Code Structure

Rockchip use fbdev based now, base on normal fb driver, add many custom ioctl to Optimization system. The major ioctl is FBIOSET_CONFIG_DONE.

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2.2 Source Code Description

显示驱动框架被分为FB框架相关的部分、VOP(LCDC)控制器相关的部分、LCD屏幕相关的部分、LVDS控制器相关部分、MIPI DSI控制器相关部分。代码目录结构及描述如下表所示

Source Code rockchip/rockchip_disp_drv.c rockchip/rockchip_disp_drv.h rockchip/rockchip_fb.c rockchip/rockchip_fb_sysfs.c include/llinux/rockchip_fb.h rockchip/rockchip_screen.c Include/linux/rockchip_screen.h rockchip/vop/rockchip_vop.c rockchip/vop/rockchip_vop.h nanosilicon/nanosilicon_lvds.c nanosilicon/nanosilicon_lvds.h xgold/dsi/dsi/dsi_device.c xgold/dsi/dsi/dsi_device.h MIPI DSI driver: Description Display platform driver entry: Control the the initial sequence of all display module contain fb/screen/lvds/mipi/hdmi/vop Framebuffer driver(Hardware abstraction): It is bridge between hardware and userspace, Provide the interface to handle vop controller Screen device driver: Parse the parameters of screen information from dts file about display timing and power control. VOP hardware driver: Operate the register of vop controller LVDS hardware driver:

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xgold/dsi/dsi/dsi_display.c xgold/dsi/dsi/dsi_display.h xgold/dsi/dsi/dsi_hwreg.c xgold/dsi/dsi/dsi_hwreg.h xgold/dsi/dsi/dsi_irqs.c xgold/dsi/dsi/dsi_dts.c xgold/dsi/dsi/dsi_dts.h rockchip/hdmi/rk_hdmi_task.c rockchip/hdmi/rk_hdmi_lcdc.c rockchip/hdmi/rk_hdmi_edid.c rockchip/hdmi/rk_hdmi_sysfs.c rockchip/hdmi/rk_hdmi.h rockchip/hdmi/chips/rk61x/rk61x_hdmi.c rockchip/hdmi/chips/rk61x/rk61x_hdmi.h rockchip/hdmi/chips/rk61x/rk61x_hdmi_hw.c rockchip/hdmi/chips/rk61x/rk61x_hdmi_hw.h rockchip/hdmi/chips/rk61x/rk61x_hdmi_hdcp.c rockchip/hdmi/chips/rk61x/rk61x_hdcp.c rockchip/hdmi/chips/rk61x/rk61x_hdcp.h

RK616/RK618 HDMI driver and include its HDCP driver HDMI common and core driver 3 Dts配置说明

3.1 fb node

dts文件中的fb node配置如下： fb { };

compatible = \

rockchip,disp-mode = ; rockchip,loader-logo-on = <1>; rockchip,loader-charge-on = <1>; rockchip,ion-drv = \

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Property rockchip,disp-mode Description 单显或双显模式 Value 默认配置：单显模式，注意sofia3gr只带1个VOP,请配置为该模式单VOP双显模式，外接RK616（或者RK618）实现HDMI双显，配置为该模式双VOP双显模式（3GR不支持该模式） rockchip,loader-logo-on Loader logo显示标志 <1> 开启loader logo显示; <0> 关闭loader logo显示，启用kernel logo显示 rockchip,loader-charge-on Loader charge显示标志 <1> 开启loader充电动画显示;

<0> 关闭loader充电动画显示，充电模式直接进android充电动画 3.2 screen node

screen { };

Screen节点各属性详细说明如下表所示：

#include \

compatible = \pm,class-name = \pm,user-name = \pm,state-D0 = \pm,state-D3 = \

intel,display-gpio-reset = <&xgold_pmx_gpio 36 0>;

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Property pm,class-name = \pm,user-name = \pm,state-D0 = \pm,state-D3 = \ Description lcd pm state用于切换display的power (D0为打开状态，D3为关闭状态)，这一组pm是成对出现的，默认包括：VDD_MIPI_DSI/VDD_LVDS_1V8/VDD_DIF_LCD和VCC_LCD Value 如果不关心VCC_LCD的时序的话，按照上表默认的配置即可。如果屏对VCC_LCD有严格的要求的话，可把VCC_LCD独立为lcd_vdd0进行控制，把整组PM修改为 pm,class-name = \pm,user-name = \pm,state-D0 = \pm,state-D3 = \pm,state-D0i0 = \pm,state-D0i1 = \pm,state-D3i0 = \pm,state-D3i1 = \ 注：最多支持4个vdd用于屏的power控制： lcd_vdd0、lcd_vdd1、lcd_vdd2、lcd_vdd3分别对应dts中的vdd_prim_display_reg、vdd_lcd_dsi_reg、vdd_lcd_vdd2_reg、vdd_lcd_vdd3_reg配置的pmu-domain 控制时序分别对应lcd-xxx.dtsi文件中的gpio-power-on/off节点的regulator-type为”lcd_vdd0”、”lcd_vdd1”、”lcd_vdd2”、”lcd_vdd3”的控制节点 intel,display-gpio-reset 目前最多支持4个power控制脚： pin和vpwr pin <&xgold_pmx_gpio 36 0> 这里是配置lcd屏的reset pin脚为xgold的GPIO36，据实际的硬件设计配置为相应的gpio脚）同上同上 reset pin、vhigh pin、vlow 第3个参数0：表示初始化为高，（请根intel,display-gpio-vhigh 注：每个GPIO脚对应的操 intel,display-gpio-vlow 作时序在lcd-xxx.dtsi中配置

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intel,display-gpio-vpwr #include \

同上请根据硬件实际接的lcd屏，include对应lcd屏的panel参数配置文件lcd-xxx.dtsi DTS中screen node的配置属于board级的配置，与屏无关只跟硬件设计有关，而与屏相关的配置都在lcd-xxx.dtsi中。

3.3 LCD panel dtsi

在arch/x86/boot/dts/xgold/display/目录下放置了不同的lcd屏的panel参数配置文件（请参考目录中已有的dtsi文件新建你所需要的lcd-xxx.dtsi文件），lcd-xxx.dtsi中包含display-timings的参数、dsi参数、lcd屏的power on时序和power off时序，以及mipi屏的initial command等配置.

下面给出了一个MIPI屏的lcd-xxx.dtsi配置信息，如果是LVDS屏的话一般只有display-timings、gpio-power-on、gpio-power-off信息。

福州瑞芯微电子有限公司 auo-lp055apkp153a { compatible = \ intel,display-fps = <60>; intel,display-dc-clkrate = <297000000>; intel,display-if-nblanes = <4>; intel,display-vid-mode = \ intel,display-vid-id = <0>; intel,display-eot = <1>; intel,display-gate = <1>; display-timings { native-mode = <&timing0>; timing0: timing0 { screen-type = ; out-face = ; color-mode = ; clock-frequency = <71421000>; hactive = <720>; vactive = <1280>; hback-porch = <80>; hfront-porch = <80>; hsync-len = <15>; vback-porch = <20>; vfront-porch = <20>; vsync-len = <10>; hsync-active = <0>; vsync-active = <0>; de-active = <0>; pixelclk-active = <0>; swap-rb = <0>; swap-rg = <0>; swap-gb = <0>; }; }; panel-detect { /* 默认不需要panel-detect节点使用multi panle时需配置该节点 */ intel,id-detect-method = \ intel,id-verification = <0x40>; intel,cmd-type = <0x14>; intel,cmd-data = <0xDA 0x40>; /* panel id */ intel,cmd-lp = <1>; }; gpio-power-on { power_en { intel,gpio-type = \ intel,gpio-value-delay = <1 0>; }; reset1 { intel,gpio-type = \ intel,gpio-value-delay = <0 5>; }; reset2 { intel,gpio-type = \ intel,gpio-value-delay = <1 10>; }; }; gpio-power-off { reset { intel,gpio-type = \ intel,gpio-value-delay = <0 20>; }; power_en { intel,gpio-type = \ intel,gpio-value-delay = <0 10>; }; }; cmd-init { cmd1 { intel,cmd-type = <0x15>; intel,cmd-data = <0x00 0x00>; intel,cmd-lp = <1>; }; //cmd2 ... cmd3 ... }; cmd-sleep-in { display-off { intel,cmd-type = <0x05>; intel,cmd-data = <0x28>; intel,cmd-delay = <20>; intel,cmd-lp = <1>; }; sleep-in { intel,cmd-type = <0x05>; intel,cmd-data = <0x10>; intel,cmd-delay = <10>; intel,cmd-lp = <1>; }; }; cmd-sleep-out { sleep-out { intel,cmd-type = <0x05>; intel,cmd-data = <0x11>; intel,cmd-delay = <120>; intel,cmd-lp = <1>; }; display-on { intel,cmd-type = <0x05>; intel,cmd-data = <0x29>; intel,cmd-delay = <10>; intel,cmd-lp = <1>; }; }; }; 15

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3.3.1 MIPI DSI Parameter

intel,display-fps = <60>;

intel,display-dc-clkrate = <297000000>; intel,display-if-nblanes = <4>; intel,display-vid-mode = \ intel,display-vid-id = <0>; intel,display-eot = <1>; intel,display-gate = <1>;

Property intel,display-fps intel,display-dc-clkrate Description 屏幕刷新率 DSI Controller Clock频率 Pixel Clock频率的2倍 Value 默认配置：<60> 默认配置：<297000000> 注：具体参考3.4节，需配置为VOP节点的uhigh_perf_freq属性相同的值 intel,display-if-nblanes DSI data lane的个数默认配置：<4> 可选择1~4个lane 注：请根据lcd屏的datasheet进行配置 intel,display-vid-mode Video mode的数据传输模式默认配置：\\同步脉冲模式 \模式 \同步事件模式注：某些不支持burst模式的MIPI屏请选择pulses模式 intel,display-vid-id intel,display-eot Video id Enable the end-of-transmission packet after each high-speed transmission 默认配置：<0> 默认配置：<1>（允许发送eot包） intel,display-gate Enable clock gating(HS TX clock will be deactivated 默认配置：<1> （使用discontinuous clock）如果MIPI屏不支持非连续clock的话，请关闭clock gating. between HS transmissions) 注：开启clock gating会降低功耗.

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3.3.2 Display-timings

display-timings {

native-mode = <&timing0>; timing0: timing0 {

screen-type = ; out-face = ; color-mode = ; width = <69>; height = <122>;

clock-frequency = <71421000>; hactive = <720>; vactive = <1280>; hback-porch = <80>; hfront-porch = <80>; hsync-len = <15>; vback-porch = <20>; vfront-porch = <20>; vsync-len = <10>; hsync-active = <0>; vsync-active = <0>; de-active = <0>; pixelclk-active = <0>; swap-rb = <0>; swap-rg = <0>; swap-gb = <0>; }; };

注意：如果使用multiple panle的话，另外一个lcd panel的timing0节点不能重名以免编译出错，例如可以命名为timing1

Display-timings节点主要配置的是屏的类型、timing和pixel clock等信息，各个属性说明详见下表：

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Property screen-type Description 屏幕类型 Value LVDS屏 RGB屏 MIPI屏 lvds-format LVDS的数据格式(只有LVDS的屏幕需要设置该格式) 注：如何选择lvds format详见附录A1说明. out-face 屏幕的接线格式，表示屏幕采用多少位的接线方式 24bit的屏幕 18bit的屏幕且数据线分别接在每种单元色的高六位 18bit的屏幕且数据线接在LCDC的低18位注：请根据lcd屏的datasheet进行配置该属性如果设置的不正确，比如24bit的接法，定义成OUT_D888_P666或者OUT_P666就有可能出现色阶。需要注意的是，很多屏幕，都有管脚接高电平还是低电平来控制该屏幕使用18BIT还是24BIT，这个在实际开发的过程中要留意。 width LCD屏active area的宽度请根据屏的尺寸填写，单位为mm 注：该值会用于计算上报的XDPI值 height LCD屏active area的高度请根据屏的尺寸填写，单位为mm 注：该值会用于计算上报的YDPI值 clock-frequency VOP理论需要的dclk的频率请根据下列公式计算： Htotal = hbp + hsync + hactive + hfp Vtotal = vbp + vsync + vactive + vfp clock-frequency = Htotal x Vtotal x Fps 例如以上配置的计算为： clock-frequency = (80 + 15+ 720 + 80) x (20 + 10 + 1280 + 20) x 60 = 71421000

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hactive vactive hback-porch hfront-porch hsync-len 屏幕水平分辨率屏幕纵向分辨率 Horizontal Blanking: 左边界右边界屏幕水平同步脉宽屏的固定值屏的固定值一般有最小值和最大值限制，具体取值范围请根据参照屏的datasheet 注：对于MIPI屏，由于DSI的timing配置还有以下限制： hback-porch <= 85 hfront-porch <= 85 hsync-len <= 85 vback-porch vfront-porch vsync-len Vertical Blanking: 上边界下边界屏幕纵向同步脉宽一般有最小值和最大值限制，具体取值范围请根据参照屏的datasheet 注：对于MIPI屏，由于DSI的timing配置还有以下限制： vback-porch <= 255 vfront-porch <= 255 vsync-len <= 255 hsync-active vsync-active de-active pixelclock-active swap-rb swap-rg swap-gb dsp-lut Hsync极性 Vsync极性 DEN极性 Dclk极性 R、B通道对调 R、G通道对调 G、B通道对调一组256维的GAMMA LUT数组（如果有的屏幕要用LUT对显示效果进行调整，在display-timings中添加该属性） <0> 默认的时钟极性 <1> 对时钟极性进行翻转 <0> 默认不对调r、g、b颜色组 <1> 把对应的颜色组进行对调 <0x000000 0x010101 0x020202 ... 0xfdfdfd 0xfefefe 0xffffff> 注：如何生成和配置GAMMA LUT数组详见附录A2说明

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3.3.3 Panel Power On/Off Sequence

gpio-power-on {

power_en {

intel,gpio-type = \ intel,gpio-value-delay = <1 0>; }; reset1 {

intel,gpio-type = \ intel,gpio-value-delay = <0 5>; }; reset2 {

intel,gpio-type = \ intel,gpio-value-delay = <1 10>; }; };

gpio-power-off { reset {

intel,gpio-type = \ intel,gpio-value-delay = <0 20>; };

power_en {

intel,gpio-type = \ intel,gpio-value-delay = <0 10>; }; };

gpio-power-on为屏power on时序，上述上电时序配置表示：

vhigh脚拉高 --> reset脚拉低后延迟5 ms --> reset脚拉高后延迟10 ms gpio-power-off为屏power off时序，上述下电时序配置表示： reset脚拉低后延迟20 ms --> vhigh脚拉低延长10ms

内核在解析到这些电源控制节点后，会以他们在dts里面出现的顺序依次去操作他们。所以这些节点，请按照上电时序和下电时序要求填写。

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1.GPIO类型

GPIO Power ctrl各属性说明详见下表:

Property intel,gpio-type Description GPIO name，用于查找对应的GPIO脚 \Value 对应dts中intel,display-gpio-reset属性中的reset pin \对应dts中intel,display-gpio-vhigh属性中的vhigh pin \对应dts中intel,display-gpio-vhigh属性中的vlow pin \对应dts中intel,display-gpio-vpwr属性中的vpwr pin intel,gpio-value-delay GPIO输出高低以及delay时间（单位ms）例如： <0 10> 表示拉低后延迟10 ms <1 10> 表示拉高后延迟10 ms

2.Regulator类型

下面的Power时序中就包括两种Power Control类型：GPIO和REGULATOR gpio-power-on {

power1 {

intel,power-type = \ intel,regulator-type = \ intel,regulator-value-delay = <1 10>; }; power2 {

intel,power-type = \ intel,regulator-type = \ intel,regulator-value-delay = <1 30>; }; reset1 {

intel,gpio-type = \ intel,gpio-value-delay = <1 20>; }; reset2 {

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intel,gpio-type = \ intel,gpio-value-delay = <0 20>; }; reset3 {

intel,gpio-type = \ intel,gpio-value-delay = <1 100>; }; };

gpio-power-off { reset {

intel,gpio-type = \ intel,gpio-value-delay = <0 1>; }; power2 {

intel,power-type = \ intel,regulator-type = \ intel,regulator-value-delay = <0 1>; }; power1 {

intel,power-type = \ intel,regulator-type = \ intel,regulator-value-delay = <0 1>; }; };

Regulator Power Ctrl各属性说明详见下表:

Property intel,power-type intel,regulator-type Description Power Ctrl Type： Regulator和GPIO Regulator name: 用于查找dts中配置的对应的VDD/LDO “regulator” Value Regulator类型必须声明该属性为最多支持4个vdd: \\\\ 注：lcd_vdd对应的pmu-domain需在dts中配置，请参考3.8节的patch

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intel,regulator-value-delay Regulator输出高低以及delay时间（单位ms）例如： <0 10> 表示输出低后延迟10 ms <1 10> 表示输出高后延迟10 ms

3.3.4 Panel Initial Command Sequence

cmd-init {

cmd1 {

intel,cmd-type = <0x15>; intel,cmd-data = <0x00 0x00>; intel,cmd-lp = <1>; }; //cmd2 ... cmd3 ... };

cmd-sleep-in { display-off {

intel,cmd-type = <0x05>; intel,cmd-data = <0x28>; intel,cmd-delay = <20>; intel,cmd-lp = <1>; }; sleep-in {

intel,cmd-type = <0x05>; intel,cmd-data = <0x10>; intel,cmd-delay = <10>; intel,cmd-lp = <1>; }; };

cmd-sleep-out { sleep-out {

intel,cmd-type = <0x05>; intel,cmd-data = <0x11>; intel,cmd-delay = <120>; intel,cmd-lp = <1>; };

display-on {

intel,cmd-type = <0x05>; intel,cmd-data = <0x29>; intel,cmd-delay = <10>;

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intel,cmd-lp = <1>; }; };

cmd-init为panel初始化发送的cmd队列 cmd-sleep-in为panel进入休眠发送的cmd队列 cmd-sleep-out为panel退出休眠发送的cmd队列这部分cmd的配置请参考屏原厂提供的cmd时序

Property intel,cmd-type Description CMD类型根据cmd data参数长度填写（参数个数忽略cmd data的第1个参数） DCS write: Value <0x05> short packet,no parameters <0x15> short packet,1 parameter DCS long write: <0x39> long packet 参考屏原厂提供的CMD时序 intel,cmd-data cmd data of packet cmd data的第1个参数为data type intel,cmd-delay intel,cmd-lp 发送cmd后的延迟时间单位：ms 是否使用lower power mode发送CMD 参考屏原厂提供的CMD时序 <1> 在lower power mode下发送cmd <0> 在high speed mode下发送cmd 注：默认使用lower power mode发送CMD，请配置为1

3.3.5 Panel-detect

不使用Multiple Panel时默认不需要配置该节点

当include多个lcd-xxx.dtsi文件时，软件上会通过panel detect判断硬件插入的是哪款屏，以便加载对应的屏驱动，支持两种panel detect方式：

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1.GPIO:

硬件必须预留GPIO脚用于检测panel,GPIO脚在dts的screen节点intel,display-gpio-id0 和 intel,display-gpio-id0 属性中配置，软件上会根据判断这两根GPIO脚的Input Value值和id-verication的value进行比较，即可判断硬件上是否接的是该panel，匹配的话就加载该屏驱动. panel-detect {

intel,id-detect-method = \ intel,id-verification = <0 1>; };

2.MIPI:

只有MIPI屏支持该detect方式，在每个panel node的子节点中都加上panel-detect，通过各自的read panel id的cmd读取panel id和id-verication中的id进行比较，即可判断硬件上是否接的是该panel，匹配的话就加载该屏驱动. panel-detect {

intel,id-detect-method = \ intel,id-verification = <0x40>; intel,cmd-type = <0x14>;

intel,cmd-data = <0xDA 0x40>; /* panel id */ intel,cmd-lp = <1>; };

Panel-detect节点各个属性的详细说明如下表：

Property intel,id-detect-method Description Panel ID detect方式 GPIO Input Value 或Panel ID Value “GPIO”: 通过GPIO输入脚的高低判断 “MIPI”: 通过read cmd读取panel id GPIO方式：请填写为2根GPIO脚的intput高低值 MIPI方式：根据屏的datasheet填写为panel id intel,id-verification intel,cmd-type = <0x14>; 读取panel ID的cmd： 0x04: Generic Read, 0 parameter 不同屏不一样，请根据屏的datassheet填写 0x14: Generic Read, 1 parameter 0x24: Generic Read, 2 parameter

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例如：cmd-data: 0xDA 0x40 这里0xDA为data type,参数只有一个是0x40, 所以cmd-type选择0x14. intel,cmd-data = <0xDA 0x40>; 根据屏的datasheet填写默认使用lower power mode发送CMD intel,cmd-lp = <1>;

3.4 vop node

&vop { };

对应的各个属性的详细说明如下表：

status = \

rockchip,fb-win-map = ; rockchip,iommu-enabled = <1>; uhigh_perf_freq = <297000000>;

Property rockchip,fb-win-map Description fb和win的映射关系例如： fb0对应win0,fb1对应win1表示：操作dev/graphics/fb0节点，实际操作的是vop的win0层操作dev/graphics/fb1节点，实际操作的是vop的win1层 Value 默认的fb和win映射关系，即fb0对应win0,fb1对应win1 fb0对应win2,fb1对应win1,fb2对应win0 fb0对应win1,fb1对应win2,fb2对应win0 fb0对应win2,fb1对应win0,fb2对应win1 fb0对应win0,fb1对应win2,fb2对应win1 fb0对应win0,fb1对应win1,fb2对应win2 fb0对应win1,fb1对应win0,fb2对应win2 rockchip,iommu-enabled 是否启用VOP的iommu 开启iommu可以使用非连续的物理地址

<1> 默认开启vop iommu <0> 关闭vop iommu,使用CMA 26

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uhigh_perf_freq display clock频率(对于Controller的clock频率),该频率为vop dclk频率的两倍请根据lcd-xxx.dtsi文件中mipi屏该频率也是DSI display-timings节点的clock-frequency值（参照3.2.2节）填写该属性值： 1）LVDS/RGB屏： uhigh_perf_freq = 2 x clock-frequency 该clock频率会影响输出的帧率 2）MIPI屏： uhigh_perf_freq >= 2 x clock-frequency MIPI屏的帧率由MIPI DSI控制，该频率配置不影响帧率，建议配置为297M（DSI Controller的频率越高越好）注：由于vmm clock频率表的限制，不是所有的频率都支持，下表列出了所有支持的clock频率表，请选择最接近的频率.

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Display支持的clock频率表（vop dclk的两倍）

Support Clock Frequency 1.3M 1.62M 2.4M 3.1M 3.15M 3.2M 3.25M 4.8M 5.2M 6M 6.5M 8.67M 9.6M 10.4M 12M 13M 15.4M 15.6M 16M 16.9M 19.2M 19.5M 22.7M 24M 24.5M 26M 29.02M 31.2M 34.67M 39M 48M 52M 54M 62.4M 67M 69.33M 74.2M 78M 83.2M 89M 96M 1300000 1625000 2400000 3104477 3151515 3200000 3250000 4800000 5200000 6000000 6500000 8666666 9600000 10400000 12000000 13000000 15407407 15600000 16000000 16864864 19200000 19500000 22690909 24000000 24470588 26000000 29023255 31200000 34666666 39000000 48000000 52000000 54000000 62400000 67000000 69333333 74200000 78000000 83200000 89142857 96000000 104M 108M 113.5M 117M 120M 124.8M 130M 134M 136.5M 138.67M 148.5M 156M 136.5M 138.67M 148.5M 156M 178M 182M 188.5M 192M 200M 208M 211M 225M 234M 240M 249.6M 250M 260M 273M 277.3M 297M 305.5M 312M 333M 338M 356.6M 364M 377M 400M Support Clock Frequency 104000000 108000000 113454545 117000000 120000000 124800000 130000000 134000000 136500000 138666666 148500000 156000000 136500000 138666666 148500000 156000000 178285714 182000000 188500000 192000000 200000000 208000000 211000000 225000000 234000000 240000000 249600000 250000000 260000000 273000000 277300000 297000000 305500000 312000000 333000000 338000000 356600000 364000000 377000000 400000000

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3.5 mipi/lvds node

1. lcd屏为mipi屏：

&mipi_dsi {

status = \}; &lvds {

status = \};

2. lcd屏为lvds屏：

&lvds { };

&mipi_dsi { };

status = \

pinctrl-names = \pinctrl-0 = <&lvds_default_pins>; pinctrl-1 = <&lvds_sleep_pins>; pinctrl-2 = <&lvds_inactive_pins>; status = \

3.6 backlight node

3.6.1 XGOLD PWM

backlight {

compatible = \ brightness-levels = <

20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20

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20 20 20 20 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255>; default-brightness-level = <128>; enable-gpios = <&abb_pmx_gpio 32 0>; pinctrl-names = \ pinctrl-0 = <&led_agold_default_pins>; pinctrl-1 = <&led_agold_sleep_pins>; pinctrl-2 = <&led_agold_inactive_pins>;

pwms = <&pwm0 0 25000 PWM_POLARITY_INVERTED>; };

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1.brightness-levels：为具体的背光亮度列表

请根据背光硬件设计的是正极性还是负极性，采用正序或者倒序去排列。 2.default-brighness-level：为默认背光亮度 3.enable-gpios：为背光电源控制使能IO

3.6.2 AGOLD PWM

请参考以下配置和说明填写AGLOD backlight节点（蓝色部分为新驱动代码支持新增的），其中 free running 指的是agold的背光模块只提供PWM信号 analog feedback 指的是agold的背光模块提供驱动电路

backlight:agold620-backlight {

compatible = \ reg = <0xE6501800 0x154 0xE6401134 0x4>; reg-names = \ intel,flags-use-safe-ctrl; pm,class-name = \ pm,user-name = \ pm,state-D0 = \ pm,state-D3 = \

intel,run-mode = <1>; //1:free running,2:analog feedback,3,digital control intel,led-polarity = <0>; //(free running need)

intel,led-max-brightness = <96>; //(free running need) intel,led-min-brightness = <10>; //(free running need) intel,default-brightness-level = <60>;

intel,ref-voltage = <2>; //0:100mv, 1:150mv, 2:200mv (analog feedback need) intel,cabc = <0>; //for all mode

intel,bl-gpio-enable = <&abb_pmx_gpio 32 0>; };

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3.7 HDMI dts配置说明

3.7.1 RK616 HDMI

若外接RK616实现主屏LVDS和HDMI双显(这里主屏LVDS使用的是RK616上的LVDS而不是SOFIA3GR上的LVDS)，dts需要配置:

1.rockchip,disp-mode修改为ONE_DUAL 2.添加DIF pinctrl（iomux dif接口为RGB输出） 3.添加rk61x node（添加到对应的i2c上）

4.配置RK616芯片的供电（请参考power文档配置各路供电对应的LDO和电压值）

详细配置可参考下面的patch

diff --git a/arch/x86/boot/dts/SF_3GR-tablet.dts b/arch/x86/boot/dts/SF_3GR-tablet.dts index e59c502..cce16bb 100644

--- a/arch/x86/boot/dts/SF_3GR-tablet.dts +++ b/arch/x86/boot/dts/SF_3GR-tablet.dts @@ -137,8 +137,8 @@

fb {

compatible = \

- rockchip,disp-mode = ; + rockchip,disp-mode = ; rockchip,loader-logo-on = <1>; rockchip,ion-drv = \ };

@@ -177,7 +177,14 @@ screen {

compatible = \ pm,class-name = \ pm,user-name = \ pm,state-D0 = \ pm,state-D3 = \ backlight = <&backlight>;

+ pinctrl-names = \

+ pinctrl-0 = <&dif_highdrv_pins>; /* <&dif_default_pins> */ + pinctrl-1 = <&dif_sleep_pins>; + pinctrl-2 = <&dif_inactive_pins>;

#include \ };

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@@ -1066,6 +1113,27 @@ &i2c_4 {

status = \

pinctrl-names = \ pinctrl-0 = <&i2c4_default_pins>; pinctrl-1 = <&i2c4_sleep_pins>; pinctrl-2 = <&i2c4_inactive_pins>; +

+ rk61x {

+ compatible = \+ reg = <0x50>; +

+ rk61x,lcd0_func = <1>; /* 0: UNUSED; 1: INPUT; 2: OUTPUT */ + rk61x,lcd1_func = <0>; + rk61x,lvds_ch_nr = <1>;

+ /* pll source: 0: LCD0_DCLK; 1: LCD1_DCLK; 2: sysclock 26M */ + rk61x,pll_clk_sel = <0>; + /* rk61x,hdmi_irq_gpio = <>; */ //pls config the GPIO according to hardware +

+ pinctrl-names = \+ pinctrl-0 = <&hdmi_default_pins>; + pinctrl-1 = <&hdmi_sleep_pins>; + pinctrl-2 = <&hdmi_inactive_pins>; +

+ pm,class-name = \+ pm,user-name = \+ pm,state-D0 = \+ pm,state-D3 = \+ }; };

@@ -1383,14 +1452,14 @@ };

&mipi_dsi {

- status = \+ status = \ };

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3.7.2 ITE66121 HDMI

若外接ITE66121芯片实现HDMI单显（HDMI显示时主屏是灭屏的），dts需要配置: 1.非双显模式，rockchip,disp-mode保留默认值NO_DUAL 2.添加DIF pinctrl（iomux dif接口为RGB输出） 3.添加it66121 node（添加到对应的i2c上）

4.配置ITE66121芯片的供电（请参考power文档配置各路供电对应的LDO和电压值）

详细配置可参考下面的patch

diff --git a/arch/x86/boot/dts/SF_3GR-svb.dts b/arch/x86/boot/dts/SF_3GR-svb.dts index b06361c..fe8910e 100644

--- a/arch/x86/boot/dts/SF_3GR-svb.dts +++ b/arch/x86/boot/dts/SF_3GR-svb.dts &i2c_4 {

@@ -738,6 +737,15 @@

intel,max-x = <800>; intel,max-y = <1280>; }; +

+ it66121 {

+ compatible = \+ reg = <0x4c>;

+ pinctrl-names = \+ pinctrl-0 = <&hdmi_default_pins>; + pinctrl-1 = <&hdmi_sleep_pins>; + pinctrl-2 = <&hdmi_inactive_pins>; + }; };

3.8 Multiple panel配置说明

如果要使用该功能，直接在dts的screen节点中include多个不同的屏的lcd-xxx.dtsi，并且在每个lcd-xxx.dtsi文件中配置panel-detect节点用于检测硬件接入是哪款屏，驱动会自动检测并加载对应的屏驱动。

Multiple panel的修改配置请参考下面的patch：

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1.Enable the multiple panel support in DTS:

注：下面lcd-xxx.dtsi的修改是针对旧的代码，需将display-timings节点移到panel节点内部作为panel的子节点

diff --git a/arch/x86/boot/dts/SF_3GR-es1-sr-garnet.dts b/arch/x86/boot/dts/SF_3GR-es1-sr-garnet.dts index 4063a8c..83612b3 100644

--- a/arch/x86/boot/dts/SF_3GR-es1-sr-garnet.dts +++ b/arch/x86/boot/dts/SF_3GR-es1-sr-garnet.dts @@ -126,6 +126,7 @@

pm,state-D3 = \

intel,display-gpio-vhigh = <&xgold_pmx_gpio 45 0>; intel,display-gpio-reset = <&xgold_pmx_gpio 46 0>; + #include \ #include \ };

diff --git a/arch/x86/boot/dts/xgold/display/auo_b070atn02.dtsi b/arch/x86/boot/dts/xgold/display/auo_b070atn02.dtsi index 59ee9eb..26c3f29 100644

--- a/arch/x86/boot/dts/xgold/display/auo_b070atn02.dtsi +++ b/arch/x86/boot/dts/xgold/display/auo_b070atn02.dtsi @@ -2,30 +2,6 @@

* definition at \ */

-display-timings {

- native-mode = <&timing0>; - timing0: timing0 {

- screen-type = ; - out-face = ; - color-mode = ; - clock-frequency = <49768320>; - hactive = <600>; - vactive = <1024>; - hback-porch = <60>; - hfront-porch = <100>; - vback-porch = <10>; - vfront-porch = <22>; - hsync-len = <24>; - vsync-len = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>;

- pixelclk-active = <0>; - swap-rb = <0>; - swap-rg = <0>; - swap-gb = <0>; - };

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-};

auo_b070atn02 {

compatible = \@@ -39,6 +15,31 @@ auo_b070atn02 { intel,display-eot = <1>; intel,display-gate = <1>;

+ display-timings {

+ native-mode = <&auo_b070atn02_timing>;

+ auo_b070atn02_timing: auo_b070atn02_timing { + screen-type = ; + out-face = ; + color-mode = ; + clock-frequency = <49768320>; + hactive = <600>; + vactive = <1024>; + hback-porch = <60>; + hfront-porch = <100>; + vback-porch = <10>; + vfront-porch = <22>; + hsync-len = <24>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>;

+ pixelclk-active = <0>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + }; + }; +

gpio-power-on { power_en {

intel,gpio-type = \

diff --git a/arch/x86/boot/dts/xgold/display/innolux_n080ice.dtsi b/arch/x86/boot/dts/xgold/display/innolux_n080ice.dtsi index c23950a..77ca43e 100644

--- a/arch/x86/boot/dts/xgold/display/innolux_n080ice.dtsi +++ b/arch/x86/boot/dts/xgold/display/innolux_n080ice.dtsi @@ -2,30 +2,6 @@

* definition at \ */

-display-timings {

- native-mode = <&timing0>; - timing0: timing0 {

- screen-type = ; - out-face = ; - color-mode = ; - clock-frequency = <70224960>; - hactive = <800>;

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- vactive = <1280>; - hback-porch = <40>; - hfront-porch = <40>; - vback-porch = <20>; - vfront-porch = <20>; - hsync-len = <4>; - vsync-len = <4>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>;

- pixelclk-active = <0>; - swap-rb = <0>; - swap-rg = <0>; - swap-gb = <0>; - }; -};

innolux_n080ice {

compatible = \

@@ -39,6 +15,31 @@ innolux_n080ice { intel,display-eot = <1>; intel,display-gate = <1>;

+ display-timings {

+ native-mode = <&innolux_n080ice_timing>;

+ innolux_n080ice_timing: innolux_n080ice_timing { + screen-type = ; + out-face = ; + color-mode = ; + clock-frequency = <70224960>; + hactive = <800>; + vactive = <1280>; + hback-porch = <40>; + hfront-porch = <40>; + vback-porch = <20>; + vfront-porch = <20>; + hsync-len = <4>; + vsync-len = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>;

+ pixelclk-active = <0>; + swap-rb = <0>; + swap-rg = <0>; + swap-gb = <0>; + }; + }; +

cmd-init {

nt35521v06b_cm1 {

intel,cmd-type = <0x39>;

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2.Add panel detection node for panels:

在每个panel中都添加panel-detect节点，有两种detect方式，选择其中一种即可：

（1）GPIO方式(请根据实际的硬件设计填写GPIO Input高低值) diff --git a/arch/x86/boot/dts/SF_3GR-es1-sr-garnet.dts b/arch/x86/boot/dts/SF_3GR-es1-sr-garnet.dts index 65b4882..334548f 100644

--- a/arch/x86/boot/dts/SF_3GR-es1-sr-garnet.dts +++ b/arch/x86/boot/dts/SF_3GR-es1-sr-garnet.dts @@ -126,6 +126,8 @@

pm,state-D3 = \

intel,display-gpio-vhigh = <&xgold_pmx_gpio 45 0>; intel,display-gpio-reset = <&xgold_pmx_gpio 46 0>; + intel,display-gpio-id0 = <&xgold_pmx_gpio 55 0>; + intel,display-gpio-id1 = <&xgold_pmx_gpio 48 0>; #include \ #include \ };

diff --git a/arch/x86/boot/dts/xgold/display/auo_b070atn02.dtsi b/arch/x86/boot/dts/xgold/display/auo_b070atn02.dtsi index 73b190e..1e56e13 100644

--- a/arch/x86/boot/dts/xgold/display/auo_b070atn02.dtsi +++ b/arch/x86/boot/dts/xgold/display/auo_b070atn02.dtsi @@ -40,6 +40,11 @@ auo_b070atn02 { }; };

+ panel-detect {

+ intel,id-detect-method = \+ intel,id-verification = <0 0>; + }; +

gpio-power-on { power_en {

intel,gpio-type = \

diff --git a/arch/x86/boot/dts/xgold/display/boe_tv070wsm.dtsi b/arch/x86/boot/dts/xgold/display/boe_tv070wsm.dtsi index 5e3d185..bb9bd58 100644

--- a/arch/x86/boot/dts/xgold/display/boe_tv070wsm.dtsi +++ b/arch/x86/boot/dts/xgold/display/boe_tv070wsm.dtsi @@ -39,6 +39,12 @@ boe_tv070wsm { swap-gb = <0>; }; }; +

+ panel-detect {

+ intel,id-detect-method = \+ intel,id-verification = <1 0>; + };

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cmd-init{

cmd1 {

intel,cmd-type = <0x39>;

（2）MIPI CMD方式(请根据屏的datasheet填写相应的cmd)

diff --git a/arch/x86/boot/dts/xgold/display/lcd-mipi_otm1287a_auo_lp055apkp153a.dtsi b/arch/x86/boot/dts/xgold/display/lcd-mipi_otm1287a_auo_lp055apkp index 989927c..777fb35 100644

--- a/arch/x86/boot/dts/xgold/display/lcd-mipi_otm1287a_auo_lp055apkp153a.dtsi +++ b/arch/x86/boot/dts/xgold/display/lcd-mipi_otm1287a_auo_lp055apkp153a.dtsi @@ -41,6 +41,14 @@

}; };

+ panel-detect {

+ intel,id-detect-method = \+ intel,id-verification = <0x40>; + intel,cmd-type = <0x14>;

+ intel,cmd-data = <0xDA 0x40>; + intel,cmd-lp = <1>; + }; +

gpio-power-on { power_en {

intel,gpio-type = \

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3.9 Use Regulator Power Control

默认都是使用GPIO控制panel上下电，如果使用添加Regulator的话请参考以下patch: 下面的patch控制了lcd_vdd0(对应 vdd_prim_display_reg)和lcd_vdd1（对应vdd_lcd_dsi_reg）的power时序(详细的配置说明详见3.2节和3.3.3节)

diff --git a/arch/x86/boot/dts/SF_3GR-wifionly-mult8.dts b/arch/x86/boot/dts/SF_3GR-wifionly-mult8.dts index 58205f3..d4404af 100644

--- a/arch/x86/boot/dts/SF_3GR-wifionly-mult8.dts +++ b/arch/x86/boot/dts/SF_3GR-wifionly-mult8.dts @@ -154,8 +154,12 @@

compatible = \ pm,class-name = \ pm,user-name = \- pm,state-D0 = \- pm,state-D3 = \

+ pm,state-D0 = \+ pm,state-D3 = \+ pm,state-D0i0 = \+ pm,state-D0i1 = \+ pm,state-D3i0 = \+ pm,state-D3i1 = \ backlight = <&backlight>;

rockchip,display-delay-time = <60>;

intel,display-gpio-reset = <&xgold_pmx_gpio 4 0>; @@ -1371,7 +1375,7 @@

vdd_prim_display_reg {

virt-domain = ;

pmu-domain = ; };

vdd_lcd_dsi_reg {

virt-domain = ;

- pmu-domain = ; + pmu-domain = ; };

diff --git a/arch/x86/boot/dts/xgold/display/lcd-mipi_kd080d10.dtsi b/arch/x86/boot/dts/xgold/display/lcd-mipi_kd080d10.dtsi index 3b56ab0..644616b 100644

--- a/arch/x86/boot/dts/xgold/display/lcd-mipi_kd080d10.dtsi +++ b/arch/x86/boot/dts/xgold/display/lcd-mipi_kd080d10.dtsi @@ -42,21 +42,27 @@ display-panel0{ intel,display-gate = <1>;

gpio-power-on { + power1 {

+ intel,power-type = \+ intel,regulator-type = \+ intel,regulator-value-delay = <1 10>;

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echo sat_con xxx > sys/class/graphics/fb0/bcsh (4) adjust contrast[0:510]

echo contrast xxx > sys/class/graphics/fb0/bcsh (5) adjust hue (sin_hue[0:511],cos_hue[0:511])

echo hue xxx xxx > sys/class/graphics/fb0/bcsh (para1: sin_hue value ; para2: cos_hue value) (6)disable bcsh:

echo close > sys/class/graphics/fb0/bcsh

4. fps

查看帧率: cat sys/class/graphics/fb0/fps 注：

新增支持修改帧率（目前只支持MIPI屏）用于调试，切换帧率过程会灭屏再亮屏，例如echo 50 > sys/class/graphics/fb0/fps可修改帧率为50

5.1.2 hdmi节点

在sys/class/display/HDMI节点下列出了HDMI的几个主要属性：