IC datasheet pdf-TLK3114SC,pdf(10-Gbps XAUI Transceiver)

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iii Contents

Section Title Page 1Description 1?1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1Features 1?5

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2Ordering Information 1?6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Terminal Descriptions 2?1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Detailed Description 3?1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1Serdes Modes 3?1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.210-Gbps Ethernet Transceiver Modes 3?1

. . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3Parallel Interface Clocking 3?1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4Parallel Interface Data 3?1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5Transmit Data Bus Timing 3?2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6Transmission Latency 3?2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7Channel Clock to Serial Transmit Clock Synchronization 3?3

. . . . . . . . . . . 3.8Receive Data Bus Timing 3?4

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9Data Reception Latency 3?4

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10Auto Detectable HSTL/SSTL_2 Class 1 I/O 3?5

. . . . . . . . . . . . . . . . . . . . . . 3.118-b/10-b Encoder 3?5

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12Comma Detect and 8-b/10-b Decoding 3?6

. . . . . . . . . . . . . . . . . . . . . . . . . . 3.13Channel Initialization and Synchronization 3?7

. . . . . . . . . . . . . . . . . . . . . . . 3.13.1Channel State Descriptions 3?8

. . . . . . . . . . . . . . . . . . . . . . . . . . . 3.14End-of-Packet Error Detection 3?8

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.15Fault Detection and Reporting 3?9

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.16Receive Synchronization and Skew Compensation 3?10

. . . . . . . . . . . . . . 3.16.1Column State Descriptions 3?11

. . . . . . . . . . . . . . . . . . . . . . . . . . . 3.17Independent Channel Mode 3?12

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.18Inter-Packet Gap Management 3?13

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.19Clock Tolerance Compensation (CTC)3?15

. . . . . . . . . . . . . . . . . . . . . . . . . 3.20Parallel-to-Serial Shift Register 3?17

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.21Serial-to-Parallel Shift Register 3?17

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.22High-Speed VML Output Driver 3?18

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.23Device Configuration 3?18

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.24PRBS Generator 3?19

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.25MDIO Management Interface 3?20

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.26Operating Frequency Range 3?36

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.27Power-Down Mode 3?36

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.28Loopback Testing 3?37

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.29Power-On Reset 3?37

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.30Differences From the TLK3104SA Device 3?37

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4Electrical Specifications4?1

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4.1Absolute Maximum Ratings Over Operating Free-Air

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Temperature Range4?1

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4.2Recommended Operating Conditions4?1

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4.3Reference Clock Timing Requirements (RFCP/N)4?1

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4.4Reference Clock Electrical Characteristics (RFCP/N)4?2

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4.5LVTTL Electrical Characteristics4?2

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4.6SSTL_2 Class 1 Signals4?2

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4.7HSTL Signals4?3

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4.8Serial Transmitter/Receiver Characteristics4?3

4.9SSTL_2 Class 1/HSTL Output Switching Characteristics4?5

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. . . . . . . . . . . . . . . .

4.10SSTL_2 Class 1/HSTL Input Timing Requirements4?5

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4.11MDIO Timing Requirements4?6

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4.12Package Dissipation Rating4?7

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5Mechanical Data5?1

List of Illustrations

Figure Title Page

1?1System Block Diagram (Chip-to-Chip Implementation)1?1

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1?2System Block Diagram (PCS Implementation)1?2

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1?3System Block Diagram (Backplane Interconnect Implementation)1?2

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1?4TLK3114SC Block Diagram1?4

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1?5Block Diagram of Individual Channel1?5

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2?1TLK3114SC GNT/GPV-Package Terminal Diagram2?1

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3?1Transmit Interface Timing3?2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3?2Transmitter Latency3?3

3?3Transmit and Reference Clock Relationship (Channel Sync Mode)3?3

. . . . . . .

3?4Transmit and Reference Clock Relationship

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(Independent Channel Mode)3?4 3?5Receive Interface Timing3?4

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. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3?6Receiver Latency3?5

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3?7Channel Synchronization State Machine3?7

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3?8End-of-Packet Error Detection3?9

3?9Receive and Reference Clock Relationship

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(Synchronized Channel Modes)3?10

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3?10Column De-skew State Machine3?11

3?11Receive and Reference Clock Relationship

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(Independent Channel Modes)3?12

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3?12Inter-Packet Gap Management3?13

3?13IPG Management State Machine3?14

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

iv

v 3?14Channel Synchronization Using Alignment Code 3?15. . . . . . . . . . . . . . . . . . . . . 3?15Clock Tolerance Compensation: Add 3?16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?16Clock Tolerance Compensation: Drop 3?17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?17Output Differential Voltage Under Preemphasis 3?18. . . . . . . . . . . . . . . . . . . . . . 3?18Repeater-Mode Block Diagram 3?19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?19Management Interface Read Timing 3?20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?20Management Interface Write Timing 3?20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?21Management Interface Extended Space Address Timing 3?21. . . . . . . . . . . . . . 3?22Management Interface Extended Space Write Timing 3?21. . . . . . . . . . . . . . . . . 3?23Management Interface Extended Space Read Timing 3?21. . . . . . . . . . . . . . . . 3?24Management Interface Extended Space Read and Increment Timing 3?21. . . 4?1Differential and Common-Mode Output Voltage Definitions 4?4. . . . . . . . . . . . . . 4?2Transmit Template 4?4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?3Receive Template 4?4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?4Input Jitter 4?4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?5SSTL_2 Class 1/HSTL Output Timing Requirements 4?5. . . . . . . . . . . . . . . . . . . 4?6SSTL_2 Class 1/HSTL Data Input Timing Requirements 4?5. . . . . . . . . . . . . . . . 4?7MDIO Read/Write Timing 4?6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?8High-Speed I/O Direct-Coupled Mode 4?6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?9Example High-Speed I/O AC-Coupled Mode 4?6. . . . . . . . . . . . . . . . . . . . . . . . . . 4?10SSTL_2 Class 1 I/O 4?7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?11HSTL I/O 4?7

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . List of Tables

Table Title Page 2?1Clock Terminals 2?2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?2Serial Side Data Terminals 2?2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?3Parallel Data Terminals 2?3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?4JTAG Test Port Interface 2?4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?5Management Data Interface 2?5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?6Miscellaneous Terminals 2?5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?7Voltage Supply and Reference Terminals 2?6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?1Operational Interface Modes 3?1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?2Parallel Interface Clocking Modes 3?1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?3Parallel Data Modes 3?2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?4Valid K-Codes 3?6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?5Valid XGMII Channel Encodings 3?6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?6Receive Data Controls 3?7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?7Local and Remote Fault Sequences 3?9

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3?8IPG Management State Machine Notation3?14

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3?9Programmable Preemphasis3?18

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3?10Device Configuration3?19

3?11MDIO Device Address3?20

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3?12MDIO Registers3?22

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3?13Control Register Bit Definitions (Register 0)3?23

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3?14Status Register Bit Definitions (Register 1)3?23

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3?15PHY Identifier Bit Definitions (Register 2)3?24

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3?16PHY Identifier Bit Definitions (Register 3)3?24

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3?17Extended Status Register Bit Definitions (Register 15)3?24

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3?18Global Configuration Register Bit Definitions (Register 16)3?25

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3?19Channel A Configuration Registers Bit Definitions (Register 17)3?26

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3?20Channel B Configuration Registers Bit Definitions (Register 18)3?27

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3?21Channel C Configuration Registers Bit Definitions (Register 19)3?28

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3?22Channel D Configuration Registers Bit Definitions (Register 20)3?29

3?23Channel Status Register (Register 22)3?30

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3?24Channel Synchronization Status Register (Register 23)3?31

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3?25Clock Tolerance Compensation Status (Register 24)3?32

3?26Error Counter Control Register (Register 25)3?33

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3?27Channel A Error Count (Register 26)3?33

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3?28Channel B Error Count (Register 27)3?33

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3?29Channel C Error Count (Register 28)3?33

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3?30Channel D Error Count (Register 29)3?33

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3?31PHY XS Control 1 Register (Register 40)3?33

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3?32PHY XS Status 1 Register (Register 41)3?34

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3?33PHY XS Speed Ability Register (Register 44)3?34

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3?34Devices in Package Register (Register 45)3?34

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3?3510G PHY XS Status 2 Register (Register 48)3?34

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3?3610G PHY XGXS Lane Status Register (Register 424)3?34

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3?37PHY XS Register Cross Reference (Registers 432768?432776)3?35

3?38DTE XS Control 1 Register (Register 50)3?35

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3?39DTE XS Status 1 Register (Register 51)3?35

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3?40DTE XS Speed Ability Register (Register 54)3?35

3?41Devices in Package Register (Register 55)3?35

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3?4210G DTE XS Status 2 Register (Register 58)3?36

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3?4310G DTE XGXS Lane Status Register (Register 524)3?36

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3?44DTE XS Register Cross Reference (Registers 532768?532776)3?36

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3?45Comparison of TLK3104SA and TLK3114SC Devices3?37

vi

The TLK3114SC device operates with a single 2.5-V supply and dissipates less than 3 W. The device is packaged in a 19-mm ×19?mm, 289-terminal plastic ball grid array (PBGA) package and is characterized for operation from 0°C to 70°C.

The TLK3114SC device is a member of a family of CMOS multi-gigabit transceivers, intended for use in high-speed bidirectional point-to-point data transmission systems.

Figure 1?4 provides a high?level description of the TLK3114SC device. For a detailed diagram of the individual channels, see Figure 1?5.

1?3

2?1

2Terminal Descriptions

The TLK3114SC device is available in a 289-terminal MicroStar BGA package (GNT/GPV). The terminal layout for the GNT and GPV packages is shown in Figure 2?1. The TLK3114SC pinout is compatible with TLK3104SA board designs.

RDB3

VDDQ

GND

RCB

VDDQ

GND

VREF

GND

VDDQ

RCC

GND

VDDQ

RDC3

GND

VDDQ

RDB2RDB6RDB9TCB TDB5TDB8VDDQ TDC8TDC5TCC RDC9RDC6RDC2MFC MFD RDB1RDB5RDB8TDB2TDB4TDB7TDC9TDC7TDC4TDC2RDC8RDC5RDC1GND VDDQ RDB0VDDQ GND TDB1VDDQ GND VDDQ GND VDDQ TDC1GND VDDQ RDC0RDD8RDD9RDA5RDB4RDB7TDB0TDB3TDB6TDB9TDC6TDC3TDC0RDC7RDC4RDD5RDD6RDD7RDA4RDA3RDA2T?GND T?GND T?GND T?GND T?GND T?GND T?GND RDD2RDD3RDD4GND VDDQ RDA0VDDQ GND T?GND T?GND T?GND T?GND T?GND T?GND T?GND GND VDDQ RDD0RDD1RCD TDA8TDA7TDA6T?GND T?GND T?GND T?GND T?GND T?GND T?GND TDD6TDD7TDD8TDD9TCD TDA5TDA4TDA3T?GND T?GND T?GND T?GND T?GND T?GND T?GND TDD3TDD4TDD5GND VDDQ TDA0VDDQ GND T?GND T?GND T?GND T?GND T?GND T?GND T?GND GND VDDQ TDD0TDD1TDD2GNDA VDD GND T?GND T?GND T?GND T?GND T?GND T?GND T?GND GND VDD GNDA GNDA VDDA VDDA TXAN GND T?GND T?GND T?GND T?GND T?GND T?GND T?GND GND TXDN VDDA RXDN VDDA VDDA TXAP GND GNDA GNDA GND GND GND GNDA GNDA GND TXDP VDDA RXDP VDDA GNDA VDD VDD TXBP TXBN VDD VDD VDD TXCN TXCP GNDA VDD GNDA GNDA GNDA LPENA LPENB GNDA VDDA VDDA GND RFCP GND VDDA VDDA GNDA LPENC LPEND PADR2MDIO CONFIG0CONFIG1GNDA RXBP RXBN GND RFCN GND RXCN RXCP VDD TESTEN PADR4PADR3MDC PSYNC SYNCEN GNDA VDDA VDDA VDD PRBSEN

VDD VDDA VDDA GNDA CODE PADR0PADR1DADR0B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

GND

MFB GND RDA8RDA6GND RDA1TDA9GND TDA1GNDA RXAN RXAP GNDA TDI TMS RSTN 17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

A

VDDQ

MFA VDDQ RDA9RDA7VDDQ RCA TCA VDDQ TDA2VDDA VDDA VDDA GNDA TCLK TDO ENABLE

B C D E F G H J K L M N P R T U A

17

16151413121110987654321Pin Out (Top View)

Figure 2?1.TLK3114SC GNT/GPV-Package Terminal Diagram

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