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IntroductiontoMegafunctionIPCores

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Alteraprovidesafreelibraryofparameterizableintellectualproperty(IP)blocks,calledmegafunctions,that

emegafunctionstoaccessarchitecture-specificfeatureswithinmemory,DSPblocks,shiftregisters,andothersimpleandcomplexfunctions.

YoucanquicklydefineamegafunctionvariationintheMegaWizardPlug-InManagerGUI.Alternatively,youcandefineandinstantiatemegafunctionsdirectlyinHDLfiles.TheQuartusIIsoftwareautomaticallyinfersmegafunctioncodewheneverHDLcodecanbeoptimizedbymegafunctionsubstitution.

AlteraProvidedMegafunctions

TheQuartusIIsoftwareimplementsyourspecifiedsystemorIPcoreparametersandgeneratesfilesforsynthesisandsimulationintheQuartusIIsoftwareandotherEDAtools.TheQuartusIIsoftwareincludesthefollowingmegafunctionsforusewithoutadditionallicense.

ArithmeticMegafunctions

TheQuartusIIsoftwareincludesthesearithmeticmegafunctions.

MegafunctionName

Function

LPM_ABSLPM_ADD_SUBLPM_COMPARELPM_COUNTERLPM_DIVIDELPM_MULTALTACCUMULATEALTECCALTMEMMULTALTMULT_ACCUMALTMULT_ADD

AbsolutevalueAdder/SubtractorComparatorCounterDividerMultiplierAccumulatorECCEncoder/Decoder

MemoryConstantCoefficientMultiplierMultiply-AccumulatorMultiply-Adder

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2Floating-PointMegafunctions

MegafunctionNameFunction

ALTMULT_COMPLEXALTSQRTPARALLEL_ADD

ComplexMultiplierIntegerSquare-RootParallelAdder

Floating-PointMegafunctions

TheQuartusIIsoftwareincludesthesefloating-pointmegafunctions.

MegafunctionName

Function

ALTFP_ADD_SUBALTFP_DIVALTFP_MULTALTFP_EXPALTFP_INVALTFP_INV_SQRTALTFP_LOGALTFP_ATANALTFP_SINCOSALTFP_ABSALTFP_COMPARE

Adder/SubtractorDividerMultiplierExponentialInverse

InverseSquareRootNaturalLogarithmArctangent

TrigonometricSine/CosineAbsolutevalueComparator

GateMegafunctions

TheQuartusIIsoftwareincludesthesegate

megafunctions.

MegafunctionName

Function

LPM_CLSHIFTLPM_CONSTANTLPM_DECODELPM_MUX

CombinatoriallogicshifterConstantgeneratorDecoderMultiplexer

I/OMegafunctions

TheQuartusIIsoftwareincludestheseI/Omegafunctions.

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MemoryMegafunctions3

MegafunctionNameFunction

ALTLVDSALTPLL

ALTPLL_RECONFIGALTERA_PLL

ALTREMOTE_UPDATEALTGXBAL2TGXBALTOCTALTCLKCTRLALTDDIOALTIOBUFALTTEMP_SENSEALTDLL

ALTDQandALTDQSALTDQ_DQS2ALTASMI_PARALLEL

LVDStransmitterandreceiverPhase-LockedLoop(PLL)PLLreconfiguration

Phase-LockedLoopforStratix®VdevicesonlyRemoteUpdate

Gigabittransceiverblock(GXB)GigabittransceiverblockII(GXB)On-ChipTerminationClockControlDoubleDataRateI/OI/OBuffer

TemperatureSensorDelayLockedLoop(DLL)DQandDQS

DQandDQSforStratixVActiveSerialMemoryInterface

MemoryMegafunctions

TheQuartusIIsoftwareincludesthesememorymegafunctions.

MegafunctionName

Function

RAMandROMSCFIFOandDCFIFOFIFOPartitionerLPM_SHIFTREGALTSHIFT_TAPSALT_UFMALTOTP

Internalmemories

SingleclockFIFOandDual

ClockFIFOFirst-InFirst-OutPartitionerShift-registerRAMShiftRegisterUserFlashMemory

One-TimeProgrammablefunction

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4JTAGMegafunctions

JTAGMegafunctions

TheQuartusIIsoftwareincludestheseJTAGextensiblemegafunctions.

MegafunctionName

Function

PFL

SLD_VIRTUAL_JTAG

RelatedInformation

ParallelFlashLoaderVirtualJTAG

MegafunctionsandIPDocumentationWebPage

CustomizingMegafunctions

ingmegafunctionsinyourdesigninvolvesthefollowingsteps:

1.Identifythemegafunctionthatbestmeetsyourdesignandtargetdevicerequirements.

2.TodefineandinstantiateamegafunctionusingtheGUI,clickTools>MegaWizardPlug-InManagerandfollowthewizardtodefineyourmegafunction.TheQuartusIIsoftwareautomaticallygeneratessynthesisandoptionalsimulationoutputfiles.

etheBlockEditororQsystoconnectthemegafunctiontootherelementsinthedesign.

pileyourdesignintheQuartusIIsoftware.OptionallygenerateanetlistforotherEDAtools.5.SimulateyourdesigninyourpreferredEDAsimulator.

RelatedInformation

ConnectingMegafunctionsonpage5UsingHDLCodeTemplatesonpage7

SynthesizingMegafunctionsinotherEDAToolsonpage11

CustomizingMegafunctionsintheGUI

TheMegaWizardPlug-InManagerGUIallowsyoutodefineandinstantiateacustomvariationofanAlteramegafunction.Youcaneditmegafunctionsatanytime.MegafunctionsdefinedinyourprojectappearintheProjectNavigator.Toeditamegafunction,double-clickthemegafunctionfileintheProjectNavigatororBlockEditortodisplaytheMegaWizardGUI.TocustomizeamegafunctionusingtheMegaWizardPlug-InManagerGUI,followthesesteps:

unchtheMegaWizardPlug-InManagerusinganyofthefollowingmethods:

IntheQuartusIIsoftware,clickTools>MegaWizardPlug-InManager.

IntheProjectNavigator,right-clickamegafunctionfileandclickMegaWizardPlug-InManager. IntheBlockEditor,clickEdit>InsertSymbolasBlock.IntheSymboleditor,clickMegaWizardPlug-InManager.

Startthestand-aloneversionoftheMegaWizardPlug-InManagerGUIbytypingthefollowingcommandat

thecommandprompt:qmegawiz(forGUIorcommand-linemode)or

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ConnectingMegafunctions5

qmegawizq(forGUIonly)

2.SpecifyCreate,Edit,orCopyamegafunction.

3.InWhichdevicefamilywillyoubeusing?selectyourtargetdevicefamily.

OnlymegafunctionsavailableforthetargetdeviceareavailableinWhichmegafunctionwouldyouliketocustomize?Unsupportedmegafunctionsaregrayedout.

4.Specifythenameandfileformatoftheoutputfile.ClickNext

5.Parameterizethemegafunctionbyspecifyingoptionsinthewizard.ClickNext.6.IfthewizardincludesEDAandSummarytabs,followthesesteps:

Somethird-partysynthesistoolscanuseagreyboxnetlistthatcontainsthestructureofanIPcorewithoutdetailedlogictooptimizetimingandperformanceofthedesigncontainingit.Tousethisfeature,turnonGenerateNetlisttogenerateanetlistfileforareaandtimingestimationinsteadofawrapperfile.

OntheSummarytab,selectthefilesyouwanttogenerate.Agraycheckmarkindicatesafilethatisautomaticallygenerated.Allotherfilesareoptional.ThisstepinstantiatesthemegafunctionintoyourHDLcodeandcreatesawrapperfile.7.ClickFinish.Themegafunctionvariationisgeneratedalongwiththefilesyouspecify.

8.Toviewthemegafunctionschematic,openthegeneratedblocksymbolfile(.bsf)locatedinyourprojectdirectory.ThemegafunctionblocksymbolappearsintheSymbolwindow.

Youcaneditmegafunctionsatanytime.MegafunctionsdefinedinyourprojectappearintheProjectNavigator.Toeditamegafunction,double-clickthemegafunctionfileintheProjectNavigatororBlockEditortodisplaytheMegaWizardGUI.Figure1:ExampleParameterizedGlobalClockControl

Module

RelatedInformation

CreatingaSystemwithQsys

ConnectingMegafunctions

YoucaneasilyvisualizeandconnectmegafunctionstootherelementsofyourdesignwiththeQuartusIIBlockEditor.Youcanmakeconnectionsbydrawingnode(wire),bus,andconduitconnectionsbetweenblocksrepresentingmegafunctionsandprimitivesintheschematic.IftheI/Osignalnamesinoneblockmatchthoseinanotherconnectedblock,theQuartusIIsoftwareautomaticallyconnectscommonI/O's

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6GeneratedMegafunctionFiles

betweentheblocks.IftheI/Osintwoconnectedblocksaredifferentlynamed,youcanassignanamethatmatchesablockI/Oporttoconnecttheporttothebusorconduit,oryoucanmapthesignalconnectionbynameexplicitly.YoucanalsoconnectmegafunctionsincludedinaQsyssystemintheQsysGUI.Toconnectamegafunctionusingtheblockeditor,followthesesteps:

1.Todrawawire,busorconduitlineconnectingoneormoreblock,performanyofthefollowing: Todrawaconduit,clicktheSelectionandSmartDrawingToolortheOrthogonalConduitToolbuttononthetoolbar.Thesmartselectionanddrawingtoolautomaticallychangestothecorrectnode,bus,orconduittoolwhenyoudragitfromablockorsymbolborder. Todrawabus,clicktheOrthogonalBusToolbuttononthetoolbar. Todrawawire,clicktheOrthogonalNodeToolbuttononthetoolbar.

TheQuartusIIsoftwareautomaticallyconnectscommonI/O'sbetweentheblocks2.TomapdifferentlynamedI/Obetweentwomegafunctions,followthesesteps:

a.Ataconduitconnection,doubleclickthemappersymbol.TheMapperPropertiesdialogboxappears.b.OntheGeneraltab,specifytheI/OType.c.ClicktheMappingstab.

d.UnderConduitMappings,selectthenameofyourI/OonblockandthecorrespondingSignalsinconduit.

e.ClickAdd.Alogicalconnectioniscreatedbetweenthesignals.3.IntheFilemenu,clickSave.

Figure2:ExampleGlobalClockControl

Connections

GeneratedMegafunctionFiles

TheMegaWizardPlug-InManagergeneratesoneormoreofthefollowingfilesforsynthesisandsimulationofthemegafunctionIPcoreintheQuartusIIsoftwareandotherEDAtools.

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InstantiatingMegafunctionsinHDL7

Figure3:IPFilesGeneratedbyMegaWizardPlug-In

Manager

RelatedInformation

SynopsysSimplifySupport

InstantiatingMegafunctionsinHDL

YoucaninstantiateamegafunctiondirectlyinyourHDLcodebycallingthemegafunctionandsettingitsparametersasyouwouldinanyothermodule,component,orsubdesign.WheninstantiatingamegafunctioninVHDL,besuretoincludethecorrectlibraries.

UsingHDLCodeTemplates

TheQuartusIIsoftwareincludescodeexamplesortemplatesforinferredRAMs,ROMs,shiftregisters,arithmeticfunctions,andDSPfunctionsoptimizedforAlteradevices.ToaccessHDLcodetemplatestodefinemegafunctions,followthesesteps:

1.Openafileinthetexteditor.2.OntheEdit>Inserttemplate.

3.IntheInsertTemplatedialogbox,clickthe+icontoexpandeithertheVerilogHDLcategoryortheVHDLcategory,dependingontheHDLyouprefer.

4.UnderFullDesigns,expandthenavigationtreetodisplaythetypeoffunctionsyouwanttoinfer.5.SelectthefunctiontodisplaythecodefortheselectedtemplateinthePreviewpane,andclickInsert.Note:FornewDSPfeaturesoptimizedforArriaV,CycloneV,andStratixV,expandtheArithmetic

category,andthenexpandtheDSPfeatures(Stratix-V,Arria-VandCyclone-V)category.

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8ExampleTop-LevelVerilogModule

ExampleTop-LevelVerilogModule

VerilogHDLALTFP_MULTinTop-LevelModulewithOneInputConnectedtoMultiplexer.moduleMF_top(a,b,sel,datab,clock,result);

input[31:0]a,b,datab;inputclock,sel;

output[31:0]result;wire[31:0]wire_dataa;

assignwire_dataa=(sel)?a:b;

altfp_multinst1(.dataa(wire_dataa),.datab(datab),.clock(clock),.result(result));

defparam

inst1.pipeline=11,inst1.width_exp=8,inst1.width_man=23,

inst1.exception_handling="no";

endmodule

ExampleTop-LevelVHDLModule

VHDLALTFP_MULTinTop-LevelModulewithOneInputConnectedtoMultiplexer.libraryieee;

useieee.std_logic_1164.all;libraryaltera_mf;

usealtera_mf.altera_mf_components.all;

entityMF_topis

port(clock,sel:instd_logic;

a,b,datab:instd_logic_vector(31downto0);result:outstd_logic_vector(31downto0));

endentity;

architecturearch_MF_topofMF_topis

signalwire_dataa:std_logic_vector(31downto0);begin

wire_dataa<=awhen(sel='1')elseb;inst1:altfp_mult

genericmap(

pipeline=>11,width_exp=>8,width_man=>23,

exception_handling=>"no")

portmap(

dataa=>wire_dataa,datab=>datab,clock=>clock,result=>result);

endarch_MF_top;

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ExampleMegafunctionInference9

ExampleMegafunctionInference

TheQuartusIIsoftwareinfersfollowingthefollowingVerilogHDLcodeastheLPM_MULTor

ALTMULT_ADDmegafunctionsforanunsignedandasignedmultiplier.EachexamplefitsintooneDSPblock9-bitelement.Inaddition,whenregisterpackingoccurs,noextralogiccellsforregistersarerequired.moduleunsigned_mult(out,a,b);

output[15:0]out;input[7:0]a;input[7:0]b;

assignout=a*b;endmodule

modulesigned_mult(out,clk,a,b);

output[15:0]out;inputclk;

inputsigned[7:0]a;inputsigned[7:0]b;regsigned[7:0]a_reg;regsigned[7:0]b_reg;regsigned[15:0]out;

wiresigned[15:0]mult_out;

assignmult_out=a_reg*b_reg;always@(posedgeclk)begin

a_reg<=a;b_reg<=b;

out<=mult_out;endendmodule

RelatedInformation

RecommendedHDLCodingStylesQuartusIIIntegratedSynthesis

UsingqmegawizCommand-LineExecutable

Youcanuseqmegawizcommand-lineversionoftheMegaWizardPlug-InManagerthatallowsyoutomodify,update,orcreatevariationfileswithoutusingaGUI.ThefollowingtablelistscommonqmegawizsyntaxoptionsandargumentsTouseqmegawiz,usethefollowingsyntax:

qmegawiz[options][module=<modulename>]|wizard=<wizardname>][<param>=<value>...<port>=<used>|<unused>...]<variationfilename>

Options/Arguments

Description

-silent

-f:<parameterfile>

RunstheMegaWizardPlug-InManagerin

command-linemode,withoutdisplayingtheGUI.Specifiesa.txtnamethatcontainsalltheparameterandportvalues.

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10UsingIP-generateCommand-LineExecutable

Options/ArgumentsDescription

-p:<workingdirectory>module=<modulename>wizard=<wizardname>

Specifiesthedefaultworkingdirectorythatqmegawizuseswhenitgeneratesfiles.

Specifiesthemoduleorwizardname.Whentherearemultiplewizardnamesthatcorrespondtoonemodulename,usethewizardoptiontospecifyonewizard.Whentherearemultiplemodulenamesthatcorrespondtoonewizardname,usethemoduleoptiontospecifyonemodule.

Specifiestheparametervalues.Specifieswhethertheportsareused.

Specifiesavariationfilename.Validextensionsare.v,.vhd,or.tdf.

<param>=<value><port>=<used>|<unused><variationfilename>

Forexample,

qmegawiz-silentmodule=altlvds_rxwizard=altlvds

common_rx_tx_pll=ONtx_coreclock=usedlvds_sample.v

RelatedInformation

Command-LineScripting

UsingIP-generateCommand-LineExecutable

Youcanuseip-generatetocreateormodifycustommegafunctionvariations.Toruntheip-generatecommand,followthesesteps:

1.Typethefollowingcommandatthecommandpromptofyouroperatingsystem:<ACDSinstallationdirectory>\quartus\sopc_builder\bin\2.Toruntheexecutabletypeip-generate.

3.Toinstantiatethemegafunctionusingtheexecutablefile,typethefollowingsyntax:ip-generate--component-name=altdq_dqs2

-–component-system-param=DEVICE_FAMILY=”StratixV”

-–file-set=QUARTUS_SYNTH--output-name[=<file_name>]–-component-param[=<parameter_name>][=<parameter_value>]

RelatedInformation

Command-LineScripting

IP-GenerateArguments

IP-generateacceptsthesecommonarguments.

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SynthesizingMegafunctionsinotherEDATools11

Options/ArgumentsDescription

--component-name=<variantname>-–file-set=QUARTUS_SYNTH--output-name[=<file_name>]

-–component-system-param=DEVICE_FAMILY=”<devicefamilyname>”–-component-param[=<parameter_name>][=<parameter_value>]

Specifiesthemegafunctionvariantname.

Aparameterthatisusedbytheip-generatortospecifyanoutputfile.Validextensionsare.v,.sv,.vhd,or.tdf.Specifiesthetargetdevicefamily.

Specifiesthetargetdevicefamily.

SynthesizingMegafunctionsinotherEDATools

YoucanusesupportedEDAtoolstosynthesizeadesignthatincludesmegafunctions.Whenyougeneratemegafunctionsynthesisfilesforusewiththird-partyEDAsynthesistools,youcanoptionallycreateanareaandtimingestimationnetlist.

areaandtimingestimationnetlistdescribethemegafunctionconnectivityandarchitecture,butnotdetailsabouttruefunctionality(greybox).Thisinformationenablescertainthird-partysynthesistoolstobetterreportareaandtimingestimates.Inaddition,synthesistoolscanusethetiminginformationtoachievetiming-drivenoptimizationsandimprovethequalityofresults.

Thenetlistfileiscalled<variantname>_syn.vfile.TheQuartus

IIsoftwaregeneratesthisfileinVerilogHDLformatregardlessoftheoutputfileformatyouspecify.Ifyouusethisnetlistforsynthesis,youmustincludethemegafunctionwrapperfile<variantname>.vor<variantname>.vhdinyourQuartusIIprojectforplacementandrouting.

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12SimulatingMegafunctions

Figure4:QuartusIIGeneratedFilesforOtherEDA

Tools

RelatedInformation

QuartusIIIntegratedSynthesis

SimulatingMegafunctions

Simulationverifiesdesignbehaviorbeforedeviceprogramming.TheQuartusIIsoftwaresupportsRTLandgateleveldesignsimulationofmegafunctionIPcoresinotherEDAsimulators.Simulationinvolvessettingupyoursimulatorworkingenvironment,compilingsimulationmodellibraries,andrunningyoursimulation.Alteraprovidesvarioustoolstohelpyouquicklysetupandrunsimulation.YoucanusetheQuartusIINativeLinkfeaturetoautomaticallygeneratesimulationfilesandscripts.NativeLinklaunchesyourpreferredsimulatorafromwithintheQuartusIIsoftware.

Useacustomflowformorecontroloverallaspectsofsimulationfilegeneration.Alternatively,theSimulationLibraryCompilerautomaticallycompilesandstoresthecorrectsimulationmodellibrariesforfunctionalandgate-leveltimingsimulationofyourdesign.

RelatedInformation

SimulatingAlteraDesigns

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IntroductiontoMegafunctionIPCores

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