东芝电子可靠性测试

东芝电子可靠性测试

[ 3 ] Reliability Testing

Semiconductor Company

东芝电子可靠性测试

Contents

1. What is Reliability Testing...........................................1

1.1 1.2 1.3 1.4 1.5

Significance and Purpose of Reliability Testing...........................................1 Before Testing.................................................................................................1 Reliability Test Methods.................................................................................3 Failure Assessment Criteria...........................................................................9 Equivalent electrostatic Discharge Test Circuit.........................................10

1.6 Latch-Up Test................................................................................................11

2. Accelerated Life time Tests.......................................12

2.1 2.2 2.3 2.4 2.5 2.6 2.7

Purpose..........................................................................................................12 Constant Stress and Step Stress.................................................................13 Temperature..................................................................................................14 Temperature and Humidity...........................................................................19 Voltage...........................................................................................................21 Temperature Difference................................................................................22 Current...........................................................................................................24

3. Failure Rate Estimation Methods.............................26

3.1 Overview........................................................................................................26 3.2 Estimating Failure Rates Using Accelerated Life time Tests....................26 3.3 Estimating Electronic Equipment Failure Rates Using MIL-HDBK-217....28

4. Detailed Application Methods for Reliability Testing

......................................................................................40

4.1 Design Approval Test Procedures...............................................................40 4.2 Reliability Monitoring during Mass Production..........................................41

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1. What is Reliability Testing

1.1

Significance and Purpose of Reliability Testing

The purpose of semiconductor device reliability testing is primarily to ensure that shipped devices, after assembly and adjustment by the customer, exhibit the desired lifetime, functionality and performance in the hands of the end user.

Nevertheless, there are constraints of time and money. Because semiconductor devices require a long lifetime and low failure rate, to test devices under actual usage conditions would require a great amount of test time and excessively large sample sizes.

The testing time is generally shortened therefore by accelerating voltage, temperature and humidity. In addition, statistical sampling is used, taking into account the similarities between process and design, so as to optimize the number of test samples.

Toshiba performs various reliability testing during new product development following the stages shown in Table 1.1. In recent years, customer demand for shorter development-to-shipment times, and the increasing advancement and complexity of semiconductor devices, has made failure analysis extremely difficult. Consequently, evaluation of basic failure mechanisms must begin in the development phase, dividing products into different test element groups (TEG), such as process TEG and design TEG.

To verify product reliability, various lifetime and environment tests – a process referred to as design approval testing (DAT) – ensure that the required specifications and quality/reliability targets are met.

During mass production, devices are made under strict manufacturing control and screening to eliminate those with a potential for failure and ensure higher reliability. In addition, initial inspections of product characteristics and periodic reliability monitoring are used to assess whether or not the product quality level remains high. Tests are carried out with high efficiency and focus by classifying assessment levels according to product innovation and importance, and defining test items and assessment standards accordingly.

The various reliability testing described above, through problem identification and correction at each phase of device development, is used to provide customers with a level of reliability that ensures safe product use, and to maintain and improve reliability in the manufacturing phase as well.

1.2 Before Testing

The following points must be considered before implementing reliability tests in order to satisfy the objectives described above:

(1) For what applications will the device be used?

(2) In what possible environments and operating conditions will the device be used?

(3) What are the possible failure modes and mechanisms, and what kind of accelerated stress testing is

appropriate?

(4) What level of reliability (failure rate, for example) does the market require for the device? (5) How long is the device expected to be in service?

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(6) How does the device rate in terms of innovation and importance?These points must be considered when

determining tests, stress conditions and sample sizes.

The following are accelerated stresses which can be applied to devices. They are described in detail in Section 3.2. (1) Temperature

(2) Temperature and humidity (3) Voltage

(4) Temperature difference (5) Current

The various tests and test conditions for each stress type are described in later sections.

An important consideration in reliability testing is that the testing must contribute to the appropriate evaluation and improvement of semiconductor device reliability.

It is therefore important to accumulate reliability testing results, to perform detailed failure analysis when failure occurs, and to feed back the results to the design department and manufacturing process.

Table 1.1 Main Stages, Purposes and Contents of Reliability Testing

Material, process and basic design verification

To assess whether the

material, process and design rules enable satisfaction of designed quality/reliability objectives and user

specifications when applied to the product.

To assess whether the

product design satisfies the designed quality/reliability objectives and user specifications.

Content

Sample

Semiconductor Device Development

Process TEGs, Metal (Al, Cu) electromigration and stress migration

function block evaluation, gate oxide film breakdown voltage

evaluation (TDDB test, breakdown voltage test), MOS TEGs, etc. transistor hot carrier injection (HCI) effect, negative bias temperature instability (NBTI) evaluation, failure rate for medium- and large-scale integrated circuits or products, new package mechanical strength and environment test, etc.

Development verification tests (lifetime test, environment test, etc.), structural analysis

Products

Product reliability verification

To assess whether the Screening and reliability monitoring (by Si process product quality and reliability generation and product family) are maintained at prescribed levels.

Products, TEGs

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1.3 Reliability Test Methods

Reliability test methods include TEG evaluation, in which special sets of devices (referred to as a test element group or TEG) are created for each failure cause, and product evaluation, whereby the product is comprehensively evaluated.

1.3.1 TEG Evaluation

TEG evaluation targets basic failure mechanisms. In this method, a set of devices is manufactured especially for the evaluation and analysis of each failure mechanism. The method allows detailed evaluation and failure analysis of failure mechanisms, and is very effective for quantifying limits and acceleration capabilities. Table 1.2 shows an example of TEG evaluation method.

Depending on the objective, TEG evaluation can be performed either by on wafer or an encapsulated packag. TEG evaluation has four major objectives:

(1) During DAT (design approval testing) of new technology and products, it is used tofind the method of elimination for failure mechanisms that affect reliability. The various kinds of TEG shown in Table 1.2 are used to evaluate failure mechanisms attributable to the process or the design.

(2) Clarify failure mechanisms involved in defects found during the product evaluation phase.

(3) For monitoring manufacturing process parameters, monitor process quality control items such as film thickness, film shape and contamination, and failure rates for each process and design rule.

(4) Develop TEG for each function block and estimate product reliability lifetime and failure rate from each TEG combination.

In this manner, the TEG can be used for various purposes to precisely obtain appropriate data.

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Table 1.2 TEG Evaluation Examples

TEG Structure MOS capacitor

Evaluation Target Gate oxide film breakdown Ion drift

Interface trap Process damage Variation in manufacturing conditions

Radiation effect

Design Process Parameter Gate film thickness

Gate film quality Oxidation methodGate film materialElectrode materialContamination Surface area Shape

Dimensions Gate size (W/L) Gate film thickness

Gate film quality Electrode materialContamination Passivation material Shape and structure

Ion implantation conditions Metallization material

Metallization widthMetallization space

Through-hole diameter

Contact diameterStep, hole shapeInterlayer insulating film Passivation Molding resin Shape,

dimensions, number of elements Gate film thickness

Gate film quality Interlayer film quality

Stress TemperatureVoltage Electric fieldCurrent

Evaluation Method TDDB (constant current, constant voltage, step stress) Oxide film breakdown voltage test

C-V (Pulse C-V) DLTS (deep level

transient spectroscopy)

Evaluation ParametersFailure rate vs. time Oxide film breakdown voltage

QBD (oxide film breakdown static charge)

Electric field acceleration coefficient

Activation energy COX (oxide film capacitance) Failure rate

Vth (threshold voltage degradation)

Id (drain current degradation)

gm (gm degradation) Voltage acceleration coefficient

Activation energy Sub-threshold characteristics

Field breakdown voltage Resistance change Failure rate vs. time Activation energy Current density dependence Open Short

MOS transistor

Hot carrier effect

Negative bias stability Ion drift

Interface trap Variation in manufacturing conditions

Process damage Short channel effect Field leak

TemperatureElectric fieldMechanical stress Current

High-temperature DC biasing

Low-temperature DC biasing

Charge pumping DC pulse

Multi-layer metallization (metal, diffusion layer, interlayer insulating film)

Stress Migration

Electromigration Contact open

Interlayer breakdown voltage Corrosion

TemperatureCurrent density

Temperature gradient Voltage Mechanical stress

Temperature and humidity

High temperature, constant current test High-temperature discharge

Temperature cycle Reflow process High-temperature, high-humidity biasing Pressure cooker

Function block

Process monitoring Failure rate estimation Process approval Humidity resistance

TemperatureHigh-temperature Voltage biasing (DC, pulse)

Low-temperature biasing (DC, pulse) High-temperature discharge, etc.

Failure rate vs. time Activation energy Voltage acceleration Standby current AC/DC parameters

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1.3.2 Product Evaluation

TEG evaluation produces detailed and well-related data for each failure mechanism. However, defects due to inconsistencies and the synergy effect resulting from combinations of failure mechanisms are difficult to be detected. Therefore, as a complement to TEG evaluation, a comprehensive product evaluation must be performed.

Product reliability testing is preferably performed under actual field environment conditions to the extent possible and must always be repeatable. For this reason, standardized test methods are preferably selected to the extent possible, and tests should be performed according to approved semiconductor device standards, such as JIS, JEITA, MIL, IEC and JEDEC. Table 1.3 shows representative tests for these standards.

Toshiba performs tests common to semiconductor products in accordance with test methods compliant with JIS, MIL, IEC, JEITA and JEDEC standards, as shown in Table 1.4. In addition, tests for electrostatic discharge (ESD), latch-up, soft error and other conditions are performed under field environmental and climatic conditions.

Table 1.3 Reliability Test Standards

Japan Electronics and Information Technology Industries Association (JEITTA) Standards

EIAJ ED-4701/001

EIAJ ED-4701/100 EIAJ ED-4701/200 EIAJ ED-4701/300 EIAJ ED-4701/400 EIAJ ED-4701/500

US Military (MIL) Standards

MIL-STD-202 MIL-STD-883 IEC 60749 IEC 60068-1 IEC 60068-2 JESD 22 JESD 78

[General]

JIS C 00XX (IEC 60068-2) CECC 90000 CECC 90100

Test Methods for Electronic and Electrical Parts Test Methods and Procedures for Microelectronics

Semiconductor devices- Mechanical and climatic test methods Environmental testing Part 1: General and guidance Environmental testing Part 2

Series Test Methods IC Latch-Up Test

Environmentarl and endurance test methods for Semiconductor Devices (General)

Environmentarl and endurance test methods for Semiconductor Devices (Lifetime Test I) Environmentarl and endurance test methods for Semiconductor Devices (Lifetime Test II)Environmentarl and endurance test methods for Semiconductor Devices (Strength Test I)Environmentarl and endurance test methods for Semiconductor Devices (Strength Test II)Environmentarl and endurance test methods for Semiconductor Devices (Other Tests)

International Electrotechnical Commission (IEC) Standards

Joint Electron Devices Engineering (JEDEC) Standards

Japanese Industrial Standards (JIS)

Environment Testing Methods (Electricity and Electronics) Series General Specification Monolithic Integrated Circuit

General Specification Digital Monolithic Integrated Circuit

CENELEC Electronic Components Committee (CECC)

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Table 1.4 Product Reliability Test Method Examples (1/2)

东芝电子可靠性测试

Table 1.4 Product Reliability Test Examples (2/2)

Type

Standards

Test

Description and Test Conditions

EIAJ ED-4701

MIL-STD-883IEC 60749

JESD22

Vibration test Evaluate resistance to the vibration applied during

transport and usage. The test includes variable and constant frequency vibration; normally variable is used.

Normal test conditions:

Constant frequency vibration: 60 ± 20 Hz, 200 m/s2 in three directions, 96 ± 8H in each

direction

Variable frequency vibration: 100 to 2000 Hz 200 m/s2 in three directions, four cycles per direction, four minutes per cycle

Mechanical Shock test

Evaluate resistance to the shock applied during transport and usage. Normal test conditions:

Depends on device structure. With resin molded devices, shock acceleration of 15,000 m/s2 is applied three times in each of four directions. Evaluate resistance to constant acceleration. Normal test conditions:

Depends on device structure. With resin molded devices, acceleration of 200,000 m/s2 is applied in six direction, each for one minute Evaluate whether or not the strength of the terminal area is sufficient for the force applied during installation and usage. Normal test conditions:

Suspend a prescribed load onto the tip of the lead to bend it 90° and back. Apply tensile force

in a direction parallel to the lead. The prescribed load varies according to device structure.

Solder- ability test

Evaluate terminal solderability. Normal test conditions:

Solder bath temperature: 230°C, Dipping time: 5 sec.

Solder bath temperature: 245°C, Dipping time: 3 sec. (lead-free solder)

Sealing test

Evaluate the airtightness of the seal. Use bubbles to detect large leaks. This test is suitable for metallic and ceramic packages.

Evaluate the resistance to corrosion in a salt atmosphere.

Normal test conditions:

35°C, 5% salt solution, 24 hours

Mechanical Tests

Constant

acceleration test

―

Terminal

strength test

Salt

atmosphere test

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Standards

Type

Test Description and Test Conditions

EIAJ ED-4701―

MIL-STD-883IEC 60749

―

Part 33

JESD22 A102-C

Pressure cooker test

Evaluate resistance when stored under pressure under high temperature, high humidity for a short period of time. Normal test conditions: 203 to 255kPa, RH = 100%

Other

Electrostatic Evaluate the resistance to static electricity. discharge test Normal test conditions:

Human body model: C = 100 pF, R = 1.5 k ,

three discharges

Machine model: C = 200 pF, R = 0 , one discharge

Device charge model

Latch-up strength test

Evaluate resistance to latch-up. Normal test conditions:

Pulse current injection method, current

application method, voltage application method

Part A114-C/

Part 27 A115-A/

C101-C (Part 28)

306 ― Part 29 JESD78

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1.4 Failure Assessment Criteria

In general, failures are divided into fatal failures such as functional failure, opens and shorts, and other failures such as degradation of electrical characteristics and defective outer appearance which is detected as the failure in visual inspection. Toshiba in principle assesses failures based on the satisfaction of standards stipulated in specifications for the device.

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1.5 Equivalent Electrostatic Discharge Test Circuit

(1) Human Body Model (HBM)

Figure 1.1 Equivalent circuit for Human Body Model (HBM) Test

(2) Machine Model (MM)

Figure 1.2 Equivalent circuit for Machine Model (MM) Test

(3)

Charged Device Model (CDM)

Figure 1.3 Schematic images of Charged Device Model (CDM) Test

(Left: Relay Discharge Method, Right: Field induced Method)

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1.6 Latch-Up Test

The following shows two latch-up test circuit and the results of test implementation.

(1)

Test Circuit

Figure 1.4 Latch-Up Test Circuit

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2. Accelerated Lifetime Tests

2.1 Purpose

With the ever-increasing requirements for part and device reliability, the need to evaluate product lifetime and failure rates quickly is now greater than ever. Reliability tests are conducted under test conditions that simulate potential stresses applied to semiconductor components. Depending on the situation, however, it may take an exceedingly long time until failure occurs or failure may not occur within the limited test time. Therefore, stresses beyond those of actual operating conditions are applied to devices to physically and/or chronologically accelerate causes of degradation. In this way, device lifetime and failure rates can be determined, and failure mechanisms can be analyzed. This type of test is referred to as an accelerated lifetime test. Such tests are used to shorten the evaluation period and analyze mechanisms in detail.

The accelerated lifetime test is also sometimes used as a forced degradation test to forcibly accelerate a constant stress. It is also sometimes used as a limit test for accelerating stress to determine a limit value.

It is necessary to be noted that failure mechanisms in accelerated tests differ somewhat from those that occur under actual usage conditions. In general, if the degradation mechanism is simple, acceleration is also simple and lifetime and failure rates can be estimated relatively accurately. Complicated failure mechanisms, however, are difficult to simulate, even when best efforts are made to accelerate stresses simultaneously. This is because the different stress effects are interrelated. Therefore, analysis of acceleration data as well as estimation of lifetime and failure rates can be difficult. When performing accelerated lifetime tests, it is important to select test conditions that result in as few failure mechanism changes as possible and that minimize the number of failure mechanisms, making testing easy and simple.

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2.2 Constant Stress and Step Stress

There are two types of accelerated lifetime testing: constant stress and step stress. In a constant stress test, the time-dependent failure distribution of a test sample subjected to constant stress at several stress levels is observed. In a step stress test, stress is applied to a test sample gradually in stepped increments, and the step at which failure occurs is observed.

A typical constant stress test is the application of the constant stress of power or ambient temperature exceeding the maximum rating. Weibull distribution is often used to verify that the failure mode has not been changed by the test. The validity of the accelerated test is confirmed if the shape parameter m of the Weibull distribution remains unchanged by the accelerated stress.

Figure 2.1 shows Weibull plots when the power consumption of a silicon transistor is changed. It is evident from the figure that parameter m is constant regardless of the power consumption level.

Figure 2.1 Weibull Distribution and Shape Parameter for Transistor Accelerated Lifetime Test

This same result should occur in both constant tests and step tests.

Thus, a step test produces the failure data corresponding to at least one constant stress. If the failure mode of the previous step is the same, a step test can by used to determine the critical temperature for the component and to estimate its lifetime. Figure 2.2 shows an example.

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[ 3 ] Reliability Testing

Figure 2.2 Failure Rate Estimation Step Stress

2.3 Temperature

Accelerated lifetime testing is closely associated with the physics of the failure. The physical and chemical reactions of device degradation are generally used as chemical kinetics. Chemical kinetics is a basic chemical reaction model that describes the temperature dependence of failures. It is used with the Arrhenius model1 in accelerated lifetime testing of semiconductor devices in relation to temperature stress.

Given a chemical reaction speed K, the Arrhenius equation can be expressed as:

Ea Ea: Activation energy (eV) K=Aexp

k: Boltzmann’s constant (8.617×10－5[eV/K] ( 1.380×10－23[J/K]))

T: Absolute temperature (K)

A:Constant

If the product’s lifetime ends at a certain degradation a, then lifetime L can be expressed as L = a/K. Given a/A = A’:

L=A'exp

kT

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[ 3 ] Reliability Testing

This equation expresses the relationship between temperature and lifetime. If the failure mechanism is uniform, lnL and 1/T can be plotted on a straight line as shown in Figure 2.3. That is, the acceleration from temperature T1 to T2 is lnL1/lnL2.

lnL2Lifetime lnL1

1/T11/T2

Temperature

(K)

Figure 2.3 Relationship between Lifetime and Temperature

Given acceleration coefficient α and the lifetimetimes L1 and L2 at temperatures T1 and T2, respectively, the acceleration coefficient α can be found using the following formula:

L Ea: Activation energy (eV) α=2=exp 11 2

k: Boltzmann’s constant

temperature (K) T1, T2: Absolute

Figure 2.4 shows the relationship between the activation energy and the acceleration coefficient at each temperature.

It can be seen from the Arrhenius equation that the acceleration due to temperature changes drastically with the activation energy Ea. Figure 2.5 shows the relationship between each activation energy level and the accelerated coefficient when the temperature difference as a parameter.

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[ 3 ] Reliability Testing

Figure 2.4 Relationship between Activation Energy and Acceleration Coefficient

Figure 2.5 Relationship between Temperature and Acceleration Coefficient Using Activation

Energy as a Parameter

Numerous sets of data have been disclosed regarding the relationship between temperature and lifetime or failure rate of semiconductor devices. Some examples of data from experiments conducted by Toshiba are as follows:

(1) Temperature Acceleration of Intermetallic Formation of Bonding Wire

As temperature rises, intermetallic alloy begins to form at the junction of Au wire and the Al used on the pad, causing the contact resistance to increase and the contact to open. Figure 2.6 shows the relationship between the temperature and lifetime from the results of high-temperature storage testing.

From the lifetime values at different temperature conditions, it can be seen that the activation energy is approximately 1.0 eV.

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Figure 2.6 Temperature Dependence of Formation of Intermetallic Alloy in Bonding Wire

(2) Temperature Acceleration on Different Semiconductor Devices

Various data have been reported for the relationship between the temperature and failure rate of semiconductor devices. Figure 2.7 shows an example of data obtained from this type of experiment. The figure gives the acceleration rate for each device.

105 104 Acceleration Rate

10

3

MOS IC

102 10 1

Bip IC

2.42.62.83.075

3.23.41/T × 103 (K 1)50

25

(°C)

150125100

Temperature

Figure 2.7 Example of Device Temperature Acceleration

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The activation energy differs according to the failure mechanism. Table 2.1 shows typical failure mechanisms and activation energy values obtained from experiments performed by Toshiba and other organizations.

Table 2.1 Main Failure Mechanisms and Activation Energy Values (Examples)

Failure Mode

Failure Mechanism

Al metal electromigration

Metal wiring failure (open, short, corrosion)

Al metal stress migration Au-Al alloy growth Cu metal electromigration Al corrosion (moisture penetration)

Oxide film voltage breakdown (insulation breakdown, Oxide film breakdown leakage current increase) hFE degradation Characteristic value fluctuation

Increased leakage current

Ion movement acceleration due to moisture Degradation by NBTI Na ion drive in SiO2

Slow trapping of Si-SiO2 interface Inversion layer formation

Activation Energy (ev)

0.4 to 1.2 0.5 to 1.4 0.85 to 1.1 0.8 to 1.0 0.6 to 1.2 0.3 to0.9 0.8 0.5 and up 1.0 to 1.4 1.0 0.8 to 1.0

Note: The above-described obtained values differ according to the Si process generation and

detailed structure. These values reflect results actually obtained as well as results from reported cases.

The model described so far was the Arrhenius model for temperature acceleration. Another failure model is the Eyring model. This model considers the effects of humidity, voltage and mechanical stress in addition to temperature. Given an average lifetime L, the relationship to temperature and stress can be expressed as:

lnL=A+ αlnS L: Average lifetime

A, B, α: Constants

T: Temperature (K)

S: Stress other than temperature

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2.4 Temperature and Humidity

2.4.1 Moisture Resistance Tests

Most semiconductors devices of recent years are encapsulated in plastic resin. The reliability of these devices largely depends on the moisture resistance of the package. Various types of moisture resistance evaluations tests have been developed in order to evaluate these devices quickly. Table 2.2 shows examples of these moisture resistance evaluation tests.

The tests are largely divided into two groups. The first group places the device in a humid atmosphere, and the second group applies bias to the device while subjecting it to humidity or after moisture has penetrated into the device. The device classification is made according to the device type (such as the level of power consumption) and the type of failure mechanism to be detected.

If the acceleration rate is too fast, humidity resistance testing can produce failure modes that are different from those that appear during actual usage or problems related to test reproducibility may arise. Therefore, extra care must be taken when performing these tests. Particularly with saturated type PCTs (pressure cooker tests), unexpected failure modes that will never occur in the field (for example, pin-to-pin migration on outer leads) can occur because the device may be exposed to conditions in which dew is formed. Consequently, care must be taken when performing assessments or when evaluating test results.

In addition, recently the mainstream semiconductor device has become the surface mounted device (SMD), accelerating compact and thin designs one step further. With these types of semiconductor devices, the thermal stress during mounting and resin humidity absorption during storage cannot be ignored. To properly simulate actual usage conditions, the mounting stress is applied as part of a pretreatment process, and a humidity resistance test is conducted.

Table 2.2 Main Moisture Resistance Evaluation Test Methods

Temperaturehumidity storage test

Saturation type

Pressure cooker test

Non-

saturation type

85°C/85% RH 60°C/90% RH 121°C/100% RH 127°C/100% RH 120°C/85% RH 130°C/85% RH 85°C/85% RH Biasing applied 130°C/85% RH Biasing applied

Shelf Test Biasing

Temperaturehumidity bias test High-acceleration stress test

Pressure cooker test, high temperature bias 121°C, 203kPa (20h) → Left at room temperature (2h) → high test (compound stress test) temperature bias t (20h)

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