计算机组成原理大作业I

计算机组成原理大 作 业

《 计算机组成原理 》大作业 （I） 2、Consider a hypothetical microprocessor generating a 16-bit address (for example, assume that the program counter and the address registers are 16 bits wide) and having a 16-bit data bus.(12 points) 使用专业、班级 学号 姓名 l a). What is the maximum memory address space that the processor can access directly if it is connected to a “16-bit memory”? 题 数 一 二 总 分 b). What is the maximum memory address space that the processor can access directly if it is connected to an “8-bit memory”? 得 分 c). What architectural features will allow this microprocessor to access a separate “I/O space”? d). If an input and an output instruction can specify an 8-bit I/O port number, how many 8-bit I/O ports can the microprocessor support? How many 16-bit I/O ports? Explain. 一、系统总线部分 〖共计30分〗 1、Consider a hypothetical 32-bit microprocessor having 32-bit instructions composed of two fields: the first byte contains the opcode and the remainder the immediate operand or an operand address.(10 points) a). What is the maximum directly addressable memory capacity (in bytes)? b). Discuss the impact on the system speed if the microprocessor bus has (1). a 32-bit local address bus and a 16-bit local data bus, or (2). a 16-bit local address bus and a 16-bit local data bus. c). How many bits are needed for the program counter and the instruction register?

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计算机组成原理大 作 业

3、Consider a 32-bit microprocessor whose bus cycle is the same duration as that of a 16-bit microprocessor. Assume that, on average, 20% of the operands and instructions are 32 bits long, 40% are 16 bits long, and 40% are only 8 bits long. Calculate the improvement achieved when fetching instructions and operands with the 32-bit microprocessor.(8 points)

二、存储器部分 〖共计70分〗 2、Consider a computer with the following characteristics: total of 1Mbyte of main

1、Consider a 32-bit microprocessor that has an on-chip 16-Kbyte four-way setassociative memory; word size of 1 byte; block size of 16 bytes; and cache size of 64 Kbytes. (25 points) cache. Assume that the cache has a line size of four 32-bit words. Draw a block diagram of a). For the main memory addresses of F0010, 01234, and CABBE, give the corresponding this cache showing its organization and how the different address fields are used to determine tag, cache line address, and word offsets for a direct-mapped cache.

a cache hit/miss. Where in the cache is the word from memory location ABCDE8F8 mapped? b). Give any two main memory addresses with different tags that map to the same (25 points) cache slot for a direct-mapped cache. c). For the main memory addresses of F0010 and CABBE, give the corresponding tag and offset values for a fully-associative cache. d). For the main memory addresses of F0010 and CABBE, give the corresponding tag, cache set, and offset values for a two-way set-associative cache.

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计算机组成原理大 作 业

3、A computer system contains a main memory of 32K 16-bit words. It also has a 4Kword cache divided into four-line sets with 64 words per line. Assume that the cache is initially empty. The processor fetches words from locations 0, 1, 2, . . . , 4351 in that order. It then repeats this fetch sequence nine more times. The cache is 10 times faster than main memory. Estimate the improvement resulting from the use of the cache. Assume an LRU policy for block replacement. (10 points)

4、Let’s say this module of chips is packaged as a single 1-Mbyte chip, where the word size is 1 Mbyte. Give a high-level chip diagram of how to construct an 8-Mbyte computer

memory using eight 1-Mbyte chips. Be sure to show the address lines in your diagram and what the address lines are used for (10 points)

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