MC68HC811A0VFN1中文资料

HC11

MC68HC11D3Technical Data

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TECHNICAL DATA v Table of Contents (Cont.)Paragraph Number Page Number

6.4 Port D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

6.5 Parallel I/O Control Register (PIOC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

Section 7

SERIAL COMMUNICATIONS INTERFACE

7.1 Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

7.2 Transmit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

7.3 Receive Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2

7.4 Wake-up Feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4

7.4.1 Idle-Line Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4

7.4.2 Address-Mark Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4

7.5 SCI Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5

7.6 SCI Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5

7.6.1 Serial Communications Data Register (SCDR) . . . . . . . . . . . . . . . . . . . . . . 7-5

7.6.2 Serial Communications Control Register 1 (SCCR1). . . . . . . . . . . . . . . . . . 7-5

7.6.3 Serial Communications Control Register 2 (SCCR2). . . . . . . . . . . . . . . . . . 7-6

7.6.4 Serial Communication Status Register (SCSR). . . . . . . . . . . . . . . . . . . . . . 7-7

7.6.5 Baud Rate Register (BAUD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8

7.7 Status Flags and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10

Section 8

SERIAL PERIPHERAL INTERFACE

8.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1

8.2 SPI Transfer Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2

8.2.1 Clock Phase and Polarity Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3

8.3 SPI Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3

8.3.1 Master In Slave Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

8.3.2 Master Out Slave In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

8.3.3 Serial Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

8.3.4 Slave Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

8.4 SPI System Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

8.5 SPI Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5

8.5.1 Serial Peripheral Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6

8.5.2 Serial Peripheral Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7

8.5.3 Serial Peripheral Data I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7

Section 9

TIMING SYSTEM

9.1 Timer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3

9.2 Input Capture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4

9.2.1 Timer Control 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5

9.2.2 Timer Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6

9.2.3 Timer Input Capture 4/Output Compare 5 Register . . . . . . . . . . . . . . . . . . . 9-6

9.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6

9.3.1 Timer Output Compare Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7

9.3.2 Timer Compare Force Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8

9.3.3 Output Compare Mask Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8

9.3.4 Output Compare 1 Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9

9.3.5 Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9

9.3.6 Timer Control 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9

9.3.7 Timer Interrupt Mask 1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10

9.3.8 Timer Interrupt Flag 1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10

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vi TECHNICAL DATA

Table of Contents (Cont.)Paragraph

Number Page Number 9.3.9 Timer Interrupt Mask 2 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-119.3.10 Timer Interrupt Flag 2 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-129.4 Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-129.4.1 Timer Interrupt Flag 2 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-139.4.2 Pulse Accumulator Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-149.5 Computer Operating Properly Watchdog Function . . . . . . . . . . . . . . . . . . . . . . . 9-159.6 Pulse Accumulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-159.6.1 Pulse Accumulator Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-179.6.2 Pulse Accumulator Count Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-179.6.3 Pulse Accumulator Status and Interrupt Bits . . . . . . . . . . . . . . . . . . . . . . . 9-18Appendix A ELECTRICAL CHARACTERISTICS Appendix B MECHANICAL DATA AND ORDERING INFORMATION B.1 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1B.2 Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3B.3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3Appendix C DEVELOPMENT SUPPORT C.1 Development System Tools. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1C.2 MC68HC11D3 Development Tools. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1INDEX

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MC68HC11D3

TA

Figure

Title Page LIST OF ILLUSTRATIONS

1-1

MC68HC11D3 Block Diagram ........................................................................1-22-1

Pin Assignments for 44-Pin PLCC .................................................................2-12-2

Pin Assignments for 40-Pin DIP .....................................................................2-22-3

External Reset Circuit .....................................................................................2-32-4

Common Crystal Connections ........................................................................2-32-5

External Oscillator Connections .....................................................................2-42-6One Crystal Driving Two MCUs .....................................................................2-4

3-1Programming Model .......................................................................................3-13-2Stacking Operations .......................................................................................3-34-1Address/Data Demultiplexing .........................................................................4-24-2MC68HC11D3 Memory Map ..........................................................................4-34-3RAM Standby MODB/V STBY Connections ......................................................4-65-1Processing Flow out of Reset (1 of 2) ..........................................................5-125-2Interrupt Priority Resolution (1 of 2) .............................................................5-145-3Interrupt Source Resolution within SCI ........................................................5-167-1SCI Transmitter Block Diagram ......................................................................7-27-2SCI Receiver Block Diagram ..........................................................................7-37-3SCI Baud Rate Diagram ...............................................................................7-107-4Interrupt Source Resolution within SCI ........................................................7-128-1SPI Block Diagram .........................................................................................8-28-2SPI Transfer Format .......................................................................................8-39-1Timer Clock Divider Chains ............................................................................9-29-2Capture/Compare Block Diagram ..................................................................9-49-3Pulse Accumulator .......................................................................................9-16A-1Test Methods ..................................................................................................A-3A-2Timer Inputs ...................................................................................................A-4A-3POR and External Reset Timing Diagram ......................................................A-5A-4STOP Recovery Timing Diagram ...................................................................A-6A-5WAIT Recovery Timing Diagram ....................................................................A-7A-6Port Write Timing Diagram .............................................................................A-8A-7Port Read Timing Diagram .............................................................................A-8A-8Multiplexed Expansion Bus Timing Diagram ................................................A-10A-9

SPI Master Timing (CPHA = 0) ....................................................................A-12

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TECHNI

(Continued)Figure Title Page LIST OF ILLUSTRATIONS

A-10

SPI Master Timing (CPHA = 1) ....................................................................A-12A-11

SPI Slave Timing (CPHA = 0) ......................................................................A-13A-12

SPI Slave Timing (CPHA = 1) ......................................................................A-13B-1

40-Pin DIP ......................................................................................................B-1B-2

44-Pin PLCC ..................................................................................................B-2B-344-Pin QFP .....................................................................................................B-3

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MC68HC11D3

TA

Table Title Page LIST OF TABLES

2-1 Port Signal Functions.............................................................................................2-63-2 Instruction Set........................................................................................................3-84-1 Register and Control Bit Assignments .................................................................4-44-2 Hardware Mode Select Summary..........................................................................4-64-3 RAM Mapping........................................................................................................4-94-4 Register Mapping...................................................................................................4-9

5-1 COP Time-out........................................................................................................5-25-2 Reset Cause, Reset Vector, and Operating Mode................................................5-45-3 Highest Priority Interrupt Selection........................................................................5-85-4 Interrupt and Reset Vector Assignments...............................................................5-95-5 Stacking Order on Entry to Interrupts..................................................................5-107-1 Baud Rate Prescale Selects..................................................................................7-87-2 Baud Rate Selects................................................................................................7-99-1 Timer Summary.....................................................................................................9-39-2 Timer Control Configuration...................................................................................9-59-3 Pulse Accumulator Timing...................................................................................9-16A-1 Maximum Ratings..................................................................................................A-1A-2 Thermal Characteristics........................................................................................A-1A-3 DC Electrical Characteristics.................................................................................A-2A-4 Control Timing.......................................................................................................A-4A-5 Peripheral Port Timing...........................................................................................A-8A-6 Expansion Bus Timing...........................................................................................A-9A-7 Serial Peripheral Interface Timing.......................................................................A-11B-1 Ordering Information.............................................................................................B-3

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INTRODUCTION

TECHNICAL DATA 1-1SECTION 1

INTRODUCTION

The MC68HC11D3 and MC68HC11D0 are ROM-based high-performance microcon-trollers (MCUs) based on the MC68HC11E9 design. Members of the Dx series are de-rived from the same mask and feature a high speed multiplexed bus capable of running at up to 3 MHz, and a fully static design that allows operations at frequencies to dc.

The only difference between the MCUs in the Dx series is whether or not the ROM has been tested and guaranteed.

1.1 Features

? MC68HC11 CPU

? Power Saving STOP and WAIT Modes

? 4 Kbytes of On-Chip ROM

? 192 Bytes of On-Chip RAM (All Saved During Standby)

? 16-Bit Timer System

— 3 Input Capture (IC) Channels

— 4 Output Compare (OC) Channels

— One IC or OC Channel (Software Selectable)

? 8-Bit Pulse Accumulator

? Real-Time Interrupt Circuit

? Computer Operating Properly (COP) Watchdog System

? Synchronous Serial Peripheral Interface (SPI)

? Asynchronous Nonreturn to Zero (NRZ) Serial Communications Interface (SCI)? 26 Input/Output (I/O) Pins

— 16 Bidirectional I/O Pins

— 3 Input Only Pins

— 3 Output Only Pins (One Output Only Pin in the 40-Pin Package)

? Available in a 44-Pin Plastic Leaded Chip Carrier (PLCC) and 40-Pin Dual In-Line Package (DIP)

1.2 Structure

Refer to Figure 1-1, which shows the structure of the MC68HC11D3 MCU.

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PIN DESCRIPTIONS

2-8TECHNICAL DATA output port suitable for wired-OR operation. In wired-OR mode (a port C bit is at logic level zero), it is actively driven low by the N-channel driver. When a port C bit is at logic level one, the associated pin has high impedance, as neither the N- nor the P-channel devices are active. It is customary to have an external pullup resistor on lines that are driven by open-drain devices. Port C can only be configured for wired-OR operation when the MCU is in single-chip mode. Refer to SECTION 6 PARALLEL I/O for addi-tional information about port C functions.

2.10.4 Port D

Port D, an 8-bit, general-purpose I/O port has a data register (PORTD) and a data di-rection register (DDRD). The eight port D bits (D[7:0]) can be used for general-purpose I/O, for the serial communications interface (SCI) and serial peripheral interface (SPI)subsystems, or for bus data direction control. Port D can be read at any time and inputs return the sensed levels at the pin; whereas,the outputs return the input level of the port D pin drivers. If PORTD is written, the data is stored in an internal latch, and can be driven only if port D is configured for general-purpose output. This port shares functions with the on-chip SCI and SPI subsystems,while bits 6 and 7 control the direction of data flow on the bus in expanded and special test modes. Refer to SECTION 6 PARALLEL I/O .

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