DSP2812相关代码和程序

/******************************************************************/ /*Copyright (C), 2008-2009, 力天电子，LiTian Tech.Co.Ltd. */ /* Module Name : XNMI */ /* File Name : main.c */ /* Author : 侯长波 */ /* Create Date : 2009/12/27 */

/* Version : 2.0 */ /* Function : */ /* Description : */ /* Support : www.LT430.com */ /******************************************************************/

/*****************头文件********************/ #include \#include \

/****************端口宏定义*****************/ #define S1 GpioDataRegs.GPEDAT.bit.GPIOE2

#define LED1_DIR GpioMuxRegs.GPBDIR.bit.GPIOB0

#define LED1_TOGGLE GpioDataRegs.GPBTOGGLE.bit.GPIOB0 #define LED1_DAT GpioDataRegs.GPBDAT.bit.GPIOB0

/****************常量宏定义*****************/

/***************全局变量定义****************/

/****************函数声明*******************/ void Manage_S1(void); //按键1处理程序 void Init_XNMI(void); interrupt void KEY(void);

/*------------------------------------------*/

/*形式参数：void */ /*返回值:void */ /*函数描述:主函数 */ /*------------------------------------------*/ void main(void) {

InitSysCtrl(); // 系统初始化子程序 Init_XNMI(); LED1_DAT=1;//发光二极管对应引脚初始化 EALLOW; LED1_DIR=1;//发光二极管对应引脚输出 EDIS;

while(1); }

/*------------------------------------------*/ /*形式参数：void */ /*返回值:void */ /*函数描述:按键S1的处理程序 */ /*------------------------------------------*/ void Manage_S1(void) { LED1_TOGGLE=1;//取反 }

/*------------------------------------------*/

/*形式参数：void */ /*返回值:void */

/*函数描述:XINT13中断设置 */ /*------------------------------------------*/ void Init_XNMI(void) {

DINT; //关闭总中断 EALLOW; GpioMuxRegs.GPEMUX.bit.XNMI_XINT13_GPIOE2 = 1; //引脚配置成XNMI XIntruptRegs.XNMICR.bit.POLARITY=0;//下降沿产生中断 XIntruptRegs.XNMICR.bit.SELECT=0; //CPU_Timer1连接到XINT13 XIntruptRegs.XNMICR.bit.ENABLE=1; //使能非屏蔽中断NMI PieVectTable.XNMI= &KEY; //中断服务程序入口地址放入中断向量表 EDIS; EINT; }

/*------------------------------------------*/

/*形式参数：void */ /*返回值:void */ /*函数描述:XNMI中断处理函数 */ /*------------------------------------------*/ interrupt void KEY(void) { unsigned int i; DINT;//关闭总中断 for(i=0;i<2000;i++); //键盘消抖动 if(S1==0) Manage_S1(); while(S1==0);//等待按键释放

EINT; //开总中断 }

/******************************************************************/ /*Copyright (C), 2008-2009, 力天电子，LiTian Tech.Co.Ltd. */ /* Module Name : system */ /* File Name : DSP281x_SysCtrl.c */ /* Author : 侯长波 */ /* Create Date : 2009/12/1 */

/* Version : 2.0 */ /* Function :初始化系统，包括看门狗、系统时钟、外设时钟 */

/* 中断积存器、中断向量表 */ /* Description : */ /* Support : www.LT430.com */ /******************************************************************/ #include \#include \

#pragma CODE_SECTION(InitFlash, \

/*------------------------------------------*/

/*形式参数：void */ /*返回值:void */ /*函数描述:初始化系统 */ /*------------------------------------------*/ void InitSysCtrl(void) {

DisableDog();//禁止看门狗

InitPll(0x2);//设置系统时钟=XCLKIN*2/2 InitPeripheralClocks(); //设置外设时钟 DINT; // 关闭总中断 IER = 0x0000; // 关闭外设中断 IFR = 0x0000; // 清中断标志 InitPieCtrl(); //初始化PIE控制寄存器 InitPieVectTable(); //使能PIE向量表 }

/*------------------------------------------*/

/*形式参数：void */ /*返回值:void */ /*函数描述:禁止看门狗 */ /*------------------------------------------*/

void DisableDog(void) {

EALLOW;

SysCtrlRegs.WDCR= 0x0068; EDIS; }

/*------------------------------------------*/

/*形式参数：void */ /*返回值:void */ /*函数描述:喂看门狗 /*------------------------------------------*/ void KickDog(void) {

EALLOW;

SysCtrlRegs.WDKEY = 0x0055; SysCtrlRegs.WDKEY = 0x00AA; EDIS; }

/*------------------------------------------*/

/*形式参数：void /*返回值:void /*函数描述:设置锁相环倍频系数 /*------------------------------------------*/ void InitPll(Uint16 val) {

volatile Uint16 iVol;

if (SysCtrlRegs.PLLCR.bit.DIV != val) {

EALLOW;

SysCtrlRegs.PLLCR.bit.DIV = val; EDIS;

for(iVol= 0; iVol<4096; iVol++); } }

/*------------------------------------------*/

/*形式参数：void /*返回值:void /*函数描述:初始化外设时钟 /*------------------------------------------*/ void InitPeripheralClocks(void)

*/ */ */ */ */ */ */ {

EALLOW;

SysCtrlRegs.HISPCP.all = 0x0001;//设置高速时钟 2分频 SysCtrlRegs.LOSPCP.all = 0x0002;//设置低速时钟 4分频

//使能外围模块时钟

SysCtrlRegs.PCLKCR.bit.EVAENCLK=1; SysCtrlRegs.PCLKCR.bit.EVBENCLK=1; SysCtrlRegs.PCLKCR.bit.SCIAENCLK=1; SysCtrlRegs.PCLKCR.bit.SCIBENCLK=1; SysCtrlRegs.PCLKCR.bit.MCBSPENCLK=1; SysCtrlRegs.PCLKCR.bit.SPIENCLK=1; SysCtrlRegs.PCLKCR.bit.ECANENCLK=1; SysCtrlRegs.PCLKCR.bit.ADCENCLK=1; EDIS; }

/*------------------------------------------*/

/*形式参数：void */ /*返回值:void */ /*函数描述:初始化Flash */ /*------------------------------------------*/ void InitFlash(void) {

EALLOW;

FlashRegs.FPWR.bit.PWR = 3; //设置Flash为正常工作状态

FlashRegs.FBANKWAIT.bit.RANDWAIT = 5;//设置随机存取等待时间 FlashRegs.FBANKWAIT.bit.PAGEWAIT = 5;//设置页面存取等待时间 FlashRegs.FSTDBYWAIT.bit.STDBYWAIT = 0x01FF; //设置从睡眠到等待的转换时间

FlashRegs.FACTIVEWAIT.bit.ACTIVEWAIT = 0x01FF; //设置从等待到激活的转换时间

FlashRegs.FOPT.bit.ENPIPE = 1; //使能流水线模式 EDIS;

asm(\软件延时，等待流水线刷新 }

/*------------------------------------------*/

/*形式参数：void */ /*返回值:状态值 */ /*函数描述:unlocks the CSM */ /*------------------------------------------*/ #define STATUS_FAIL 0 #define STATUS_SUCCESS 1

Uint16 CsmUnlock() {

volatile Uint16 temp;

// 写入密钥，应将0xFFFF替换成密钥值 EALLOW;

CsmRegs.KEY0 = 0xFFFF; CsmRegs.KEY1 = 0xFFFF; CsmRegs.KEY2 = 0xFFFF; CsmRegs.KEY3 = 0xFFFF; CsmRegs.KEY4 = 0xFFFF; CsmRegs.KEY5 = 0xFFFF; CsmRegs.KEY6 = 0xFFFF; CsmRegs.KEY7 = 0xFFFF; EDIS;

/// 执行空读

temp = CsmPwl.PSWD0; temp = CsmPwl.PSWD1; temp = CsmPwl.PSWD2; temp = CsmPwl.PSWD3; temp = CsmPwl.PSWD4; temp = CsmPwl.PSWD5; temp = CsmPwl.PSWD6; temp = CsmPwl.PSWD7;

if (CsmRegs.CSMSCR.bit.SECURE == 0) return STATUS_SUCCESS; else return STATUS_FAIL; }

/******************************************************************/ /*Copyright (C), 2008-2009, 力天电子，LiTian Tech.Co.Ltd. */ /* Module Name : system */ /* File Name : DSP281x_PieCtrl.c */ /* Author : 侯长波 */ /* Create Date : 2009/12/1 */

/* Version : 2.0 */

/* Function : 初始化PIE控制寄存器 */ /* Description : */ /* Support : www.LT430.com */

/******************************************************************/ #include \

/*------------------------------------------*/

/*形式参数：void */ /*返回值:void */

/*函数描述:初始化PIE控制寄存器 */ /*------------------------------------------*/ void InitPieCtrl(void) {

DINT; //禁止CPU级中断

PieCtrlRegs.PIECRTL.bit.ENPIE = 0;//屏蔽PIE中断向量表 //清除所有PIEIER寄存器 PieCtrlRegs.PIEIER1.all = 0; PieCtrlRegs.PIEIER2.all = 0; PieCtrlRegs.PIEIER3.all = 0; PieCtrlRegs.PIEIER4.all = 0; PieCtrlRegs.PIEIER5.all = 0; PieCtrlRegs.PIEIER6.all = 0; PieCtrlRegs.PIEIER7.all = 0; PieCtrlRegs.PIEIER8.all = 0; PieCtrlRegs.PIEIER9.all = 0; PieCtrlRegs.PIEIER10.all = 0; PieCtrlRegs.PIEIER11.all = 0; PieCtrlRegs.PIEIER12.all = 0; // 清除所有PIEIFR寄存器 PieCtrlRegs.PIEIFR1.all = 0; PieCtrlRegs.PIEIFR2.all = 0; PieCtrlRegs.PIEIFR3.all = 0; PieCtrlRegs.PIEIFR4.all = 0; PieCtrlRegs.PIEIFR5.all = 0; PieCtrlRegs.PIEIFR6.all = 0; PieCtrlRegs.PIEIFR7.all = 0; PieCtrlRegs.PIEIFR8.all = 0; PieCtrlRegs.PIEIFR9.all = 0; PieCtrlRegs.PIEIFR10.all = 0; PieCtrlRegs.PIEIFR11.all = 0; PieCtrlRegs.PIEIFR12.all = 0; }

/*------------------------------------------*/

/*形式参数：void */ /*返回值:void */ /*函数描述:使能所有中断 */ /*------------------------------------------*/ void EnableInterrupts(void) {

//使能PIE中断向量表

PieCtrlRegs.PIECRTL.bit.ENPIE = 1; // 响应所有中断 PieCtrlRegs.PIEACK.all = 0xFFFF; //使能CPU级中断 EINT; }

/******************************************************************/ /*Copyright (C), 2008-2009, 力天电子，LiTian Tech.Co.Ltd. */ /* Module Name : system */ /* File Name : DSP281x_PieVect.c */ /* Author : 侯长波 */ /* Create Date : 2009/12/1 */

/* Version : 2.0 */

/* Function : 初始化PIE向量表 */ /* Description : */ /* Support : www.LT430.com */ /******************************************************************/ #include \ #include \

//中断向量入口值，和DSP281x_DefaultIsr文件中定义的中断函数相对应 const struct PIE_VECT_TABLE PieVectTableInit = {

PIE_RESERVED, // Reserved space PIE_RESERVED, PIE_RESERVED, PIE_RESERVED, PIE_RESERVED, PIE_RESERVED, PIE_RESERVED, PIE_RESERVED, PIE_RESERVED, PIE_RESERVED,

PIE_RESERVED, PIE_RESERVED, PIE_RESERVED,

// Non-Peripheral Interrupts

INT13_ISR, // XINT13 or CPU-Timer 1 INT14_ISR, // CPU-Timer2

DATALOG_ISR, // Datalogging interrupt RTOSINT_ISR, // RTOS interrupt EMUINT_ISR, // Emulation interrupt NMI_ISR, // Non-maskable interrupt ILLEGAL_ISR, // Illegal operation TRAP USER1_ISR, // User Defined trap 1 USER2_ISR, // User Defined trap 2 USER3_ISR, // User Defined trap 3 USER4_ISR, // User Defined trap 4 USER5_ISR, // User Defined trap 5 USER6_ISR, // User Defined trap 6 USER7_ISR, // User Defined trap 7 USER8_ISR, // User Defined trap 8 USER9_ISR, // User Defined trap 9 USER10_ISR, // User Defined trap 10 USER11_ISR, // User Defined trap 11 USER12_ISR, // User Defined trap 12

// Group 1 PIE Vectors

PDPINTA_ISR, // EV-A PDPINTB_ISR, // EV-B rsvd_ISR,

XINT1_ISR, XINT2_ISR,

ADCINT_ISR, // ADC TINT0_ISR, // Timer 0 WAKEINT_ISR, // WD

// Group 2 PIE Vectors

CMP1INT_ISR, // EV-A CMP2INT_ISR, // EV-A CMP3INT_ISR, // EV-A T1PINT_ISR, // EV-A T1CINT_ISR, // EV-A T1UFINT_ISR, // EV-A T1OFINT_ISR, // EV-A rsvd_ISR,

// Group 3 PIE Vectors

T2PINT_ISR, // EV-A T2CINT_ISR, // EV-A T2UFINT_ISR, // EV-A T2OFINT_ISR, // EV-A CAPINT1_ISR, // EV-A CAPINT2_ISR, // EV-A CAPINT3_ISR, // EV-A rsvd_ISR,

// Group 4 PIE Vectors

CMP4INT_ISR, // EV-B CMP5INT_ISR, // EV-B CMP6INT_ISR, // EV-B T3PINT_ISR, // EV-B T3CINT_ISR, // EV-B T3UFINT_ISR, // EV-B T3OFINT_ISR, // EV-B rsvd_ISR,

// Group 5 PIE Vectors

T4PINT_ISR, // EV-B T4CINT_ISR, // EV-B T4UFINT_ISR, // EV-B T4OFINT_ISR, // EV-B CAPINT4_ISR, // EV-B CAPINT5_ISR, // EV-B CAPINT6_ISR, // EV-B rsvd_ISR,

// Group 6 PIE Vectors

SPIRXINTA_ISR, // SPI-A SPITXINTA_ISR, // SPI-A rsvd_ISR, rsvd_ISR,

MRINTA_ISR, // McBSP-A MXINTA_ISR, // McBSP-A rsvd_ISR, rsvd_ISR,

// Group 7 PIE Vectors rsvd_ISR, rsvd_ISR,

rsvd_ISR, rsvd_ISR, rsvd_ISR, rsvd_ISR, rsvd_ISR, rsvd_ISR,

// Group 8 PIE Vectors rsvd_ISR, rsvd_ISR, rsvd_ISR, rsvd_ISR, rsvd_ISR, rsvd_ISR, rsvd_ISR, rsvd_ISR,

// Group 9 PIE Vectors

SCIRXINTA_ISR, // SCI-A SCITXINTA_ISR, // SCI-A SCIRXINTB_ISR, // SCI-B SCITXINTB_ISR, // SCI-B ECAN0INTA_ISR, // eCAN ECAN1INTA_ISR, // eCAN rsvd_ISR, rsvd_ISR,

// Group 10 PIE Vectors rsvd_ISR, rsvd_ISR, rsvd_ISR, rsvd_ISR, rsvd_ISR, rsvd_ISR, rsvd_ISR, rsvd_ISR,

// Group 11 PIE Vectors rsvd_ISR, rsvd_ISR, rsvd_ISR, rsvd_ISR, rsvd_ISR, rsvd_ISR,

rsvd_ISR, rsvd_ISR,

// Group 12 PIE Vectors rsvd_ISR, rsvd_ISR, rsvd_ISR, rsvd_ISR, rsvd_ISR, rsvd_ISR, rsvd_ISR, rsvd_ISR, };

/*------------------------------------------*/

/*形式参数：void */ /*返回值:void */

/*函数描述:初始化PIE向量表 */ /*------------------------------------------*/ void InitPieVectTable(void) { int16 i; Uint32 *Source = (void *) &PieVectTableInit; Uint32 *Dest = (void *) &PieVectTable; EALLOW; for(i=0; i < 128; i++) *Dest++ = *Source++; EDIS; // 使能中断向量表 PieCtrlRegs.PIECRTL.bit.ENPIE = 1; }

// TI File $Revision: /main/5 $

// Checkin $Date: December 17, 2007 13:36:09 $

//########################################################################### //

// FILE: DSP281x_Device.h //

// TITLE: DSP281x Device Definitions. //

//########################################################################### // $TI Release: DSP281x C/C++ Header Files V1.20 $ // $Release Date: July 27, 2009 $

//###########################################################################

#ifndef DSP281x_DEVICE_H #define DSP281x_DEVICE_H

#ifdef __cplusplus extern \#endif

#define TARGET 1

//--------------------------------------------------------------------------- // User To Select Target Device:

#define DSP28_F2812 TARGET #define DSP28_F2811 0 #define DSP28_F2810 0

//--------------------------------------------------------------------------- // Common CPU Definitions: //

extern cregister volatile unsigned int IFR; extern cregister volatile unsigned int IER;

#define EINT asm(\#define DINT asm(\#define ERTM asm(\#define DRTM asm(\#define EALLOW asm(\#define EDIS asm(\#define ESTOP0 asm(\

#define M_INT1 0x0001 #define M_INT2 0x0002 #define M_INT3 0x0004 #define M_INT4 0x0008 #define M_INT5 0x0010 #define M_INT6 0x0020 #define M_INT7 0x0040

#define M_INT8 0x0080 #define M_INT9 0x0100 #define M_INT10 0x0200 #define M_INT11 0x0400 #define M_INT12 0x0800 #define M_INT13 0x1000 #define M_INT14 0x2000 #define M_DLOG 0x4000 #define M_RTOS 0x8000

#define BIT0 0x0001 #define BIT1 0x0002 #define BIT2 0x0004 #define BIT3 0x0008 #define BIT4 0x0010 #define BIT5 0x0020 #define BIT6 0x0040 #define BIT7 0x0080 #define BIT8 0x0100 #define BIT9 0x0200 #define BIT10 0x0400 #define BIT11 0x0800 #define BIT12 0x1000 #define BIT13 0x2000 #define BIT14 0x4000 #define BIT15 0x8000

//---------------------------------------------------------------------------

// For Portability, User Is Recommended To Use Following Data Type Size // Definitions For 16-bit and 32-Bit Signed/Unsigned Integers: //

#ifndef DSP28_DATA_TYPES #define DSP28_DATA_TYPES

typedef int int16; typedef long int32; typedef long long int64; typedef unsigned int Uint16; typedef unsigned long Uint32; typedef unsigned long long Uint64; typedef float float32; typedef long double float64;

#endif

//--------------------------------------------------------------------------- // Include All Peripheral Header Files: //

#include \ // System Control/Power Modes #include \ // Device Emulation Registers #include \ // External Interface Registers #include \ // 32-bit CPU Timers #include \ // PIE Control Registers #include \ect.h\ // PIE Vector Table #include \ // SPI Registers #include \ // SCI Registers #include \ // McBSP Registers

#include \ // Enhanced eCAN Registers #include \ // General Purpose I/O Registers #include \ // Event Manager Registers #include \ // ADC Registers #include \ // External Interrupts

#ifdef __cplusplus }

#endif /* extern \

#endif // end of DSP281x_DEVICE_H definition

//=========================================================================== // No more.

//===========================================================================

// TI File $Revision: /main/2 $

// Checkin $Date: April 28, 2005 14:57:26 $

//########################################################################### //

// FILE: DSP281x_Gpio.h //

// TITLE: DSP281x General Purpose I/O Definitions. //

//########################################################################### // $TI Release: DSP281x C/C++ Header Files V1.20 $

// $Release Date: July 27, 2009 $

//###########################################################################

#ifndef DSP281x_GPIO_H #define DSP281x_GPIO_H

#ifdef __cplusplus extern \#endif

//----------------------------------------------------

// General purpose I/O (GPIO) Register Bit Definitions

//----------------------------------------------------

// GPIO A mux control register bit definitions */ // //

struct GPAMUX_BITS { // bits description Uint16 PWM1_GPIOA0:1; // 0 Uint16 PWM2_GPIOA1:1; // 1 Uint16 PWM3_GPIOA2:1; // 2 Uint16 PWM4_GPIOA3:1; // 3 Uint16 PWM5_GPIOA4:1; // 4 Uint16 PWM6_GPIOA5:1; // 5 Uint16 T1PWM_GPIOA6:1; // 6

Uint16 T2PWM_GPIOA7:1; // 7 Uint16 CAP1Q1_GPIOA8:1; // 8 Uint16 CAP2Q2_GPIOA9:1; // 9 Uint16 CAP3QI1_GPIOA10:1; // 10 Uint16 TDIRA_GPIOA11:1; // 11 Uint16 TCLKINA_GPIOA12:1; // 12 Uint16 C1TRIP_GPIOA13:1; // 13 Uint16 C2TRIP_GPIOA14:1; // 14 Uint16 C3TRIP_GPIOA15:1; // 15 };

union GPAMUX_REG {

Uint16 all; struct GPAMUX_BITS bit; };

//---------------------------------------------------------------------------------------

// GPIO A Direction control register bit definitions // //

struct GPADIR_BITS { // bits description Uint16 GPIOA0:1; // 0 Uint16 GPIOA1:1; // 1 Uint16 GPIOA2:1; // 2 Uint16 GPIOA3:1; // 3 Uint16 GPIOA4:1; // 4 Uint16 GPIOA5:1; // 5 Uint16 GPIOA6:1; // 6

Uint16 GPIOA7:1; // 7 Uint16 GPIOA8:1; // 8 Uint16 GPIOA9:1; // 9 Uint16 GPIOA10:1; // 10 Uint16 GPIOA11:1; // 11 Uint16 GPIOA12:1; // 12 Uint16 GPIOA13:1; // 13 Uint16 GPIOA14:1; // 14 Uint16 GPIOA15:1; // 15 };

union GPADIR_REG {

Uint16 all; struct GPADIR_BITS bit; };

//---------------------------------- // GPA Qualregister bit definitions // //

struct GPAQUAL_BITS { // bits description

Uint16 QUALPRD:8; // 0:7 Qualification Sampling Period Uint16 rsvd1:8; // 15:8 reserved };

union GPAQUAL_REG {

Uint16 all; struct GPAQUAL_BITS bit;

};

//---------------------------------------------------------------------------------------

// GPIO A Data register bit definitions // //

struct GPADAT_BITS { // bits description Uint16 GPIOA0:1; // 0 Uint16 GPIOA1:1; // 1 Uint16 GPIOA2:1; // 2 Uint16 GPIOA3:1; // 3 Uint16 GPIOA4:1; // 4 Uint16 GPIOA5:1; // 5 Uint16 GPIOA6:1; // 6

Uint16 GPIOA7:1; // 7 Uint16 GPIOA8:1; // 8 Uint16 GPIOA9:1; // 9 Uint16 GPIOA10:1; // 10 Uint16 GPIOA11:1; // 11 Uint16 GPIOA12:1; // 12 Uint16 GPIOA13:1; // 13 Uint16 GPIOA14:1; // 14 Uint16 GPIOA15:1; // 15 };

union GPADAT_REG {

Uint16 all; struct GPADAT_BITS bit; };

//--------------------------------------------------------------------------------------- // GPIO A Data set bit definitions // //

struct GPASET_BITS { // bits description Uint16 GPIOA0:1; // 0 Uint16 GPIOA1:1; // 1 Uint16 GPIOA2:1; // 2 Uint16 GPIOA3:1; // 3 Uint16 GPIOA4:1; // 4 Uint16 GPIOA5:1; // 5

Uint16 GPIOA6:1; // 6

Uint16 GPIOA7:1; // 7 Uint16 GPIOA8:1; // 8 Uint16 GPIOA9:1; // 9 Uint16 GPIOA10:1; // 10 Uint16 GPIOA11:1; // 11 Uint16 GPIOA12:1; // 12 Uint16 GPIOA13:1; // 13 Uint16 GPIOA14:1; // 14 Uint16 GPIOA15:1; // 15 };

union GPASET_REG {

Uint16 all; struct GPASET_BITS bit; };

//---------------------------------------------------------------------------------------

// GPIO A Data clear register bit definitions // //

struct GPACLEAR_BITS { // bits description Uint16 GPIOA0:1; // 0 Uint16 GPIOA1:1; // 1 Uint16 GPIOA2:1; // 2 Uint16 GPIOA3:1; // 3 Uint16 GPIOA4:1; // 4 Uint16 GPIOA5:1; // 5 Uint16 GPIOA6:1; // 6

Uint16 GPIOA7:1; // 7 Uint16 GPIOA8:1; // 8 Uint16 GPIOA9:1; // 9 Uint16 GPIOA10:1; // 10 Uint16 GPIOA11:1; // 11 Uint16 GPIOA12:1; // 12 Uint16 GPIOA13:1; // 13 Uint16 GPIOA14:1; // 14 Uint16 GPIOA15:1; // 15 };

union GPACLEAR_REG {

Uint16 all; struct GPACLEAR_BITS bit; };

//---------------------------------------------------------------------------------------

// GPIO A Data toggle register bit definitions // //

struct GPATOGGLE_BITS { // bits description Uint16 GPIOA0:1; // 0 Uint16 GPIOA1:1; // 1 Uint16 GPIOA2:1; // 2 Uint16 GPIOA3:1; // 3 Uint16 GPIOA4:1; // 4 Uint16 GPIOA5:1; // 5 Uint16 GPIOA6:1; // 6

Uint16 GPIOA7:1; // 7 Uint16 GPIOA8:1; // 8 Uint16 GPIOA9:1; // 9 Uint16 GPIOA10:1; // 10 Uint16 GPIOA11:1; // 11 Uint16 GPIOA12:1; // 12 Uint16 GPIOA13:1; // 13 Uint16 GPIOA14:1; // 14 Uint16 GPIOA15:1; // 15 };

union GPATOGGLE_REG {

Uint16 all; struct GPATOGGLE_BITS bit; };

//---------------------------------------------------------------------------------

// GPIO B mux control register bit definitions // //

struct GPBMUX_BITS { // bits description Uint16 PWM7_GPIOB0:1; // 0 Uint16 PWM8_GPIOB1:1; // 1 Uint16 PWM9_GPIOB2:1; // 2

Uint16 PWM10_GPIOB3:1; // 3 Uint16 PWM11_GPIOB4:1; // 4 Uint16 PWM12_GPIOB5:1; // 5 Uint16 T3PWM_GPIOB6:1; // 6

Uint16 T4PWM_GPIOB7:1; // 7 Uint16 CAP4Q1_GPIOB8:1; // 8 Uint16 CAP5Q2_GPIOB9:1; // 9 Uint16 CAP6QI2_GPIOB10:1; // 10 Uint16 TDIRB_GPIOB11:1; // 11 Uint16 TCLKINB_GPIOB12:1; // 12 Uint16 C4TRIP_GPIOB13:1; // 13 Uint16 C5TRIP_GPIOB14:1; // 14 Uint16 C6TRIP_GPIOB15:1; // 15 };

union GPBMUX_REG {

Uint16 all; struct GPBMUX_BITS bit; };

//---------------------------------------------------------------------------------------

// GPIO B Direction control register bit definitions // //

struct GPBDIR_BITS { // bits description Uint16 GPIOB0:1; // 0 Uint16 GPIOB1:1; // 1 Uint16 GPIOB2:1; // 2 Uint16 GPIOB3:1; // 3 Uint16 GPIOB4:1; // 4 Uint16 GPIOB5:1; // 5 Uint16 GPIOB6:1; // 6

Uint16 GPIOB7:1; // 7 Uint16 GPIOB8:1; // 8 Uint16 GPIOB9:1; // 9 Uint16 GPIOB10:1; // 10 Uint16 GPIOB11:1; // 11 Uint16 GPIOB12:1; // 12 Uint16 GPIOB13:1; // 13 Uint16 GPIOB14:1; // 14 Uint16 GPIOB15:1; // 15 };

union GPBDIR_REG {

Uint16 all; struct GPBDIR_BITS bit; };

//-----------------------------------

// GPB Qualregister bit definitions // //

struct GPBQUAL_BITS { // bits description

Uint16 QUALPRD:8; // 0:7 Qualification Sampling Period Uint16 rsvd1:8; // 15:8 reserved };

union GPBQUAL_REG {

Uint16 all; struct GPBQUAL_BITS bit; };

//---------------------------------------------------------------------------------------

// GPIO B data register bit definitions // //

struct GPBDAT_BITS { // bits description Uint16 GPIOB0:1; // 0 Uint16 GPIOB1:1; // 1 Uint16 GPIOB2:1; // 2 Uint16 GPIOB3:1; // 3 Uint16 GPIOB4:1; // 4 Uint16 GPIOB5:1; // 5 Uint16 GPIOB6:1; // 6

Uint16 GPIOB7:1; // 7 Uint16 GPIOB8:1; // 8 Uint16 GPIOB9:1; // 9 Uint16 GPIOB10:1; // 10 Uint16 GPIOB11:1; // 11 Uint16 GPIOB12:1; // 12 Uint16 GPIOB13:1; // 13 Uint16 GPIOB14:1; // 14 Uint16 GPIOB15:1; // 15

};

union GPBDAT_REG {

Uint16 all; struct GPBDAT_BITS bit; };

//---------------------------------------------------------------------------------------

// GPIO B data set register bit definitions // //

struct GPBSET_BITS { // bits description Uint16 GPIOB0:1; // 0 Uint16 GPIOB1:1; // 1 Uint16 GPIOB2:1; // 2 Uint16 GPIOB3:1; // 3 Uint16 GPIOB4:1; // 4 Uint16 GPIOB5:1; // 5 Uint16 GPIOB6:1; // 6

Uint16 GPIOB7:1; // 7 Uint16 GPIOB8:1; // 8 Uint16 GPIOB9:1; // 9 Uint16 GPIOB10:1; // 10 Uint16 GPIOB11:1; // 11 Uint16 GPIOB12:1; // 12 Uint16 GPIOB13:1; // 13 Uint16 GPIOB14:1; // 14 Uint16 GPIOB15:1; // 15 };

union GPBSET_REG {

Uint16 all; struct GPBSET_BITS bit; };

//---------------------------------------------------------------------------------------

// GPIO B data clear register bit definitions // //

struct GPBCLEAR_BITS { // bits description Uint16 GPIOB0:1; // 0 Uint16 GPIOB1:1; // 1 Uint16 GPIOB2:1; // 2 Uint16 GPIOB3:1; // 3 Uint16 GPIOB4:1; // 4 Uint16 GPIOB5:1; // 5 Uint16 GPIOB6:1; // 6

Uint16 GPIOB7:1; // 7 Uint16 GPIOB8:1; // 8 Uint16 GPIOB9:1; // 9 Uint16 GPIOB10:1; // 10 Uint16 GPIOB11:1; // 11 Uint16 GPIOB12:1; // 12 Uint16 GPIOB13:1; // 13 Uint16 GPIOB14:1; // 14 Uint16 GPIOB15:1; // 15 };

union GPBCLEAR_REG {

Uint16 all; struct GPBCLEAR_BITS bit; };

//---------------------------------------------------------------------------------------

// GPIO B data toggle register bit definitions // //

struct GPBTOGGLE_BITS { // bits description Uint16 GPIOB0:1; // 0 Uint16 GPIOB1:1; // 1 Uint16 GPIOB2:1; // 2 Uint16 GPIOB3:1; // 3 Uint16 GPIOB4:1; // 4 Uint16 GPIOB5:1; // 5 Uint16 GPIOB6:1; // 6

Uint16 GPIOB7:1; // 7 Uint16 GPIOB8:1; // 8 Uint16 GPIOB9:1; // 9 Uint16 GPIOB10:1; // 10 Uint16 GPIOB11:1; // 11

Uint16 GPIOB12:1; // 12 Uint16 GPIOB13:1; // 13 Uint16 GPIOB14:1; // 14 Uint16 GPIOB15:1; // 15 };

union GPBTOGGLE_REG { Uint16 all; struct GPBTOGGLE_BITS bit; };

//---------------------------------------------------------------------------------

// GPIO D mux control register bit definitions // //

struct GPDMUX_BITS { // bits description Uint16 T1CTRIP_PDPA_GPIOD0:1; // 0 Uint16 T2CTRIP_SOCA_GPIOD1:1; // 1 Uint16 rsvd1:3; // 4:2 Uint16 T3CTRIP_PDPB_GPIOD5:1; // 5 Uint16 T4CTRIP_SOCB_GPIOD6:1; // 6 Uint16 rsvd2:9; // 15:7 };

union GPDMUX_REG { Uint16 all; struct GPDMUX_BITS bit; };

//----------------------------------------------------

// GPIO D Direction control register bit definitions // //

struct GPDDIR_BITS { // bits description Uint16 GPIOD0:1; // 0 Uint16 GPIOD1:1; // 1 Uint16 rsvd1:3; // 4:2 Uint16 GPIOD5:1; // 5 Uint16 GPIOD6:1; // 6 Uint16 rsvd2:9; // 15:7 };

union GPDDIR_REG {

Uint16 all; struct GPDDIR_BITS bit; };

//---------------------------------------------------- // GPIO D data register bit definitions

// //

struct GPDDAT_BITS { // bits description Uint16 GPIOD0:1; // 0 Uint16 GPIOD1:1; // 1 Uint16 rsvd1:3; // 4:2 Uint16 GPIOD5:1; // 5 Uint16 GPIOD6:1; // 6 Uint16 rsvd2:9; // 15:7 };

union GPDDAT_REG {

Uint16 all; struct GPDDAT_BITS bit; };

//---------------------------------------------------- // GPIO D data set register bit definitions

// //

struct GPDSET_BITS { // bits description Uint16 GPIOD0:1; // 0 Uint16 GPIOD1:1; // 1 Uint16 rsvd1:3; // 4:2 Uint16 GPIOD5:1; // 5 Uint16 GPIOD6:1; // 6 Uint16 rsvd2:9; // 15:7 };

union GPDSET_REG {

Uint16 all; struct GPDSET_BITS bit; };

//---------------------------------------------------- // GPIO D data clear register bit definitions // //

struct GPDCLEAR_BITS { // bits description Uint16 GPIOD0:1; // 0 Uint16 GPIOD1:1; // 1 Uint16 rsvd1:3; // 4:2 Uint16 GPIOD5:1; // 5 Uint16 GPIOD6:1; // 6 Uint16 rsvd2:9; // 15:7 };

union GPDCLEAR_REG {

Uint16 all; struct GPDCLEAR_BITS bit; };

//---------------------------------------------------- // GPIO D data toggle register bit definitions // //

struct GPDTOGGLE_BITS { // bits Uint16 GPIOD0:1; // 0 Uint16 GPIOD1:1; // 1 Uint16 rsvd1:3; // 4:2 Uint16 GPIOD5:1; // 5 Uint16 GPIOD6:1; // 6 Uint16 rsvd2:9; // 15:7 };

union GPDTOGGLE_REG { Uint16 all; struct GPDTOGGLE_BITS bit; };

//----------------------------------

// GPIOD Qualregister bit definitions //

description //

struct GPDQUAL_BITS { // bits description

Uint16 QUALPRD:8; // 0:7 Qualification Sampling Period Uint16 rsvd1:8; // 15:8 reserved };

union GPDQUAL_REG {

Uint16 all; struct GPDQUAL_BITS bit; };

//---------------------------------------------

// GPIO E mux control register bit definitions // //

struct GPEMUX_BITS { // bits description Uint16 XINT1_XBIO_GPIOE0:1; // 0 Uint16 XINT2_ADCSOC_GPIOE1:1; // 1 Uint16 XNMI_XINT13_GPIOE2:1; // 2 Uint16 rsvd1:12; // 15:3 };

union GPEMUX_REG {

Uint16 all; struct GPEMUX_BITS bit; };

//---------------------------------------------------

// GPIO E Direction control register bit definitions // //

struct GPEDIR_BITS { // bits description Uint16 GPIOE0:1; // 0 Uint16 GPIOE1:1; // 1 Uint16 GPIOE2:1; // 2

Uint16 rsvd1:12; // 15:3 };

union GPEDIR_REG {

Uint16 all; struct GPEDIR_BITS bit; };

//--------------------------------------------------- // GPIO E data register bit definitions

// //

struct GPEDAT_BITS { // bits description Uint16 GPIOE0:1; // 0 Uint16 GPIOE1:1; // 1 Uint16 GPIOE2:1; // 2

Uint16 rsvd1:12; // 15:3 };

union GPEDAT_REG {

Uint16 all; struct GPEDAT_BITS bit; };

//--------------------------------------------------- // GPIO E data set register bit definitions

// //

struct GPESET_BITS { // bits description Uint16 GPIOE0:1; // 0 Uint16 GPIOE1:1; // 1 Uint16 GPIOE2:1; // 2

Uint16 rsvd1:12; // 15:3 };

union GPESET_REG {

Uint16 all; struct GPESET_BITS bit; };

//--------------------------------------------------- // GPIO E data clear register bit definitions // //

struct GPECLEAR_BITS { // bits description Uint16 GPIOE0:1; // 0 Uint16 GPIOE1:1; // 1 Uint16 GPIOE2:1; // 2

Uint16 rsvd1:12; // 15:3 };

union GPECLEAR_REG {

Uint16 all; struct GPECLEAR_BITS bit; };

//--------------------------------------------------- // GPIO E data toggle register bit definitions // //

struct GPETOGGLE_BITS { // bits description Uint16 GPIOE0:1; // 0 Uint16 GPIOE1:1; // 1 Uint16 GPIOE2:1; // 2

Uint16 rsvd1:12; // 15:3 };

union GPETOGGLE_REG { Uint16 all; struct GPETOGGLE_BITS bit; };

//-----------------------------------

// GPIOE Qualregister bit definitions // //

struct GPEQUAL_BITS { // bits description

Uint16 QUALPRD:8; // 0:7 Qualification Sampling Period Uint16 rsvd1:8; // 15:8 reserved };

union GPEQUAL_REG {

Uint16 all; struct GPEQUAL_BITS bit; };

//----------------------------------------------

// GPIO F mux control register bit definitions

// //

struct GPFMUX_BITS { // bits description Uint16 SPISIMOA_GPIOF0:1; // 0 Uint16 SPISOMIA_GPIOF1:1; // 1 Uint16 SPICLKA_GPIOF2:1; // 2 Uint16 SPISTEA_GPIOF3:1; // 3 Uint16 SCITXDA_GPIOF4:1; // 4 Uint16 SCIRXDA_GPIOF5:1; // 5 Uint16 CANTXA_GPIOF6:1; // 6 Uint16 CANRXA_GPIOF7:1; // 7 Uint16 MCLKXA_GPIOF8:1; // 8 Uint16 MCLKRA_GPIOF9:1; // 9 Uint16 MFSXA_GPIOF10:1; // 10 Uint16 MFSRA_GPIOF11:1; // 11 Uint16 MDXA_GPIOF12:1; // 12 Uint16 MDRA_GPIOF13:1; // 13 Uint16 XF_GPIOF14:1; // 14 Uint16 spare_GPIOF15:1; // 15 };

/* Allow access to the bit fields or entire register */ union GPFMUX_REG {

Uint16 all; struct GPFMUX_BITS bit; };

//---------------------------------------------------

// GPIO F Direction control register bit definitions // //

struct GPFDIR_BITS { // bits description Uint16 GPIOF0:1; // 0 Uint16 GPIOF1:1; // 1 Uint16 GPIOF2:1; // 2 Uint16 GPIOF3:1; // 3 Uint16 GPIOF4:1; // 4 Uint16 GPIOF5:1; // 5 Uint16 GPIOF6:1; // 6 Uint16 GPIOF7:1; // 7 Uint16 GPIOF8:1; // 8 Uint16 GPIOF9:1; // 9

Uint16 GPIOF10:1; // 10 Uint16 GPIOF11:1; // 11 Uint16 GPIOF12:1; // 12 Uint16 GPIOF13:1; // 13 Uint16 GPIOF14:1; // 14 Uint16 GPIOF15:1; // 15 };

union GPFDIR_REG {

Uint16 all; struct GPFDIR_BITS bit; };

//--------------------------------------------------- // GPIO F data register bit definitions

// //

struct GPFDAT_BITS { // bits description Uint16 GPIOF0:1; // 0 Uint16 GPIOF1:1; // 1 Uint16 GPIOF2:1; // 2 Uint16 GPIOF3:1; // 3 Uint16 GPIOF4:1; // 4 Uint16 GPIOF5:1; // 5 Uint16 GPIOF6:1; // 6 Uint16 GPIOF7:1; // 7 Uint16 GPIOF8:1; // 8 Uint16 GPIOF9:1; // 9 Uint16 GPIOF10:1; // 10 Uint16 GPIOF11:1; // 11 Uint16 GPIOF12:1; // 12 Uint16 GPIOF13:1; // 13 Uint16 GPIOF14:1; // 14 Uint16 GPIOF15:1; // 15 };

union GPFDAT_REG {

Uint16 all; struct GPFDAT_BITS bit; };

//--------------------------------------------------- // GPIO F data set register bit definitions

// //

struct GPFSET_BITS { // bits description Uint16 GPIOF0:1; // 0 Uint16 GPIOF1:1; // 1 Uint16 GPIOF2:1; // 2 Uint16 GPIOF3:1; // 3 Uint16 GPIOF4:1; // 4 Uint16 GPIOF5:1; // 5 Uint16 GPIOF6:1; // 6 Uint16 GPIOF7:1; // 7 Uint16 GPIOF8:1; // 8 Uint16 GPIOF9:1; // 9 Uint16 GPIOF10:1; // 10 Uint16 GPIOF11:1; // 11 Uint16 GPIOF12:1; // 12 Uint16 GPIOF13:1; // 13 Uint16 GPIOF14:1; // 14 Uint16 GPIOF15:1; // 15 };

union GPFSET_REG {

Uint16 all; struct GPFSET_BITS bit; };

//--------------------------------------------------- // GPIO F data clear register bit definitions // //

struct GPFCLEAR_BITS { // bits description Uint16 GPIOF0:1; // 0 Uint16 GPIOF1:1; // 1 Uint16 GPIOF2:1; // 2 Uint16 GPIOF3:1; // 3 Uint16 GPIOF4:1; // 4 Uint16 GPIOF5:1; // 5

Uint16 GPIOF6:1; // 6 Uint16 GPIOF7:1; // 7 Uint16 GPIOF8:1; // 8 Uint16 GPIOF9:1; // 9 Uint16 GPIOF10:1; // 10 Uint16 GPIOF11:1; // 11 Uint16 GPIOF12:1; // 12 Uint16 GPIOF13:1; // 13 Uint16 GPIOF14:1; // 14 Uint16 GPIOF15:1; // 15 };

union GPFCLEAR_REG {

Uint16 all; struct GPFCLEAR_BITS bit; };

//--------------------------------------------------- // GPIO F data toggle register bit definitions // //

struct GPFTOGGLE_BITS { // bits description Uint16 GPIOF0:1; // 0 Uint16 GPIOF1:1; // 1 Uint16 GPIOF2:1; // 2 Uint16 GPIOF3:1; // 3 Uint16 GPIOF4:1; // 4 Uint16 GPIOF5:1; // 5 Uint16 GPIOF6:1; // 6 Uint16 GPIOF7:1; // 7 Uint16 GPIOF8:1; // 8 Uint16 GPIOF9:1; // 9 Uint16 GPIOF10:1; // 10 Uint16 GPIOF11:1; // 11 Uint16 GPIOF12:1; // 12 Uint16 GPIOF13:1; // 13 Uint16 GPIOF14:1; // 14 Uint16 GPIOF15:1; // 15 };

union GPFTOGGLE_REG { Uint16 all; struct GPFTOGGLE_BITS bit; };

//----------------------------------------------

// GPIO G mux control register bit definitions // //

struct GPGMUX_BITS { // bits description Uint16 rsvd1:4; // 3:0 Uint16 SCITXDB_GPIOG4:1; // 4 Uint16 SCIRXDB_GPIOG5:1; // 5 Uint16 rsvd2:10; // 15:6 };

/* Allow access to the bit fields or entire register */ union GPGMUX_REG { Uint16 all; struct GPGMUX_BITS bit; };

//---------------------------------------------------

// GPIO G Direction control register bit definitions // //

struct GPGDIR_BITS { // bits description Uint16 rsvd1:4; // 3:0 Uint16 GPIOG4:1; // 4 Uint16 GPIOG5:1; // 5 Uint16 rsvd2:10; // 15:6 };

union GPGDIR_REG {

Uint16 all; struct GPGDIR_BITS bit; };

//--------------------------------------------------- // GPIO G data register bit definitions

// //

struct GPGDAT_BITS { // bits description Uint16 rsvd1:4; // 3:0 Uint16 GPIOG4:1; // 4 Uint16 GPIOG5:1; // 5 Uint16 rsvd2:10; // 15:6 };

union GPGDAT_REG {

Uint16 all; struct GPGDAT_BITS bit; };

//--------------------------------------------------- // GPIO G data set register bit definitions

// //

struct GPGSET_BITS { // bits description Uint16 rsvd1:4; // 3:0 Uint16 GPIOG4:1; // 4 Uint16 GPIOG5:1; // 5 Uint16 rsvd2:10; // 15:6 };

union GPGSET_REG {

Uint16 all; struct GPGSET_BITS bit; };

//--------------------------------------------------- // GPIO G data clear register bit definitions // //

struct GPGCLEAR_BITS { // bits description Uint16 rsvd1:4; // 3:0 Uint16 GPIOG4:1; // 4

Uint16 GPIOG5:1; // 5 Uint16 rsvd2:10; // 15:6 };

union GPGCLEAR_REG {

Uint16 all; struct GPGCLEAR_BITS bit; };

//--------------------------------------------------- // GPIO G data toggle register bit definitions // //

struct GPGTOGGLE_BITS { // bits description Uint16 rsvd1:4; // 3:0 Uint16 GPIOG4:1; // 4 Uint16 GPIOG5:1; // 5 Uint16 rsvd2:10; // 15:6 };

union GPGTOGGLE_REG { Uint16 all; struct GPGTOGGLE_BITS bit; };

struct GPIO_MUX_REGS {

union GPAMUX_REG GPAMUX; union GPADIR_REG GPADIR; union GPAQUAL_REG GPAQUAL; Uint16 rsvd1;

union GPBMUX_REG GPBMUX; union GPBDIR_REG GPBDIR;

union GPBQUAL_REG GPBQUAL; Uint16 rsvd2[5];

union GPDMUX_REG GPDMUX; union GPDDIR_REG GPDDIR;

union GPDQUAL_REG GPDQUAL; Uint16 rsvd3;

union GPEMUX_REG GPEMUX;

union GPEDIR_REG GPEDIR;

union GPEQUAL_REG GPEQUAL; Uint16 rsvd4;

union GPFMUX_REG GPFMUX; union GPFDIR_REG GPFDIR; Uint16 rsvd5[2];

union GPGMUX_REG GPGMUX; union GPGDIR_REG GPGDIR; Uint16 rsvd6[6]; };

struct GPIO_DATA_REGS {

union GPADAT_REG GPADAT; union GPASET_REG GPASET;

union GPACLEAR_REG GPACLEAR; union GPATOGGLE_REG GPATOGGLE; union GPBDAT_REG GPBDAT; union GPBSET_REG GPBSET;

union GPBCLEAR_REG GPBCLEAR; union GPBTOGGLE_REG GPBTOGGLE; Uint16 rsvd1[4]; union GPDDAT_REG GPDDAT; union GPDSET_REG GPDSET;

union GPDCLEAR_REG GPDCLEAR; union GPDTOGGLE_REG GPDTOGGLE; union GPEDAT_REG GPEDAT; union GPESET_REG GPESET;

union GPECLEAR_REG GPECLEAR; union GPETOGGLE_REG GPETOGGLE; union GPFDAT_REG GPFDAT; union GPFSET_REG GPFSET;

union GPFCLEAR_REG GPFCLEAR; union GPFTOGGLE_REG GPFTOGGLE; union GPGDAT_REG GPGDAT; union GPGSET_REG GPGSET;

union GPGCLEAR_REG GPGCLEAR; union GPGTOGGLE_REG GPGTOGGLE; Uint16 rsvd2[4]; };

//--------------------------------------------------------------------------- // GPI/O External References & Function Declarations: //

extern volatile struct GPIO_MUX_REGS GpioMuxRegs; extern volatile struct GPIO_DATA_REGS GpioDataRegs;

#ifdef __cplusplus }

#endif /* extern \

#endif // end of DSP281x_GPIO_H definition

//=========================================================================== // No more.

//===========================================================================

/******************************************************************/ /*Copyright (C), 2008-2009, 力天电子，LiTian Tech.Co.Ltd. */ /* Module Name : system */ /* File Name : DSP281x_DefaultIsr.c */ /* Author : 侯长波 */ /* Create Date : 2009/12/1 */

/* Version : 2.0 */

/* Function : system */ /* Description : DSP281x默认中断函数定义 */ /* Support : www.LT430.com */ /******************************************************************/ #include \

// Note CPU-Timer1 ISR is reserved for TI use.

interrupt void INT13_ISR(void) // INT13 or CPU-Timer1 {

// Insert ISR Code here

// Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (\ ESTOP0\ for(;;); }

// Note CPU-Timer2 ISR is reserved for TI use.

interrupt void INT14_ISR(void) // CPU-Timer2 {

// Insert ISR Code here

// Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (\ ESTOP0\ for(;;); }

interrupt void DATALOG_ISR(void) // Datalogging interrupt {

// Insert ISR Code here

// Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (\ ESTOP0\ for(;;); }

interrupt void RTOSINT_ISR(void) // RTOS interrupt {

// Insert ISR Code here

// Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (\ ESTOP0\ for(;;); }

interrupt void EMUINT_ISR(void) // Emulation interrupt {

// Insert ISR Code here

// Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (\ ESTOP0\ for(;;); }

interrupt void NMI_ISR(void) // Non-maskable interrupt {

// Insert ISR Code here

// Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (\ ESTOP0\

for(;;); }

interrupt void ILLEGAL_ISR(void) // Illegal operation TRAP {

// Insert ISR Code here

// Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm(\ ESTOP0\ for(;;); }

interrupt void USER1_ISR(void) // User Defined trap 1 {

// Insert ISR Code here

// Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (\ ESTOP0\ for(;;); }

interrupt void USER2_ISR(void) // User Defined trap 2 {

// Insert ISR Code here

// Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (\ ESTOP0\ for(;;); }

interrupt void USER3_ISR(void) // User Defined trap 3 {

// Insert ISR Code here

// Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (\ ESTOP0\

for(;;); }

interrupt void USER4_ISR(void) // User Defined trap 4 {

// Insert ISR Code here

// Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (\ ESTOP0\ for(;;); }

interrupt void USER5_ISR(void) // User Defined trap 5 {

// Insert ISR Code here

// Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (\ ESTOP0\ for(;;); }

interrupt void USER6_ISR(void) // User Defined trap 6 {

// Insert ISR Code here

// Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (\ ESTOP0\ for(;;); }

interrupt void USER7_ISR(void) // User Defined trap 7 {

// Insert ISR Code here

// Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (\ ESTOP0\ for(;;); }

interrupt void USER8_ISR(void) // User Defined trap 8

{

// Insert ISR Code here

// Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (\ ESTOP0\ for(;;); }

interrupt void USER9_ISR(void) // User Defined trap 9 {

// Insert ISR Code here

// Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (\ ESTOP0\ for(;;); }

interrupt void USER10_ISR(void) // User Defined trap 10 {

// Insert ISR Code here

// Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (\ ESTOP0\ for(;;); }

interrupt void USER11_ISR(void) // User Defined trap 11 {

// Insert ISR Code here

// Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (\ ESTOP0\ for(;;); }

interrupt void USER12_ISR(void) // User Defined trap 12 {

// Insert ISR Code here

// Next two lines for debug only to halt the processor here

// Remove after inserting ISR Code asm (\ ESTOP0\ for(;;); }

// ----------------------------------------------------------- // PIE Group 1 - MUXed into CPU INT1

// -----------------------------------------------------------

// INT1.1

interrupt void PDPINTA_ISR( void ) // EV-A {

// Insert ISR Code here

// To receive more interrupts from this PIE group, acknowledge this interrupt // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;

// Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (\ ESTOP0\ for(;;); }

// INT1.2

interrupt void PDPINTB_ISR(void) // EV-B {

// Insert ISR Code here

// To receive more interrupts from this PIE group, acknowledge this interrupt // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;

// Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (\ ESTOP0\ for(;;); }

// INT1.3 - Reserved

// INT1.4

interrupt void XINT1_ISR(void) {

// Insert ISR Code here

// To receive more interrupts from this PIE group, acknowledge this interrupt // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;

// Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (\ ESTOP0\ for(;;); }

// INT1.5

interrupt void XINT2_ISR(void) {

// Insert ISR Code here

// To receive more interrupts from this PIE group, acknowledge this interrupt // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;

// Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (\ ESTOP0\ for(;;); }

// INT1.6

interrupt void ADCINT_ISR(void) // ADC {

// Insert ISR Code here

// To receive more interrupts from this PIE group, acknowledge this interrupt // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;

// Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (\ ESTOP0\ for(;;); }

// INT1.7

interrupt void TINT0_ISR(void) // CPU-Timer 0 {

// Insert ISR Code here

// To receive more interrupts from this PIE group, acknowledge this interrupt

// PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;

// Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (\ ESTOP0\ for(;;); }

// INT1.8

interrupt void WAKEINT_ISR(void) // WD {

// Insert ISR Code here

// To receive more interrupts from this PIE group, acknowledge this interrupt // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;

// Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (\ ESTOP0\ for(;;); }

// ----------------------------------------------------------- // PIE Group 2 - MUXed into CPU INT2

// -----------------------------------------------------------

// INT2.1

interrupt void CMP1INT_ISR(void) // EV-A {

// Insert ISR Code here

// To receive more interrupts from this PIE group, acknowledge this interrupt // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;

// Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (\ ESTOP0\ for(;;); }

// INT2.2

interrupt void CMP2INT_ISR(void) // EV-A

{

// Insert ISR Code here

// To receive more interrupts from this PIE group, acknowledge this interrupt // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;

// Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (\ ESTOP0\ for(;;); }

// INT2.3

interrupt void CMP3INT_ISR(void) // EV-A {

// Insert ISR Code here

// To receive more interrupts from this PIE group, acknowledge this interrupt // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;

// Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (\ ESTOP0\ for(;;); }

// INT2.4

interrupt void T1PINT_ISR(void) // EV-A {

// Insert ISR Code here

// To receive more interrupts from this PIE group, acknowledge this interrupt // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;

// Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (\ ESTOP0\ for(;;); }

// INT2.5

interrupt void T1CINT_ISR(void) // EV-A

{

// Insert ISR Code here

// To receive more interrupts from this PIE group, acknowledge this interrupt // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;

// Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (\ ESTOP0\ for(;;); }

// INT2.6

interrupt void T1UFINT_ISR(void) // EV-A {

// Insert ISR Code here

// To receive more interrupts from this PIE group, acknowledge this interrupt // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;

// Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (\ ESTOP0\ for(;;); }

// INT2.7

interrupt void T1OFINT_ISR(void) // EV-A {

// Insert ISR Code here

// To receive more interrupts from this PIE group, acknowledge this interrupt // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;

// Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (\ ESTOP0\ for(;;); }

// INT2.8 - Reserved

// ----------------------------------------------------------- // PIE Group 3 - MUXed into CPU INT3

// -----------------------------------------------------------

// INT 3.1

interrupt void T2PINT_ISR(void) // EV-A {

// Insert ISR Code here

// To receive more interrupts from this PIE group, acknowledge this interrupt // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;

// Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (\ ESTOP0\ for(;;); }

// INT3.2

interrupt void T2CINT_ISR(void) // EV-A {

// Insert ISR Code here

// To receive more interrupts from this PIE group, acknowledge this interrupt // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;

// Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (\ ESTOP0\ for(;;); }

// INT3.3

interrupt void T2UFINT_ISR(void) // EV-A {

// Insert ISR Code here

// To receive more interrupts from this PIE group, acknowledge this interrupt // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;

// Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (\ ESTOP0\ for(;;);

}

// INT3.4

interrupt void T2OFINT_ISR(void) // EV-A {

// Insert ISR Code here

// To receive more interrupts from this PIE group, acknowledge this interrupt // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;

// Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (\ ESTOP0\ for(;;); }

// INT3.5

interrupt void CAPINT1_ISR(void) // EV-A {

// Insert ISR Code here

// To receive more interrupts from this PIE group, acknowledge this interrupt // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;

// Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (\ ESTOP0\ for(;;); }

// INT3.6

interrupt void CAPINT2_ISR(void) // EV-A {

// Insert ISR Code here

// To receive more interrupts from this PIE group, acknowledge this interrupt // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;

// Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (\ ESTOP0\ for(;;); }

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