ICC workshop学习笔记

*************************************************************************** 1. 填充单元 它是用来填充I/O单元和I/O单元之间的间隙。对于标准单元则同样有标准填充单元(filler cell)

它也是单元库中定义的与逻辑无关的填充物，它的作用主要是把扩散层连接起来满足DRC规则和设计需要，

并形成电源线和地线轨道(power rails)

2. 电压钳位单元tie cell数字电路中某些信号端口，或闲置信号端口需要钳位在固定的逻辑电平上，电压钳位单元按逻辑功能要求把这些钳位 信号通过钳高单元(tie-high)与Vdd相连，或通过钳低单元(tie-low)与Vss相连使维持在确定的电位上。电压钳位单元还起到隔离普通信号的特护信号(Vdd，Vss)

的作用，在作LVS分析或形式验证(formal verification)时不致引起逻辑混乱。

3. 二极管单元为避免芯片加工过程中的天线效应导致器件栅氧击穿，通常布线完成后需要在违反天线规则的栅输入端加入反偏二极管，这些二极管可以把加工过程中金属层积累的电荷释放到地端以避免器件失效。

4. 去耦单元当电路中大量单元同时翻转时会导致充放电瞬间电流增大，使得电路动态供电电压下降或地线电压升高，引起动态电压降(IR-drop) 为避免动态电压降

对电路性能的影响，通常在电源和地线之间放置由MOS管构成的电容，这种电容被称为去耦电容或去耦单元(decap cell) 他的作用是在瞬态电流增大，电压下降 是电路补充电流以保持电源和地线这之间的电压稳定，防止电源线的电压降和地线电压的升高。去耦单元是与逻辑无关的附加单元

5. 时钟缓冲单元时序电路设计的一个关键问题是对时钟树的设计，芯片中的时钟信号需要传送到电路中的所有时序单元。为了保证时钟沿到达各个触发器的时间偏差

(skew)尽可能地小，需要插入时钟缓冲器减小负载和平衡延时，在标准单元库中专门设计了供时钟树选用的时钟缓冲单元(clock buffer)和时钟反向器单元(clock inverter)

时钟树综合工具根据指定的时钟缓冲单元去自动构建满足时序要求的时钟网络。时钟缓冲单元是专用的逻辑单元

6. 延时缓冲单元 延时缓冲单元的作用与时钟缓冲单元相类似，它是为了调解电路中的一些路径的延时以符合时序电路的要求而设计。例如：在同步电路设计中通常采用添加 延时缓冲单元的方法来保证复位信号到达各个触发器的时间相同。避免因复位信号不一致而导致系统逻辑的混乱

7. 阱连接单元(well-tap cell) 阱连接单元属纯物理单元，没有任何逻辑功能和时序约束，主要用于限制电源或地与衬底之间的电阻大小，减小锁效应。它是近年来在130nm 或更加先进的工艺低功耗设计中新增加的一种特殊单元。

8. 电压转换单元 电压转换单元(level shifter)是近年来在90nm或更加先进的低功耗设计中新增加的一种特殊单元，用于低功耗多供电电压设计中芯片不同电压域模块之间信号电压转换。种类包括低到高、高到低以及双向电压转换三种，一般低到高电压转换单元有高电压和低电压两个供电端口，此外该单元放置在电压域的边处。 9. 隔离单元(isolation) 隔离单元专门用于低功耗设计，它可以和上述的电平转换单元结合在一起，做成具有双重功能的单元

10. 开关单元开关单元专门用于低功耗的，有精细结构和粗制结构两种，前者目前较少用，形状上有环状和柱状两种。环状开关单元由SRPG单元来实现，柱状开关单元可以 用门控单元实现。

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***整体步骤： ICC的步骤就是开始一个design，必须对这个design先建立milkyway

library。这个milkyway library指的就是你当前的design的database，当你完成当前design的P&R后，此library就包含了你的design的所有layout信息如fp，placement，routing等等。

而target library，link library指的是你的design要调用的stdcell，memory，IP的timing信息。

milkyway reference library指的就是你所调用的stdcell、memory、IP的physical 信息，一般有fram view，cell view等等。 Fram view一般只包含IO pin信息，而cell view包含了很详细的PR信息。

***唯一化：

? When reading in a non-uniquified design, the first commands of your ICC script should

be: current_design MY_TOP_DESIGN ? uniquify 读入设计后，先对设计进行器件唯一化：uniquify。

注：为了在布图时进行时钟树综合，必须唯一化DC中的网表。此操作为设计中多次例化的子模块生成唯一的模块/实体定义。原因：1.存在于这些模块内的触发器需要连接到时钟源，而把时钟树连接到这些模块需要单独的时钟连线名。2.物理上要求这些模块有单独的位置。 3.当时钟树从布图工具转到DC时，未唯一化的网表就存在问题，这问题只发生在如果时钟树信息单独转到DC，不包括从布图工具到DC的完整网表转移。 布图工具可以自己唯一化网表。 ***

.tf——technology specific information 技术库，包含金属层的物理信息。 .tlu——Look-up table for RC； 包含RC信息

.itf——interconnect format； 由供应商提供的交互文件 .db——Timing information(R, C, L) of IPs; 包含IP的时序信息

若tluplus file没有时，可由Foundry给的.itf转成tluplus（用StarRC，在shell下用此命令就行：> grdgenxo -itf2TLUPlus）。

***Keepout margin：禁止边缘

A keepout margin is a region (the unshaded portion in Figure 6-1) around the boundary of fixed macros in your design in which no other cells are placed.

Keeping the placement of cells out of such regions avoids congestion and net detouring and produces better QoR(quality of results). 避免阻塞和net绕道迂回。

***If you want to remove the current timing constraints before applying new constraints: remove_sdc # Removes all existing SDC constraints

read_sdc timing_constraints.sdc #Reads in a script in SDC format.

***Generating TLU+ Models

***Convert LEF to Milkyway FRAM

The above applies to reference libraries only.

***logical libraries提供单元时序信息

The “*” stands for all designs that have already been loaded into IC Compiler.

***Milkyway Reference Libraries

Information is stored in so-called “views”, for example:

? CEL: The full layout view

? FRAM: The abstract view used for P&R

? LM: Logic Model with Timing and Power info (optional*)。

? Reference library 包括以下几部分：stand cell library、pad library、macro cell（或IP

library）。

? Pad cell 包括信号pad、电源地pad ? Macro 即设计中用到的一些宏模块

? 下页以图讲解stand cell、pad cell、macro

*** How does IC Compiler Find Files?

You may specify where to look for files:

lappend search_path ./design_data ../scripts lappend search_path [glob $MW_libs/*/LM]

the command lappend is used to “append” two paths to the current setting of search_path. Never use the command “set” to set this variable.

You can also use set instead of lappend to modify the search_path: set search_path \cripts“ set search_path \

Typically, the target_library points to your standard cells only，other cell librays such as used for SRMA or ROM are set in the link_path,for example: Set target_library “slow.db” Set link_library “* fast.db slow.db io_max.db ram32x32.db”

create library

By creating a design library!

create_mw_lib design_lib_orca -technology techfile.tf -mw_reference_library “sc io ram32” -open

You may also create the library first, then add the reference libraries afterwards: create_mw_lib design_lib_orca –technology techfile.tf

set_mw_lib_reference design_lib_orca –mw_reference_library \

If the “-open” switch is not used, the library needs to be opened in order to

import the design:

open_mw_lib design_lib_orca

saving and loading the design

? Once setup is complete, save the Milkyway design:

? By default, link_library, search_path, target_library and TLU+ settings are stored with the

CEL

? If library files change or move to somewhere else, the settings have to be

re-applied. See notes section below!

? When you re-open the CEL, by default the stored settings are not re-applied,

unless you set:

set auto_restore_mw_cel_lib_setup true open_mw_cel orca_init

Whether settings are stored with the MW library or not is controlled through the variable save_mw_cel_lib_setup. This variable is set to true by default.

When the logical libraries change, please follow this procedure: set auto_restore_mw_cel_lib_setup false set search_path \set link_library \set target_library \open_mw_cel -lib link

set_tlu_plus_files –max_tlu <> –min_tlu <> –tech2itf <>

the design library

Structure of a Design Milkyway Database

This library data structure or design database is called Milkyway. Milkyway实际就是一个数据库。

Summary

ICC recommended setup

# load common settings & useful procedures source ../ref/icc_settings.tcl lappend search_path ./scripts ../ref/sdb ../ref/db set symbol_library \ set link_library \set target_library \create_mw_lib design_lib_orca -open \\ -technology techfile.tf \\ -mw_reference_library \set mw_logic0_net \set mw_logic1_net \import_designs design.ddc \\ -format ddc \\ -top ORCA_TOP read_def –allow_physical design.def def是fp文件 save_mw_cel –overwrite或save_mw_cel -as ORCA_TOP # CEL saved as ORCA_TOP The example above reads a DDC file created by Design Compiler. The DDC file contains timing constraints already, therefore read_sdc was not used.

The following two variables are set by default by the tool. If logic 0/1 are connected to different supply names, settings must be changed. set mw_logic0_net “VSS” set mw_logic1_net “VDD”

If the settings are changed, you need to make sure that the variables are changed before you read the design into IC Compiler.

Note that import_designs has to be run after the design library has been created using create_mw_lib.

IC Compiler Three Initialization Files

import design

import_designs orca.v \\ -format verilog \\ -top ORCA_TOP

Can be replaced by:

read_verilog –netlist orca.v current_design ORCA_TOP uniquify link

save_mw_cel –as ORCA_TOP

4 design planning

DP Features Flat vs. Hierarchical

Create the Starting Floorplan

Connecting Power and Ground Ports

The macro cells and modules in your design contain power and ground pins that must be connected before initializing the floorplan.

icc_shell>

derive_pg_connection -power_net VDD -power_pin VDD \\ -ground_net VSS -ground_pin VSS

In the case of a single voltage design, the -power_net name and -ground_net name options are required.

Using the GUI Menu Command to Perform Power and Ground Connections

To perform automatic power and ground and tie connections, Note:

Make sure the PG network already exists in the design before you run the

derive_pg_connection -tie command. If you run the derive_pg_connection –tiecommand before the PG network is created, it can cause unexpected results for the PGtie-off connections in the design flow.

Creating Power and Ground Ports(optional)

Depending on the floorplan creation flow you use, you can add top-level power and groundports at the same time that you connect the power and ground pins in your design. Use thederive_pg_connection command with the -create_ports top option to automatically create ports for the nets specified by the -power_net and -ground_net options. In the GUI,choose Preroute > Derive PG Connection. In the Derive Power Ground Connection dialogbox that opens, select “Manual connection” and then select Top as the “Create port” option.

Adding Power, Ground, and Corner Cells(optional)

Physical-only cells for power, ground, and corner placement might not be part of the synthesized netlist and must be added to design. Use the create_cell command to add aleaf or hierarchical cell to the current design.

Setting the I/O Pad Constraints(optional)

Before initializing the floorplan, you can create placement and spacing settings for I/O padsby using the set_pad_physical_constraints command. This command specifies the padcell ordering, orientation, placement side, offset from die edge, and pad-to-pad spacing foreach I/O pad. After setting the constraints with the

set_pad_physical_constraintscommand, the initialize_floorplan command places the I/O pad cells accordingly. Theconstraints are stored in the Milkyway database when you save the design.

The initialize_floorplan command places constrained pads first. Any

unconstrainedpads are placed next, using any available pad location. The tool does not placeunconstrained pads between consecutively ordered constrained pads.

The following example script portion describes two corner pad locations and several I/O padlocations for the floorplan.

create_cell {cornerll cornerlr cornerul cornerur} cornercell create_cell {vss1left vss1right vss1top vss1bottom} vsscell # additional create_cell commands not shown

set_pad_physical_constraints -pad_name \set_pad_physical_constraints -pad_name \# additional corner pad constraints not shown

set_pad_physical_constraints -pad_name \set_pad_physical_constraints -pad_name \# additional left side pad constraints not shown

set_pad_physical_constraints -pad_name \-side 2 -order 1 set_pad_physical_constraints -pad_name \-side 2 -order 2 # additional top side pad constraints not shown

set_pad_physical_constraints -pad_name \-side 3 -order 1

set_pad_physical_constraints -pad_name \-side 3 -order 2

# additional right side pad constraints not shown

set_pad_physical_constraints -pad_name \set_pad_physical_constraints -pad_name \# additional bottom side pad constraints not shown

Setting the Pin Constraints

You can use the set_pin_physical_constraints command to set constraints on individual pins or nets. Use the set_fp_pin_constraints command to set global constraints for a block. If a conflict arises between the individual pin constraints and

theglobal pin constraints, the individual pin constraints have higher priority. The constraints arestored in the Milkyway database.

Saving the Pin and Pad Constraints

You can save the current pin and pad constraints for your design with the

write_pin_pad_physical_constraints command. This command creates a constraintsfile that contains set_pin_physical_constraints and

set_pad_physical_constraintscommands that you can use to reapply pin and pad constraints. The positional informationfor the pins and pads is based on their current location in the design.

To create the pin and pad constraints file, use

thewrite_pin_pad_physical_constraintscommand (or by choosing Floorplan > Write Pin/Pad Physical Constraints in the GUI).

Reading an Existing Pad and Pin Constraints File

Use the read_pin_pad_physical_constraints command (or by choosing

Floorplan >Read Pin/Pad Physical Constraints in the GUI) to read a file that contains set_pin_physical_constraints and set_pad_physical_constraints

commands. Theread_pin_pad_physical_constraints command applies the constraints to the currentdesign or to another design that you specify.

The constraints defined in the file can either remove the current constraints or append tothem, based on the behavior you choose. For example, if physical constraints for pin A arespecified and you do not define any constraints for pin A in the constraints file, theread_pin_pad_physical_constraints command removes the existing physicalconstraints on pin A by default. To maintain the existing constraints and append newconstraints contained in the constraints file, specify the -append option (or click the“Append” check box in the GUI).

Reporting the Pad and Pin Constraints

Use the report_pin_pad_physical_constraints command to display a list of set_pin_physical_constraints and set_pad_physical_constraints

commands thatdefine the pin and pad constraints for the current design. You can report only pin constraints,only pad constraints, only chip-level pad constraints, or all constraints depending on thecommand options you specify.

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