HYM4V33100DTYG-75中文资料

元器件交易网

1Mx32 bits

PC133 SDRAM AIMM

based on 1Mx16 SDRAM with LVTTL, 2 banks & 4K Refresh

HYM4V33100DTYG Series

DESCRIPTION

The Hynix HYM4V33100DTYG Series are 1Mx16bits Synchronous DRAM Modules. The modules are composed of two 1Mx16bitsCMOS Synchronous DRAMs in 400mil 50pin TSOP-II package, on a 132pin glass-epoxy printed circuit board. Two 0.22uF and one0.1uF decoupling capacitors per each SDRAM are mounted on the PCB.

The Hyundai HYM4V33100DTYG Series are AGP In-line Memory Modules suitable for easy interchange and addition of 4Mbytesmemory. The Hyundai HYM4V33100DTYG Series are fully synchronous operation referenced to the positive edge of the clock . Allinputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very highbandwidth.

FEATURES

PC133/PC100MHz support132pin SDRAM AIMM

1.4” (35.56mm) Height PCB with double sided com-ponents

Single 3.3±0.3V power supply

- 1, 2, 4 or 8 or Full page for Sequential Burst

All device pins are compatible with LVTTL interface

- 1, 2, 4 or 8 for Interleave Burst

Data mask function by DQM

SDRAM internal banks : two banks

Programmable CAS Latency ; 2, 3 Clocks

Module bank : one physical bankAuto refresh and self refresh4096 refresh cycles / 64ms

Programmable Burst Length and Burst Type

ORDERING INFORMATION

Part No.

HYM4V33100DTYG-75

Clock Frequency

133MHz

InternalBank

4 Banks

Ref.

4K

Power

Normal

SDRAMPackage

TSOP-II

Plating

Gold

This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of

HYM4V33100DTYG Series

PIN DESCRIPTION

PIN

CK0, CK1CKE/CSBAA0 ~ A10/RAS, /CAS, /WEDQM0~DQM3DQ0 ~ DQ31VCCVSSNC

PIN NAME

Clock InputsClock EnableChip Select

SDRAM Bank AddressAddress

Row Address Strobe, Column Address Strobe, Write EnableData Input/Output MaskData Input/OutputPower Supply (3.3V)GroundNo Connection

DESCRIPTION

The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK

Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refreshEnables or disables all inputs except CK, CKE and DQMSelects bank to be activated during /RAS activitySelects bank to be read/written during /CAS activityRow Address : RA0 ~ RA10, Column Address : CA0 ~ CA7Auto-precharge flag : A10

/RAS, /CAS and /WE define the operationRefer function truth table for details

Controls output buffers in read mode and masks input data in write modeMultiplexed data input / output pin

Power supply for internal circuits and input buffersGroundNo connection

HYM4V33100DTYG Series

PIN ASSIGNMENTS

FRONT SIDEPIN NO.

1357911131517192123252729313335373941434547495153555759616365

BACK SIDE

PIN NO.

24681012141618202224262830323436384042444648505254565860626466

FRONT SIDEPIN NO.

6769717375777981838587899193959799101103105107109111113115117119121123125127129131

BACK SIDE

PIN NO.

68707274767880828486889092949698100102104106108110112114116118120122124126128130132

NAME

NCNCGNDNCVCCNCGNDDQ25DQ26GNDFSELKEYWAYKEYWAYTCLK1CASGNDRASA0GNDA8A10GNDVCCCSGNDA1A5GNDA3NCGNDDQ7DQM0

NAME

TYPEDET

NCNCNCDQM3DQ24NCVCCNCWEKEYWAYKEYWAYTCLK0VCCNCNCVDDQA9A11VDDQNCNCA7NCA6VDDQA2A4VDDQDQ5DQ6VDDQNC

NAME

NCNCGNDNCVCCDQ29GNDDQ31DQM2GNDDQ22KEYWAYKEYWAYDQ20DQ19GNDDQ17DQ16GNDDQ13DQ12GNDVCCVDDQGNDDQ10DQ9GNDDQ0NCGNDDQ3DQ4

NAME

NCNCNCDQ27DQ28DQ30NCVCCNCDQ23KEYWAYKEYWAYDQ21VCCDQ18NCVDDQDQ15DQ14VDDQNCNCDQ11NCNCVDDQDQ8DQM1VDDQDQ1DQ2VDDQNC

HYM4V33100DTYG Series

ABSOLUTE MAXIMUM RATINGS

Parameter

Ambient TemperatureStorage Temperature

Voltage on Any Pin relative to VSSVoltage on VDD relative to VSSShort Circuit Output CurrentPower Dissipation

Soldering Temperature Time

TATSTGVIN, VOUTVDD, VDDQIOSPDTSOLDER

Symbol

0 ~ 70-55 ~ 125-1.0 ~ 4.6-1.0 ~ 4.6501260 10

Rating

°C°CVVmAW°C Sec

Unit

Note : Operation at above absolute maximum rating can adversely affect device reliability.

DC OPERATING CONDITION (TA=0 to 70°C)

Parameter

Power Supply VoltageInput High voltageInput Low voltage

SymbolVDD, VDDQVIHVIL

Min3.02.0-0.3

Typ3.33.00

Max3.6VDDQ + 0.3

0.8

UnitVVV

Note11,21,3

Note :

1.All voltages are referenced to VSS = 0V

2.VIH(max) is acceptable 5.6V AC pulse width with <=3ns of duration.3.VIL(min) is acceptable -2.0V AC pulse width with <=3ns of duration.

AC OPERATING TEST CONDITION (TA=0 to 70°C, VDD=3.3±0.3V, VSS=0V)

Parameter

AC Input High / Low Level Voltage

Input Timing Measurement Reference Level VoltageInput Rise / Fall Time

Output Timing Measurement Reference Level VoltageOutput Load Capacitance for Access Time Measurement

SymbolVIH / VILVtriptR / tFVoutrefCL

Value2.4/0.41.411.450

UnitVVnsVpF

1Note

Note :

1.Output load to measure access times is equivalent to two TTL gates and one capacitor (50pF). For details, refer to AC/DC output load circuit

HYM4V33100DTYG Series

CAPACITANCE (TA=25°C, f=1MHz)

-75

Parameter

CK0, CK1CKE0, CKE1

Input Capacitance

/S0, /S1A0~10, BA0/RAS, /CAS, /WEDQM0~DQM3

Data Input / Output Capacitance

DQ0 ~ DQ31

Pin

Symbol

Min

CI1CI2CI3CI4CI5

CI6CI/O

5510101055

Max10101520201015

pFpFpFpFpFpFpFUnit

OUTPUT LOAD CIRCUIT

HYM4V33100DTYG Series

DC CHARACTERISTICS I (TA=0 to 70°C, VDD=3.3±0.3V)

Parameter

Input Leakage CurrentOutput Leakage CurrentOutput High VoltageOutput Low Voltage

ILIILOVOHVOL

Symbol

Min.-8-12.4-Max81-0.4

UnituAuAVV

Note12

IOH = -4mAIOL = +4mA

Note :

1.VIN = 0 to 3.6V, All other pins are not tested under VIN =0V2.DOUT is disabled, VOUT=0 to 3.6

DC CHARACTERISTICS II

Speed

Parameter

Symbol

Test Condition

-75

Operating Current

IDD1

Burst length=1, One bank active tRC ≥ tRC(min), IOL=0mACKE ≤ VIL(max), tCK = minCKE ≤ VIL(max), tCK = ∞

CKE ≥ VIH(min), CS ≥ VIH(min), tCK = minInput signals are changed one time during 2clks. All other pins ≥ VDD-0.2V or ≤ 0.2VCKE ≥ VIH(min), tCK = ∞Input signals are stable.CKE ≤ VIL(max), tCK = minCKE ≤ VIL(max), tCK = ∞

CKE ≥ VIH(min), CS ≥ VIH(min), tCK = minInput signals are changed one time during 2clks. All other pins ≥ VDD-0.2V or ≤ 0.2VCKE ≥ VIH(min), tCK = ∞Input signals are stable.tCK ≥ tCK(min), IOL=0mAAll banks active

tRRC ≥ tRRC(min), All banks activeCKE ≤ 0.2V

CL=3

2202

mA

2

mA

1

Unit

Note

Precharge Standby Current IDD2Pin Power Down Mode

IDD2PS

IDD2N

Precharge Standby Current in Non Power Down Mode

IDD2NS

Active Standby Current in Power Down Mode

IDD3PIDD3PS

40

mA

3060

mA

60

IDD3N

Active Standby Current in Non Power Down Mode

IDD3NS

Burst Mode Operating Current

Auto Refresh CurrentSelf Refresh Current

100

mA

60

IDD4IDD5IDD6

2202204

mAmAmA

123

Note :

1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open2. Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II3.HYM4v33100DTYG-75

AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)

-75

Parameter

Symbol

Min

System Clock Cycle Time

CAS Latency = 3CAS Latency = 2

tCK3tCK2tCHWtCLWtAC3tAC2tOHtDStDHtAStAHtCKStCKHtCStCHtOLZtOHZ3tOHZ2

7.5

1000

102.52.5--2.71.50.81.50.81.50.81.50.812.73

--5.46----------5.46

nsnsnsns

2

CAS Latency = 2

nsnsnsnsnsnsnsnsnsnsnsnsns

1111111111

Max

nsUnit

Note

HYM4V33100DTYG Series

Clock High Pulse WidthClock Low Pulse WidthAccess Time From Clock

CAS Latency = 3

Data-Out Hold TimeData-Input Setup TimeData-Input Hold TimeAddress Setup TimeAddress Hold TimeCKE Setup TimeCKE Hold TimeCommand Setup TimeCommand Hold Time

CLK to Data Output in Low-Z TimeCLK to Data

Output in High-Z Time

CAS Latency = 3CAS Latency = 2

Note :

1.Assume tR / tF (input rise and fall time ) is 1ns

If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter

2.Access times to be measured with input signals of 1v/ns edge rate, from 0.8v to 2.0v If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter

HYM4V33100DTYG Series

AC CHARACTERISTICS II

-75

Parameter

Symbol

Min

Operation

Auto Refresh

RAS to CAS DelayRAS Precharge Time

RAS to RAS Bank Active DelayCAS to CAS Delay

Write Command to Data-In DelayData-In to Precharge CommandData-In to Active CommandDQM to Data-Out Hi-ZDQM to Data-In MaskMRS to New CommandPrecharge to Data Output Hi-Z

CAS Latency = 3CAS Latency = 2

tRRCtRCDtRAStRPtRRDtCCDtWTLtDPLtDALtDQZtDQMtMRDtPROZ3tPROZ2tPDEtSREtREF

652045201510252023211---100K-------------64

nsnsnsnsnsCLKCLKCLKCLKCLKCLKCLKCLKCLKCLKCLKms

1

tRC

65

Max-nsUnit

Note

Power Down Exit TimeSelf Refresh Exit TimeRefresh Time

Note :

1. A new command can be given tRRC after self refresh exit

HYM4V33100DTYG Series

DEVICE OPERATING OPTION TABLE

HYM4V33100DTYG-75

CAS Latency

133MHz(7.5ns)

3CLKs

tRCD3CLKs

tRAS6CLKs

tRC9CLKs

tRP3CLKs

tAC5.4ns

tOH2.7ns

COMMAND TRUTH TABLE

Command

Mode Register SetNo OperationBank ActiveRead

H

Read with AutoprechargeWrite

Write with AutoprechargePrecharge All BanksPrecharge selected BankBurst StopDQMAuto Refresh

Entry

Self Refresh1

Exit

HHHHL

HLH

LLHLH

Entry

Precharge power down

Exit

L

H

H

L

LHLHL

Exit

L

H

HXHXV

X

HXHXV

HXHXV

XX

X

L

HXLLXHX

LLXHX

HHXHX

X

X

H

L

XVXXX

X

H

X

L

H

L

L

X

CA

X

L

H

L

H

X

CA

HLHHLXXX

VXV

CKEn-1HHH

CKEnXX

L

X

L

HL

HH

HH

X

RA

L

VV

CSLH

RASLX

CASLX

WELX

X

X

DQMX

ADDR

A10/APOP code

BANote

HXLLHLXX

Clock Suspend

EntryHLX

X

Note :

1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high

2. X = Don′t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address, Opcode = Operand Code, NOP = No Operation

HYM4V33100DTYG Series

PACKAGE DEMENSION

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