TC24C64两线EEPROM存储芯片

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TC24C64是腾芯微专门研发的两线EEPROM存储芯片

TC24C64A

Two-Wire Serial EEPROM

32K, 64K (8-bit wide)

FEATURES

Low voltage and low power operations:

TC24C32A/64A: VCC = 1.8V to 5.5V

Maximum Standby current < 1µA (typically 0.02µA and 0.06µA @ 1.8V and 5.5V respectively). 32 bytes page write mode.

Partial page write operation allowed.

Internally organized: 4,096 × 8 (32K), 8,192 × 8 (64K). Standard 2-wire bi-directional serial interface. Schmitt trigger, filtered inputs for noise protection. Self-timed Write Cycle (5ms maximum).

800 kHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) Compatibility. Automatic erase before write operation.

Write protect pin for hardware data protection.

High reliability: typically 1, 000,000 cycles endurance. 100 years data retention.

Industrial temperature range (-40℃ to 85℃).

Standard 8-lead DIP/SOP/ MSOP/TSSOP/DFN and 5-lead SOT23/TSOT23 Pb-free packages.

DESCRIPTION

The TC24C32A/64A series are 32,768/65,536 bits of serial Electrical Erasable and Programmable Read Only Memory, commonly known as EEPROM. They are organized as 4096/8192 words of 8 bits (one byte) each. The devices are fabricated with proprietary advanced CMOS process for low power and low voltage applications. These devices are available in standard 8-lead DIP, 8-lead SOP, 8-lead MSOP, 8-lead TSSOP, 8-lead DFN, 5-lead SOT23, and 5-lead TSOT23 packages. A standard 2-wire serial interface is used to address all read and write functions. Our extended VCC range (1.8V to 5.5V) devices enables wide spectrum of applications.

PIN CONFIGURATION

Pin Name

Pin Function A2, A1, A0 Device Address Inputs SDA SCL WP No-Connect

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TC24C64是腾芯微专门研发的两线EEPROM存储芯片

TC24C64A

All these packaging types come in Pb-free certified.

A0A1A2GND

VCCWPSCLSDA

8L DIP8L SOP8L MSOP8L TSSOP8L DFN

5L SOT235L TSOT23

-40℃ to 85℃ -50℃ to 125℃

ABSOLUTE MAXIMUM RATINGS

Industrial operating temperature: Storage temperature:

Input voltage on any pin relative to ground: -0.3V to VCC + 0.3V Maximum voltage: 8V

ESD Protection on all pins: >2000V

* Stresses exceed those listed under “Absolute Maximum Rating” may cause permanent damage to the device. Functional operation of the device at conditions beyond those listed in the specification is not guaranteed. Prolonged exposure to extreme conditions may affect device reliability or functionality.

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TC24C64是腾芯微专门研发的两线EEPROM存储芯片

TC24C64A

PIN DESCRIPTIONS

(A) SERIAL CLOCK (SCL)

The rising edge of this SCL input is to latch data into the EEPROM device while the falling edge of this

clock is to clock data out of the EEPROM device. (B) DEVICE / CHIP SELECT ADDRESSES (A2, A1, A0)

These are the chip select input signals for the serial EEPROM devices. Typically, these signals are hardwired to either VIH or VIL. If left unconnected, they are internally recognized as VIL. (C) SERIAL DATA LINE (SDA)

SDA data line is a bi-directional signal for the serial devices. It is an open drain output signal and can be wired-OR with other open-drain output devices. (D) WRITE PROTECT (WP)

The TC24C32A/64A devices have a WP pin to protect the whole EEPROM array from programming. Programming operations are allowed if WP pin is left un-connected or input to VIL. Conversely all programming functions are disabled if WP pin is connected to VIH or VCC. Read operations is not affected by the WP pin’s input level.

MEMORY ORGANIZATION

The TC24C32A/64A devices have 128/256 pages respectively. Since each page has 32 bytes, random word addressing to FT24C32A/64A will require 12/13 bits data word addresses respectively.

DEVICE OPERATION

(A) SERIAL CLOCK AND DATA TRANSITIONS

The SDA pin is typically pulled to high by an external resistor. Data is allowed to change only when Serial clock SCL is at VIL. Any SDA signal transition may interpret as either a START or STOP condition as described below. (B) START CONDITION

With SCL 　VIH, a SDA transition from high to low is interpreted as a START condition. All valid commands must begin with a START condition.

With SCL 　VIH, a SDA transition from low to high is interpreted as a STOP condition. All valid read or write commands end with a STOP condition. The device goes into the STANDBY mode if it is after a read command. A STOP condition after page or byte write command will trigger the chip into the

STANDBY mode after the self-timed internal programming finish (see Figure 1). (D) ACKNOWLEDGE

The 2-wire protocol transmits address and data to and from the EEPROM in 8 bit words. The EEPROM acknowledges the data or address by outputting a "0" after receiving each word. The ACKNOWLEDGE signal occurs on the 9th serial clock after each word.

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TC24C32_64-A0--page3

TC24C64是腾芯微专门研发的两线EEPROM存储芯片

TC24C64A

(E) STANDBY MODE

The EEPROM goes into low power STANDBY mode after a fresh power up, after receiving a STOP bit in read mode, or after completing a self-time internal programming operation.

Figure 1: Timing diagram for START and STOP conditions

SCL

SDA

START Condition

Data Data Valid Transition

STOP Condition

Figure 2: Timing diagram for output ACKNOWLEDGE

START Condition

SCL

Data in

Data out

ACK

DEVICE ADDRESSING

The 2-wire serial bus protocol mandates an 8 bits device address word after a START bit condition to invoke a valid read or write command. The first four most significant bits of the device address must be 1010, which is common to all serial EEPROM devices. The next three bits are device address bits. These three device address bits (5th, 6th and 7th) are to match with the external chip select/address pin states. If a match is made, the EEPROM device outputs an ACKNOWLEDGE signal after the 8th read/write bit, otherwise the chip will go into STANDBY mode. However, matching may not be needed for some or all device address bits (5th, 6th and 7th) as noted below. The last or 8th bit is a read/write command bit. If the 8th bit is at VIH then the chip goes into read mode. If a “0” is detected, the device enters programming mode.

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TC24C32_64-A0--page4

TC24C64是腾芯微专门研发的两线EEPROM存储芯片

TC24C64A

WRITE OPERATIONS

(A) BYTE WRITE

A write operation requires two 8-bit data word address following the device address word and ACKNOWLEDGE signal. Upon receipt of this address, the EEPROM will respond with a “0” and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will again output a “0”. The addressing device, such as a microcontroller, must terminate the write sequence with a STOP condition. At this time the EEPROM enters into an internally-timed write cycle state. All inputs are disabled during this write cycle and the EEPROM will not respond until the writing is completed (figure 3). (B) PAGE WRITE

The 32K/64K EEPROM are capable of 32-byte page write.

A page write is initiated the same way as a byte write, but the microcontroller does not send a STOP condition after the first data word is clocked in. The microcontroller can transmit up to 31 more data words after the EEPROM acknowledges receipt of the first data word. The EEPROM will respond with a “0” after each data word is received. The microcontroller must terminate the page write sequence with a STOP condition (see Figure 4).

The lower five bits of the data word address are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. If more than 32 data words are transmitted to the EEPROM, the data word address will “roll over” and the previous data will be overwritten. (C) ACKNOWLEDGE POLLING

ACKNOWLEDGE polling may be used to poll the programming status during a self-timed internal programming. By issuing a valid read or write address command, the EEPROM will not acknowledge at the 9th clock cycle if the device is still in the self-timed programming mode. However, if the programming completes and the chip has returned to the STANDBY mode, the device will return a valid ACKNOWLEDGE signal at the 9th clock cycle.

READ OPERATIONS

The read command is similar to the write command except the 8th read/write bit in address word is set to “1”. The three read operation modes are described as follows: (A) CURRENT ADDRESS READ

The EEPROM internal address word counter maintains the last read or write address plus one if the power supply to the device has not been cut off. To initiate a current address read operation, the micro-controller issues a START bit and a valid device address word with the read/write bit (8th) set to “1”. The EEPROM will response with an ACKNOWLEDGE signal on the 9th serial clock cycle. An 8-bit data word will then be serially clocked out. The internal address word counter will then automatically increase by one. For current address read the micro-controller will not issue an ACKNOWLEDGE signal on the 18th clock cycle. The micro-controller issues a valid STOP bit after the 18th clock cycle to terminate the read operation. The device then returns to STANDBY mode (see Figure 5). (B) SEQUENTIAL READ

The sequential read is very similar to current address read. The micro-controller issues a START bit

and a valid device address word with read/write bit (8th) set to “1”. The EEPROM will response with an ACKNOWLEDGE signal on the 9th serial clock cycle. An 8-bit data word will then be serially clocked out. Meanwhile the internally address word counter will then automatically increase by one.

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TC24C32_64-A0--page5

TC24C64是腾芯微专门研发的两线EEPROM存储芯片

TC24C64A

Unlike current address read, the micro-controller sends an ACKNOWLEDGE signal on the 18th clock cycle signaling the EEPROM device that it wants another byte of data. Upon receiving the ACKNOWLEDGE signal, the EEPROM will serially clocked out an 8-bit data word based on the incremented internal address counter. If the micro-controller needs another data, it sends out an ACKNOWLEDGE signal on the 27th clock cycle. Another 8-bit data word will then be serially clocked out. This sequential read continues as long as the micro-controller sends an ACKNOWLEDGE signal after receiving a new data word. When the internal address counter reaches its maximum valid address, it rolls over to the beginning of the memory array address. Similar to current address read, the micro-controller can terminate the sequential read by not acknowledging the last data word received, but sending a STOP bit afterwards instead (figure 6). (C) RANDOM READ

Random read is a two-steps process. The first step is to initialize the internal address counter with a target read address using a “dummy write” instruction. The second step is a current address read. To initialize the internal address counter with a target read address, the micro-controller issues a START bit first, follows by a valid device address with the read/write bit (8th) set to “0”. The EEPROM will then acknowledge. The micro-controller will then send two address words. Again the EEPROM will acknowledge. Instead of sending a valid written data to the EEPROM, the micro-controller performs a current address read instruction to read the data. Note that once a START bit is issued, the EEPROM will reset the internal programming process and continue to execute the new instruction - which is to read the current address (figure 7).

Figure 3: Byte Write

STARWRITSTODEVICE FIRST WORD SECOND WORD DATA

SDA LINE

S/CBWK

SCBK

Figure 4: Page Write

STARWRITSTO

DEVICE FIRST WORD SECOND WORD SDA LINE

S/CBWK

SCBK

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TC24C32_64-A0--page6

TC24C64是腾芯微专门研发的两线EEPROM存储芯片

TC24C64A

Figure 5: Current Address Read

STARREAD

STODEVICE DATA

SDA LINE

S/CBWK

O ACK

Figure 6: Sequential Read

DEVICE READ

STODATA (N)DATA (N+1)DATA (N+2)DATA (N+3)

/CWK

O ACK

Figure 7: Random Read

STARWRITSTARREAD

DEVICE FIRST WORD SECOND WORD DEVICE DATA (N)

STOSDA LINE

S/CBWK

SCBK

S/CBWK

O ACK

Notes: 1) * = Don’t Care bits

2) # = Don’t Care bits for TC24C32

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TC24C32_64-A0--page7

TC24C64是腾芯微专门研发的两线EEPROM存储芯片

TC24C64A

Figure 8: SCL and SDA Bus Timing

SCL

SDA IN

SDA OUT

AC CHARACTERISTICS

Symbol

Parameter Unit

Clock frequency, SCL Clock pulse width low Clock pulse width high

Noise suppression time(1)

Clock low to data out valid

Time the bus must be free before a new

transmission can start(1)START hold time START set-up time Data in hold time Data in set-up time Input rise time(1)

(1)

fSCL tLOW tHIGH tI tAA tBUF tHD.STA tSU.STA tHD.DAT tSU.DAT tR tF tSU.STO tDH tWR

1.2

400

0.9

800

kHz µs

0.6 0.6 0 100

µs µs µs ns

0.6 200

0.6 50

µs ns ms

Write Cycles

Input fall timeSTOP set-up time Date out hold time Write cycle time

Endurance(1)oC, Page Mode, 3.3V

1,000,000

Notes: 1. This Parameter is expected by characterization but are not fully screened by test.

2. AC Measurement conditions: RL (Connects to Vcc): 1.3K

Input Pulse Voltages: 0.3Vcc to 0.7Vcc

Input and output timing reference Voltages: 0.5Vcc

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TC24C32_64-A0--page8

TC24C64是腾芯微专门研发的两线EEPROM存储芯片

TC24C64A

DC CHARACTERISTICS

VCC1××A supply VCC ICC ICC

Supply read current Supply write current

VCC @ 5.0V SCL = 400 kHz VCC @ 5.0V SCL = 400 kHz

Test Units1.8

0.4 2.0

5.5 1.0 3.0

V mA mA

ISB1current ISB2current ISB3current ILO VIL VIH VOL2 VOL1

VCC @ 1.8V, VIN = VCC or VSSVCC @ 2.5V, VIN = VCC or VSSVCC @ 5.0V, VIN = VCC or VSS -0.6

VCC× 0.7

IILleakage VIN = VCC or VSS

Output leakage current VIN = VCC or VSS Input low level Input high level Output low level Output low level

VCC @ 3.0V, IOL = 2.1 mA VCC @ 1.8V, IOL = 0.15 mA

3.0 3.0

VCC× 0.3VCC + 0.5

µA µA V V V V

0.4 0.2

ORDERING INFORMATION

U:-40D: DIP8 S: SOP8 M: MSOP8 T: TSSOP8 L: SOT23-5 P: TSOT23-5 N: DFN8

Temperature Range

Packaging B: Tube

T: Tape and Reel HSF R: RoHS G: Green

Ordering Tape and ReelFT24C32A-USR-T

Tape and ReelFT24C32A-USG-T

Tape and ReelFT24C32A-UMR-T

Tape and ReelFT24C32A-UMG-T

RoHS

℃-85℃GreenRoHS

℃-85℃Green

Shenz hen Tengchip MicroTechnology Co.,Ltd.

32kbits

TC24C32_64-A0--pa

ge9

TC24C64是腾芯微专门研发的两线EEPROM存储芯片

TC24C64A

RoHS

℃-85℃Green

32kbits

RoHSGreenRoHS

℃-85℃GreenRoHS

℃-85℃GreenSOT23-5

-40℃-85℃

1.8V-5.5V

RoHS

℃-85℃GreenRoHS

℃-85℃Green

64kbits

RoHS

℃-85℃GreenRoHS

℃-85℃Green

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TC24C64是腾芯微专门研发的两线EEPROM存储芯片

TC24C64A

DIP8 PACKAGE OUTLINEDIMENSIONS

Symbol

Dimensions In Millimeters

Dimensions In Inches

A 3.710 4.310 0.146 0.170 A2 3.200 3.600 0.126 0.142 B 0.380 0.570 0.015 0.022

1.524（BSC）（BSC） C 0.204 0.360 0.008 0.014 D 9.000 9.400 0.354 0.370 E 6.200 6.600 0.244 0.260 E1 7.320 7.920 0.288 0.312 0.100（BSC） L 3.000 3.600 0.118 0.142

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TC24C32_64-A0--page11

TC24C64是腾芯微专门研发的两线EEPROM存储芯片

TC24C64A

SOP8 PACKAGE OUTLINE DIMENSIONS

Symbol

Dimensions In Millimeters

Dimensions In Inches

0.050 θ

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TC24C32_64-A0--page12

TC24C64是腾芯微专门研发的两线EEPROM存储芯片