单片机外文翻译--STC89C52处理芯片

外文资料翻译

STC89C52 processing chip

Prime features:

With MCS - 51 SCM product compatibility, 8K bytes in the system

programmable Flash memory, 1000 times CaXie cycle, the static operation: 0Hz ~ 33Hz, triple encryption program memory, 32 programmed I/O port, three 16 timer/counter, the eight uninterrupted dual-career UART serial passage, low power consumption, leisure and fall after fall electric power mode can be awakened and continuous watchdog timer and double-number pointer, power identifier. Efficacy: characteristics

STC89C52 is one kind of low power consumption, high CMOS8 bit

micro-controller, 8K in system programmable Flash memory. Use high-density nonvolatile storage technology, and industrial 80C51 product instruction and pin fully compatible. The Flash memory chips allows programs in the system, also suitable for programmable conventional programming. In a single chip, have clever 8 bits CPU and online system programmable Flash, increase STC89C52 for many embedded control system to provide high vigorous application and useful solutions. STC89C52 has following standard efficacy: 8k byte Flash RAM, 256 bytes, 32 I/O port, the watchdog timer, two, three pointer numerical 16 timer/counter, a 6 vector level 2 continuous structure, the serial port, working within crystals and horological circuit. In addition, 0Hz AT89S52 can drop to the static logic operation, support two software can choose power saving mode. Idle mode, the CPU to stop working, and allows the RAM, timer/counters, serial, continuous to work. Protection asana pattern, RAM content is survival, vibrators frozen, SCM, until all the work under a continuous or hardware reset. 8-bit microcontrollers 8K bytes in the system programmable Flash AT89S52 devices.

Mouth: P0 P0 mouth is a two-way open drain I/O. As export, each can

drive eight TTL logic level. For P0 port to write \foot as the high impedance input.

When access to external programs and numerical memory, also known

as low P0 mouth eight address/numerical reuse. In this mode, with the internal P0 resistor.

In the flash when programming, also used for P0 mouth; absorb

instruction bytes In the process, the output command byte calibration. When the program requires external, calibration on pull-up resistors.

Mouth: P1 mouth P1 is an internal resistance of the eight two-way I/O

buffers can drive, P1 output four TTL logic level. To write \P1 port, the internal resistance to port, can push as input mouth. When used as input, external and internal foot because of low resistance, will output current (IIL).

In addition, P1.0 and P1.2 respectively timer/counter 2 external

counting input (P1.0 / T2) and when the trigger editor/counter P1.1 input (2), specific T2EX/are shown below. In programming and calibration, flash P1 mouth absorb eight address low byte. Efficacy: the foot.

P1.0 T2 (timer/counter T2 external counting input), clock output P1.1 T2EX (timer/counter T2 capture/overloaded triggered signals and

direction control),

P1.5 MOSI (with) online system programming, P1.6 MISO (with) online system programming, P1.7 SCK (with) online system programming,

Mouth: P2 P2 mouth is an internal resistance of the eight two-way I/O

buffers and P2 output can drive four TTL logic level. To write \internal resistance to port, can push as input mouth. When used as input, external and internal foot because of low resistance, will output current (IIL).

In the external program memory access or use 16bit external numerical

memory address read (for example MOVX execution DPTR @), P2 mouth send out high 8 address. In this application, P2 mouth on the internal use

strong pull send 1. In using 8-bit address (such as MOVX @ RI) access to external numerical memory, P2 mouth output P2 latches content. In programming and calibration, flash P2 mouth also absorb high eight address byte and some control signal.

P3: a P3 mouth on the inside of the eight two-way pull-up resistors

I/O buffers can drive, p2 output four TTL logic level. For P3 port to write \the internal resistance to port, can push as input mouth. When used as input, external and internal foot because of low resistance, will output current (IIL). P3 mouth AT89S52 special functions (also as the second efficacy), are shown below. In programming and calibration, flash also absorb some P3 mouth control signals.

Port pin second efficacy:

P3.0 RXD (serial input) P3.1 TXD (serial export), P3.2 INTO the discontinuous (0) P3.3 INT1 (1) the discontinuous P3.4 (time/counter TO 0) P3.5 T1 (1) time/counter,

P3.6 WR (external numerical memory write for) P3.7 RD (external numerical memory read for)

In addition, also absorb some used in mp3 mouth FLASH memory

programming and calibration of program control signals.

RST, reset input: when the vibrator, RST pin appeared two machine

cycle above high level will be reset the chip.

ALE/PROG - when access to external program memory or numerical

memory, ALE (address latch allow) output pulses are used to latch address of low eight bytes. Normally, ALE with clock frequencies are 1/6 output pulse signal with fixed, so it can be used for the purpose or output clocks. Timing Those who want an attention is: whenever access to external numerical memory will skip a ALE pulse.

For FLASH memory programming, this pin is used for input

programming pulse (.) PROG

If necessary, but through special effect to the zone registers (SFR) 8EH

D0 position, the unit can be banned ALE operations. This position is a bit, MOVX and MOVC instructions will be activated. ALE -- In addition, the foot will be weak, execute external program MCU hign should be banned, a void. Set ALE

PSEN - program storage PSEN allowed (output is outside of the

program memory read, choose communication by external program memory when taking AT89C52 instructions (or), each machine cycle PSEN twice, two pulse output is useful, during this period, when access to external numerical memory, will skip PSEN twice.

EA/VPP - external access permission, to make the CPU only access to

external program memory (address for 0000H - FFFFH), EA end must remain low level (ground). Should notice is: if a LB1 is encrypted, reset when programming will latch EA end.

As for the high level of the EA (VCCS), the CPU is the

implementation of the program memory internal instructions.

FLASH memory when programming, this pin plus + 12 v

programming allow power Vpp, of course, that is the part is used to Vpp voltage 12V programming.

中文翻译

STC89C52处理芯片 首要性能：

与MCS-51单片机产物兼容 、8K字节在系统可编程Flash存储器、 1000次擦写周期、全静态操作：0Hz～33Hz 、三级加密程序存储器、 32个可编程I/O口线 、三个16位定时器/计数器 八个间断源、全双职工UART串行通道、 低功耗空闲和掉电模式 、掉电后间断可唤醒 、看门狗定时器 、双数值指针 、掉电标识符。 功效特性描述：

STC89C52 是一种低功耗、高性能CMOS8位微控制器，具有 8K 在系统可编程Flash 存储器。使用高密度非易失性存储器技术制造，与工业80C51 产物指令和引脚完全兼容。片上Flash允许程序存储器在系统可编程，亦适于常规编程器。在单芯片上，拥有灵巧的8 位CPU 和在线系统可编程Flash，使患上STC89C52为众多嵌入式控制应用系统提供高矫捷、超有用的解决方案。 STC89C52具有以下标准功效： 8k字节Flash，256字节RAM， 32 位I/O 口线，看门狗定时器，2 个数值指针，三个16 位 定时器/计数器，一个6向量2级间断结构，全双职工串行口， 片内晶振及钟表电路。另外，AT89S52 可降至0Hz静态逻辑操作，支持2种软件可选择节电模式。空闲模式下，CPU 停止工作，允许RAM、定时器/计数器、串口、间断继续工作。掉电保护体式格局下，RAM内容被生存，振动器被冻结，单片机一切工作停止，直到下一个间断或者硬件复位为止。8 位微控制器 8K字节在系统可编程 Flash AT89S52

P0 口：P0口是一个8位漏极开路的双向I/O口。作为输出口，每位能驱动8个TTL逻辑电平。对于P0端口写“1”时，引脚用作高阻抗输入。 当访问外部程序和数值存储器时，P0口也被作为低8位地址/数值复

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