外文文献及翻译：基于STC89C52单片机的多路抢答器设计

2010 International Conference on Intelligent Computation Technology and Automation Design and Implement of Responder Based on Freescale HCS12 Single Chip

Microcomputer

Cheng Qiming, Cheng Yinman, Wang Mingmei, Chang Lin

College of Electric Power and Automation

Shanghai University of Electric Power

Changyang 2588 road, Yandpu district, Shanghai 200090, China

E-mail :chengqiming@a88fc3931711cc7930b71686

Abstract—An 8-channel responder based on Freescale HCS12

single chip microcomputer is designed. The responder can

display the number of the first player correctly. It also can count

the scores and show the player with the highest score. The

system includes four modules: CPU12, the SCI serial

communication, digital display tube and timer. When

competition signal input, it is been caught and then cause

interruption, the timer is used to time accurately, the serial port

is used to send and receive the start answer signal, judgment

signal and other signals, the digital display tube is used to show

the scores of the current player . LCD display tube shows

subjects and answers. So the basic functions of the responder are

achieved.

Keywords--responder; single chip microcomputer; timer; input

capture; interruption

I.I NTRODUCTION

Responder is also known as the first signal discriminator,

which is widely used in various competitions. It can judge the

number of the first player accurately, fairly and intuitively.

Currently, a variety of quiz responder has emerged on the

market, in which a small responder is commonly designed with

small-scale digital integrated circuit. Although the technology

has been quite mature, but it is simple function, low

intelligence, high fault, simple display, less flexibility, not

convenience for upgrade, it has been unable to meet all kinds

of requirements for intellectual competitions and variety

shows. Therefore, it is necessary to develop some kinds of

responder which are more suitable for applications.

In recent years, with the rapid development of science and

technology, the applications of single-chip microcomputer are

becoming widely, which promotes the development of

traditional measurement and control technology. In this paper,

Freescale HCS12 [1-3] is designed as a core component to

achieve an intelligent digital responder with 8-channel [4-8], it

has some breakthroughs on technology, function and other

aspects, comparing with the past responder. It is characterized

by simple structure, powerful, good reliability, practicability,

so that the competition can really carried out on just, fair and

open rules.

II.F UNCTION OF RESPONDER

The basic functions of responder designed in this paper are:

(1)The system can limit the competition time and answer

time of the alarm;

1 This work is supported by Leading Academic Discipline Project of

Shanghai Municipal Education Commission (Project Number: J510301，

J510303)

978-0-7695-4077-1/10 $26.00 ? 2010 IEEE DOI 10.1109/ICICTA.2010.128 1127

(2)The system can identify the answer signal and identify

the player’s number;

(3)The system can calculate score for each player and

display the scores.

Responder can accommodate 8 players numbered 1 to 8. In addition, LED digital tubes are designed to display the latched data. After race host clears the system, if participants press switch, and after answer is certificated whether it is correct or not, the number of first player to answer in action is immediately shown by digital tubes. Responder should have a strong ability to distinguish players to answer in the action, its resolution reaches at least a few ms.

III.I DEAS OF RESPONDER DESIGN

After the requirements and functions of responder are analyzed, the following circuits are required in general:

A Responder circuit

The circuit has two functions: one is to identify the number of the player who press button, and to save the number; the other is to prohibit the other players from buttoning or to make other buttons not available.

B Timing circuits

Host can set competition time and answer time by the time pre-set-circuit. If nobody can answer question within the set time, all players will not get score, then the host will announce the answer. Besides, if someone gets the chance to answer the question, but does not give the right result before the allowable time, he or she won’t get the score, the overtime signal will be also send, the host will declare the right answer. Freescale HCS12 contains timer module, the timer module can be directly used.

C Overtime circuit

HCS12 will send overtime signal when time goes beyond the set time, this signal will be transferred to the PC computer by the serial port. The next question will be proceeded to answer.

D Scores count and display circuit.

When host presses the answer key, it is time to start to answer, if one player presses the answer key, his or her number will be recorded, his or her score will be counted and displayed on the LED digital tubes.

Bedside the circuits designed above, some necessary logic designs are also necessary. The logic designs are as following:

First, the host will read the question which will show in the LCD; next, the PC computer will send letter “k”, which means that play is beginning to competition. At the same time, timing circuit starts to work, if nobody gets the chance to answer the question within permitted time, microcontroller will send the word “chao shi” to PC computer; If someone presses the competition key within the specified time, microcontroller will send his or her number. If the time goes beyond the permitted time, PC computer will send “next” which means turning to the next question, the next question will be automatically showed to answer. If some player gets the chance to answer the question, his or her number and scores will decrease 1 automatically and show in the digital tubes, then microcontroller sends “next” to go on the next question. If the score is few than 0 after decreasing, player is eliminated. The right answer will show on the LCD. Finally, if all the questions are done, microcontroller will send “e” to end the game, then the scores of all players will be computed, the highest one will be shown on the digital tubes.

IV. D ESIGN OF RESPONDER HARDWARE

Responder hardware is firstly designed; Responder hardware is taken directly from the hardware resources of Freescale HCS12 development board developed by Suzhou University. The development board takes MC9S12DG128 as the core, using modular design approach, it extracts part of I/O resources, and it also provides each module with a corresponding interface circuit. It also provides A/D input channels, PWM low-pass filter circuits, 16-key keyboard input channels, 8-bit digital I/O circuits, SPI I/O circuits, SCI communication circuits, I 2C bus I/O expansion circuits and so on.

In this paper, the hardware modules, the pin connections and the corresponding interfaces of the development board are listed and unified to redesign by actual needs of the system. Figure 1 shows the hardware structure diagram of the selected part of development board.

Figure 1. Diagram of hardware structure

A Selection of hardware modules

The responder designed in this paper is relatively simple, the I/O ports and the modules involved are not many.

(1) The system uses push-button switch as the competition key, which is generally used as a switch input, there are 0 and 1. Here, the system need know whether the button is switched by somebody, the system need not care about the switch on or off.

(2) Timer module is indispensable in timing circuit. Here, the timer module's functions are to limit time, and to capture

input signals. This will be followed some of the circuit design described in detail.

(3) LED digital tubes are used to show the participant’s number and scores in the display circuit. The system records the player's number and the corresponding score, and then transmits to the LED digital tubes through I/O ports. LCD is achieved by external connection module; it is used to display questions and answers.

(4) LED small light is used to show whether somebody presses the competition button. If player answer, the small light will be bright, otherwise, it will not light.

(5) SCI module is necessary in serial communication port. Since the signal that starts to answer needs to be send by PC computer, if there is no serial communication port, the whole system will be paralyzed. The function of SCI module is that receives the signal to HCS12, and then sends the player’s number to PC.

B Design of hardware circuits

1)

Competition circuit design

Competition circuit captures competition signals by means of input capturing; there will be a interruption once the push- button switch jumps. 8 push-button switches are connected with 8 channels, so the system can know which player competes to answer the question by reading corresponding channel. In this paper, the 8 channels connect with input capture channels PT0~ PT7 of HCS12. 2) Timing circuit

As the HCS12 has its own timing module, timing circuit don’t need to be designed, and internal timing module of HCS12 can be directly used.

3) Overtime reminding circuit

Small light or buzzer could connect with any I/O port, but the system should ensure the selected I/O ports have not conflict with the I/O ports occupied by the module. Once the specified time is over, I / O port send a high level, and the LED small light is on. In this paper, the first pin of PA port is chosen as the alarm signal port; this pin is connected to the testing of small light.

4) Electronic counter and display circuit

The scoring scores can be resolved by programming, but the displaying scores needs hardware connection, LED digital tubes and LCD are connected with corresponding I/O ports of HCS12, external LCD module should have the function of displaying Chinese characters. 5) Communication connect

The development board has a 9-pin cable of RS232 serial port; it can be connected with PC computer by the cable.

V.

D ESIGN OF RESPONDER SOFTWARE

A Design of software subprogram

1) SCI subprogram

(1) SCI initialization function

SCI initialization is to set corresponding register, mainly to set serial port baud rate, here baud rate is set to 9600 bps, the baud rate is:

B t = f BUS / (16 * B R ) (1)

where, B R is set by SCI baud rate register, and it is a 16-bit register, is assigned twice, first set the low 8 bits, and then set

the higher 5 bits, the first three of high 8 bits are meaningless;

f BUS is the bus frequency.

The next is to set control registers (SCICR1 and SCICR2), here SCI serial port be allowed to run, and the normal code, 8- bit, no parity data is output. The D6 bit of the SCICR1 (SCISWAI) is a SCI allowing bit, SCI module is prohibited at SCISWAI=1, SCI module is allowed when SCISWAI=0; D4 bit (M bit) is a choice bit of pattern/character length, it is used to define the sending/receiving data format, 9-bit data transfer is allowed at M=1, 8-bit data transfer is allowed at M= 0; D1 bit (PE) is the parity enabling bit, PE=1 allows parity, PE = 0 does not allow parity. SCICR2 needs also to be set in order to receive and send data, the D3 bit of SCICR2 (TE) is a transmitter allowing bit, TE=1 allows to send, TE=0 prohibits to send; D2 bit is receiver allowing bit, RE=1 allows to receive, RE=0 prohibits to receive.

(2)SCI sending function

Firstly, 1 bit sending function of serial port should be programmed. At the beginning, SCI status register 1 (SCISR1) needs to be judged, its D7 bit (TDRE) sends the empty flag of data register at TDRE=1, which means that the data to send has already moved into the sending shift register, if the data register is empty, the new data that is written into the data register can be sent. More bits data sending function calls repeatedly 1 bit sending functions until the sending is over.

(3)SCI receiving function

Similarly, 1 bit receiving function of serial port is programmed. Here, SCI status register 1 (SCISR1) is judged, its D5 bit (RDRF) represents the full flag of the receiving data register. RDRF=1 means that the receiver is full, the received data can be read from the SCI data register, then, the data needs to be read out from data register (SCIDR). The receiving data is one more step than the sending data, which it is to determine whether any data has been received. If the receiving process is failed, FFH data will be returned. More bits data receiving function call repeatedly 1 bit receiving function, and the system will report the receiving error as long as there is 1 bit receiving failure.

2)Timer subprogram

(1)Timer initialization

When timer is initialized, timer is prohibited to work until timer is used. The D7 bit (TEN) of timer control register 1(TSCR1) is an enabling bit of timer, timer is enabled at TEN=1, and timer is disabled at TEN=0. The following step is to allow the timer interrupt and to prohibit the timer reset. The D7 bit (TOI) and the D3 bit (TCRE) of timer control register 2 (TSCR2) are respectively the enabling bit of timer overflow interrupt and the reset enabling bit of timer counter, timer interrupt is allowed at TOI=1, otherwise, timer interrupt is not allowed at TOI=0. When OC7 is successfully compared, the counter can be reset at TCRE=1, it can’t be reset at TCRE=0; D2 ~ D0 bits (PR2 ~ PR0) of TSCR2 are the selection bits of frequency factor, they are used to set the division factor of bus clock frequency, frequency division factor p can be 1,2,4,8,16, 32, 64 or 128. The overflow time of timer can be described as following:

t=np/f BUS (2) where, n is the count value of counter; f BUS is the bus clock frequency; p is the frequency division factor. In this paper, n = 216 = 65536, p is chosen to be 2, t≈0.03s, t is much closed to 1/38s, 38 interruptions is about 1s.

(2)Input capturing initialization

First, the option is to capture input or to compare output. The select register of input capturing/output comparing (TIOS) is used to do this work, the Dx bit (IOSx) of the register is the select bit of x channel, the x channel is set as the output comparing channel at IOSx = 1, and it is set as the input capturing channel at IOSx = 0. In our design, because 8 players take pert in the competition, 8 channels should all be set as input capturing channels, namely TIOS = 0x00.

After input capturing is set, the interruption also needs to be open, which it should be done after the competition is allowed.

3)Subprogram of LED digital tubes

(1)Initialization of LED digital tubes

LED digital tubes are used to dynamic display, its initialization is the I/O port initialization, the direction registers of corresponding I/O ports (the pins of 8-bit data port are connected with 7-segment digits and decimal point of digital tubes; the pins of 4-bit bit choice are connected with 4 digital tubes) are set to be output, that is, data port is 0xFF, bit choice port is 0xF0.

(2)Display of LED digital tubes

The basic idea of LED digital tubes display is that the display codes of all the numbers and the chip select code of the displaying bits are stored into the corresponding registers, when display functions are called, the parameter numbers of functions can match with the numbers and the bits in the tables of number display code and chip select code

4)LCD display

(1)LCD initialization

The module is enabled and the lattice size is defined as 8*8 or 8*10, the display format is defined as 1 row or 2 rows, the display of Chinese characters is used.

(2)Subprogram of LCD display

The emphasis of the program is the display of Chinese characters. Chinese characters are identified by two ASCII codes. The ASCII codes of Chinese characters to be displayed are recorded into data registers.

B Design of interrupt service subprogram

1)Subprogram of overflow interruption

The frequency division factor has been set in the program of timer initialization, 38 interruptions is about 1s, so the counter variable needs to be set, it adds 1 automatically after each interruption, it calls the second accumulating function after 38 interruptions. It needs to be noted that the interruption flag register 2 (TFLG2) is set to 0 after each overflow interruption. Otherwise, the system is always identified as overflow interrupt. D7 bit of the register is TOF bit, when the 16-bit running counter changes from $FFFF to $0000, the overflow interrupt occurs, this bit is set to 1, this bit can be cleared by writing 0 to it, other 7 bits are invalid. The flow of overflow interrupt is shown in Figure 2.

2)Subprogram of input capturing interruption

The main task of input capturing interruption program is to judge whether player competes to answer and to record the player’s number. The interrupt flag bit needs to be set, it is set to 1 when an interrupt happens, which means that someone

competes to answer, and then the person number will be read. Interrupt flag register 1 (TFLG1) of main timer is used to read the interrupt channel. Its Dx bit (CxF) is the interrupt flag of input capturing / output comparing channel x, when an input capturing / output comparing event happen, the corresponding bit is set to 1, the channel number of corresponding interrupting can read from TFLG1 register and it is also the number of competition player. To note that, the flag register needs to be cleared after the flag register is read. The flag register can be cleared when the appropriate channel is set to 1. The flow of input capturing interrupt is shown in Figure 3.

VI. C ONCLUSIONS

Responder is one of the essential devices in various knowledge and intellectual contests, the development of better and more intelligent digital responder is very significant. Responder designed in this paper can achieve a responder's basic functions through experimental prototype testing.

It reaches the design target with reasonable design, simple structure, good commonality, strong function, reliable answer and quick reaction. However, as hardware limitations of development board, some functions have not been able to achieve, such as the development board does not have enough LED digital tubes to display all player’s scores simultaneously, the host can not adjust answer time according the difficulty of the question and so on. These issues will remain to be addressed in future development.

Figure 2. Flow of overflow

Figure 3. Flow of input capturing interrupt

interrupt

C The main program design

Before the start of the main program, the total interruptions are turned off and each module is initialized. The initialization of each module has been done in the corresponding initialization subprogram of each module. Here we only need call the corresponding initialization subprogram. After the initialization of each module is completed, the total interruptions should be turned on. The main body of the main program is a loop structure; there are also several sub-cycles in the main loop, which are used for the cycle waiting of each loop. The flow of the main program is shown in Figure 4. After the completion of the initialization, the system has been waited for the signal of competition start with the circular mode until the signal comes. When this signal is received, the system checks whether the cycle time is overtime, if it is overtime, the system changes to the next question, otherwise, the system checks the competition signal, if some player competes to answer, then the system checks whether the answer time is out, if the time is not out, the system judges whether the result is true, if the result is right, the player is added 1 point, otherwise, the player is subtracted 1 point, and the system enters the next question. To the player whose score will be subtracted, the system needs to check whether the score is low than 0, if it does, this player’s input channel is turned off. To be noted that, if the competition flag is 1, it should be cleared.

Figure 4. Flow of the main program

R EFERENCES

[1] Steven F B, Daniel J P. Embedded systems –using the HCS12

microcontroller design and application [M]. NewYork: Publishing House of Electronics Industry, America, 2006.

[2] Wang Yihuai, Liu Xiao. Embedded systems –the design and application

of HCS12 micro controller [M]. Beijing: Beijing University of Aeronautics and Astronautics Press, 2008.

[3] Wang Wei. Principle and applications of HCS12 microcontrollers [M].

Beijing: Beijing University of Aeronautics and Astronautics Press, 2007.

[4] Zhang Ruixi. Design of quiz responder [J]. Mechanical and Electrical

Engineering and Technology, 2007, vol.36, no.8, pp.51-52.

[5] Li Ming, Tan Andrew, Zhu Shunli. 8-way intelligent responder based

on the LPC932 single chip microcontroller [J]. Ordnance Automation, 2007, vol.26, no.7, pp.70-71.

[6] Chou Kungming, Zhou Chenchen. Design of 9-way multi-functional

quiz responder based on the single chip microcontroller AT89C2051 [J]. Modern electronic technology, 2006, vol.25, no.20, pp.4-6.

[7] Wang Gongtang, Yang Shanying. 16-way responder based on the

PIC16F873 [J]. Computer Development & Applications, 2006, vol.19 , no.9, pp.9-13.

[8] Gong Changlay. Design of intelligent responder controlled by single

chip microcomputer [J]. Guangdong Automation and Information Engineering, 2003, no.3, pp.28-30.

基于飞思卡尔HCS12单片机设计和实施的抢答器

程启明，程尹曼，汪明媚，常林

上海电力学院电力与自动化工程学院,上海,200090

摘要——基于飞思卡尔HCS12单片机的八通道抢答器设计。抢答器可以正确

的显示首位成功抢答选手的号码。它还可以计算分数，并显示得分最高的选手。该系统包括四个模块：CPU12、SCI串行通信、数字显示管和计时器。抢答信号输入

时将被锁定，然后引起中断、定时器准确的工作。串行端口用于开始应答信号的发送和接收，区分不同信号。数码管用于显示当前选手的分数，液晶显示管用于显示科目和答案。所以抢答器的基本功能得以实现。

关键词：抢答器；单片机；定时器；输入锁定；中断

一、导言

抢答器也被称为第一信号鉴别器，它广泛的用于各种比赛。它可以准确、公正、直观的判断首位成功抢答选手的号码。目前，市场上出现了各种小规模数字集成电路设计的抢答器，虽然该技术已经相当成熟，但是设计的抢答器功能简单，不智能，故障率高，显示简单，缺乏灵活性，改进又不方便。它已经无法满足各种知识竞赛和各种节目的需求。因此，有必要制造出一些更适合应用的抢答器。

近年来，随着科学技术的迅猛发展，单片机的应用越来越广泛，这促进了传统测量和控制技术的飞速发展。在本文中，飞思卡尔的HCS12[1-3]单片机作为设计一个八通道[4-8]智能抢答器的核心部件，与过去的抢答器相比，它在技术、功能和其他方面都有了较大突破。它的特点是结构简单，功能强大，可靠性好，实用性强，这样的竞争才能真正公正、公平、公开的进行。

二、抢答器功能

本文设计的抢答器基本功能是：

（1）该系统可以调整比赛时间和答题倒计时提示时间;

（2）该系统能识别抢答信号并确定选手的号码;

（3）该系统可以计算出每位选手的得分并显示出来。

抢答器可以提供8名选手使用编号为1至8。此外，LED数码管显示锁存数据。在主持人清除系统后，如果参与者按下抢答开关，并且无论答案正确与否，第一个抢答者的号码将立即由数码管显示。抢答器应该有很强的能力来区分选手抢答的先后顺序，其分辨率至少达到几毫秒。

三、抢答器设计的思路

对抢答器的要求和功能进行分析后，一般需要以下电路：

A响应电路

该电路有两个功能：一个是识别抢答时该选手的号码并将其保存; 另一个是在抢答成功时系统将禁止其他选手抢答。

B时序电路

主持人可以通过预先的电路来设置比赛时间和答题时间。如果在设定的时间内没有人回答问题，那么所有的选手将不会得分，然后主持人将公布答案。此外，如果有人获得回答这个问题的机会，但在规定的时间内给出的答案不正确，他也不能得分，若超过了时间也不得分，主持人将宣布正确的答案。飞思卡尔HCS12单片机包含定时器模块，并且可以直接使用。

C超时电路

若超出了设定的时间HCS12将发出超时信号，并把这个信号传送到PC计算机的串行端口，接下来将进行下一轮抢答。

D分数计算和显示电路

当主持人按下开始键就开始抢答，如果选手最先按下抢答键，他或她的号码将被记录下来，他或她的得分将被计算并用LED数码管显示出来。此外，一些逻辑设计也是必要的。逻辑设计如下：

首先，主持人将读取液晶屏上显示的问题，接下来，PC电脑将发送字母“K”，这标志着比赛开始。同时，定时电路开始工作，如果在允许的时间内没有得到回答问题的机会，微控制器将给PC机发送“超时”，如果有人在指定的时间内按下抢答键，微控制器将发送他或她的号码。如果超出允许的时间，PC电脑将发送“下一步”，这意味着转向下一个问题，接下来该问题将自动显示回答。如果一些选手得到机会而回答错误，他或她的分数将减1并显示在数码管上，然后单片机发送“下

一步”，进行下一个问题。如果得分在减少后小于0，该选手将被淘汰。正确的答案将显示在液晶屏上。最后，如果所有的问题都抢答完了，微控制器将发送“e”来结束游戏，然后计算所有选手的得分，并将得分最高的选手号码显示在数码管上。

四、响应硬件设计

抢答器的硬件要优先设计。抢答器的硬件资源直接由苏州大学开发的飞思卡尔HCS12开发板代替。开发板以MC9S12DG128为核心部件，采用模块化设计方法，它提取了I / O资源的一部分，也提供了每个模块相应的接口电路，它还提供了A / D输入通道，PWM低通滤波电路，16键的键盘输入通道，8位数字I / O电路，SPI的I / O电路，SCI通信电路，I2C总线I / O扩展电路等等。在这篇论文中，列出了硬件模块、引脚连接、相应的开发板接口及重新设计系统的实际需求。图1显示了开发板选定部分的硬件结构图。

图1 硬件结构图

A 硬件模块的选择

本文设计的抢答器是比较简单的，涉及的I/ O端口和模块并不多。

（1）本系统采用按钮开关作为抢答的关键，0和1通常被用来作为开关的输入，在这里，系统需要知道是否有人按了按钮，而不需要关心开关打开或关闭。（2）定时器模块是必不可少的时序电路。在这里，定时器模块的功能是限制时间，和捕捉输入信号。之后，将详细介绍部分电路设计。

（3）LED数码管显示电路用于显示参赛者的人数和分数。该系统记录选手的号码和相应的得分，然后通过I / O端口传输到LED数码管。液晶屏是通过外部连接模块来显示问题和答案的。

（4）LED小灯用来显示是否有人按下按钮抢答。如果选手回答，小灯将是亮的，

否则，它不会亮。

（5）SCI是必要的模块串行通信端口。由PC电脑发送开始回答的信号，如果没有串行通信端口，整个系统就会瘫痪。SCI模块的功能是接收HCS12的信号，然后把选手号码传送到PC。

B 设计的硬件电路

1）比赛的电路设计

巡回赛比赛信号捕捉输入方式，会有一个按键开关跳一次中断。8个按键开关连接8个通道，通过读取相应的通道，这样系统就可以知道哪个选手来回答这个问题，在本文中，8通道输入捕捉通道和HCS12的PT0?PT7相连接。

2）定时电路

HCS12都有自己的定时模块，定时电路并不需要进行设计，可以直接使用HCS12的内部定时模块。

3）超时提醒电路

小灯或蜂鸣器，可以连接任何I / O端口，但该系统应确保选定的I / O端口模块所占用的I / O端口没有冲突。一旦在规定时间结束后，I / O端口发送一个信号给LED小灯上。在本文中PA口是选择报警信号端口，这个引脚连接到小灯进行测试。

4）电子计数器和显示电路

选手得分可以通过编程来解决，但显示成绩，需要硬件LED数码管和液晶连接相应的HCS12系列I / O端口，外部液晶显示模块应具有汉字显示功能。

5）通讯连接

开发板有9针RS232串口电缆，它可以与PC电脑连接电缆。

五、响应软件设计

1）SCI初始化函数

SIC的初始化设置相应的寄存器，主要是设置串口波特率，波特率为9600 bps，波特率是：B T = F BUS/（16 *B R）

（1）B R是被SCI波特率设置速率寄存器，它是16寄存器，被分配两次，第一次设置低8位，然后设置高5位，高8位前三是没有意义的; 接下来就是设置控制

寄存器，这里SCI串行端口允许运行（SCICR1和SCICR2），正常的代码为8位，无奇偶校验数据输出。SCI模块的SCICR1第6点位（SCISWAI）是SCI允许位，SCI模块被禁止在SCISWAI= 1，当SCISWAI=0时被允许; D4位（M位）的模式可以选择位/字符长度，它被用来定义发送/接收9位数据传输的数据格式，在M=1时被允许，在M=0时允许8位数据传输; D1位（PE）是校验允许位，体育= 1允许校验，体育= 0不容许校验。SCICR2还需要进行设置以便接收和发送数据，D3位SCICR2（TE）是一个发射器允许位，TE= 1允许发送，TE =0禁止发送; D2位是接收允许位，RE= 1，允许接收，RE= 0禁止接收。

（2）SCI发送1位串口进行功能编程。在开始的时候，SCI状态寄存器1（SCISR1）需要来进行判断，其D7位（TDRE的）发送的TDRE=1，这意味着，已经移动到发送移位寄存器的数据，它是发送数据寄存器空标志，如果数据寄存器是空的，到数据寄存器中写入新的数据时可以发送。对于更多位数据它将调用发送函数反复发送，直到TDRE=1。

（3）SCI接收1位串口进行功能编程。在这，判断SCI状态寄存器（SCISR1）是否为1，D5位（RDRF位）代表接收数据寄存器满标志。RDRF位=1表示接收器是完整的，可以从SCI数据寄存器读取接收到的数据，那么，它需要读取数据寄存器（SCIDR）。接收的数据比发送数据多一个步骤，它是确定是否已收到任何数据的关键。如果接收过程失败（即FFH）数据将被退回。如有更多比特的数据，只要有1位接受失败，系统将会收到错误报告。

2）定时器子程序

（1）当定时器初始化时，定时器将禁止工作，直到定时器启用。D7位定时器控制寄存器（TSCR1）为1时，启用定时器，在TOI= 1时，定时器被禁止。下面的步骤是关于允许定时器中断和禁止定时器复位。D7位（TOI）定时器和D3位定时器均控制寄存器，分别能使定时器溢出中断、使定时器计数器复位，定时器中断被允许时TOI= 1，否则，定时器中断是不允许（TOI= 0）。D2?D0（PR2?PR0）是TSCR2寄存器的频率因子选择位，他们是用来设置总线时钟频率的分频系数，分频系数P可以1,2,4,8,16，32，64或128。定时器溢出时间可以描述如下：

T = NP / F BUS（2）

其中，n是计数器的计数值; F BUS是总线时钟频率， P是分频因子。在本文中，

N = 216 = 65536，p选择为2，T≈0.03S，T是非常封闭，1/38s，38中断约1秒。（2）首先输入捕捉初始化，该选项是捕捉输入或输出。选择寄存器的输入/输出捕捉作比较，（TIOS）是用来做这项工作的，当IOSX= 1 时，DX位寄存器（IOSX）中x通道选择位设置为输出比较通道，在IOSX= 0时，它被设置为输入捕获通道。在我们的设计中，因为8名选手参加比赛，8个通道都设置为输入捕获通道，即TIOS= 0X00。设置输入捕捉后，中断也必须是开放的，完成后允许竞争。3）LED数码管的子程序

（1）初始化LED数码管动态显示，即其I / O口初始化，方向寄存器相应的I / O端口（8位数据端口引脚是连接7段数码管的数字和小数点，4位选择引脚与4位数码管连接）设置为输出，也就是说，数据端口是0xFF，位选择的端口是0xF0。（2）LED数码管显示的基本思路是，所有的数字和芯片选择显示代码存储到相应的寄存器，被称为显示功能，功能参数可以配合数字、显示代码和芯片的表位来选择代码

4）液晶显示器

（1）液晶初始化模块能和晶格尺寸为8*8或8*10（被定义为1行或2行显示格式）一起显示中文字。

（2）液晶显示子程序方案的重点是中文字的显示，中文通过两个ASCII码字符识别，把显示中文字符的ASCII码记录到的数据寄存器。

B设计的中断服务子程序

1）溢出中断子程序

38中断已在定时器初始化程序设置的分频因子，约1秒，因此需要设置计数器变量，它增加了每个自动中断，它调用的第二个积累功能也经过38中断。需要注意的中断标志寄存器（TFLG2）设置后，每次溢出中断时为0。否则，系统总是被认定为溢出中断。寄存器的D7位是TOF位，当16位计数器从$ FFFF到$ 0000运行变化，发生溢出中断，该位被设置为1，这一点可以通过写0来清除，其他7位都是无效的。溢出中断流程如图2所示。

2）子程序的输入捕捉

中断程序的主要任务是判断选手竞争抢答和记录选手的号码。需要设置中断标志位，它被设置为1时，中断发生，这意味着，有人完成回答，然后将读入选手号码。主定时器中断标志寄存器（TFLG1）是用来读取中断通道。其DX位（CXF）的输入捕捉/输出比较通道x，输入捕捉/输出比较事件发生时，相应的中断标志位设置为1，可以读取相应的中断通道号TFLG1寄存器，它也记录竞争选手的号码。需要注意的是，标志寄存器读取后需要清除。适当的通道设置为1时，可以清除标志寄存器。输入捕捉中断流程如图3所示。

图2 溢出图3 输入捕捉中断

主程序开始之前，总中断被关闭，每个模块子程序的初始化已相应完成。在这，我们只需要调用相应的初始化子程序。每个模块的初始化完成后，应打开总中断。主程序的主体是一个循环结构，也有几个子周期在主循环中，以等待每个循环周期。主程序流程如图4所示。初始化完成后，该系统已等待循环模式信号到来。当此信号被接收时，系统会检查周期时间是否超时，如果超时，系统将变化为下一个问题，否则，系统将检查信号正误，如果结果是正确的，选手加1分，否则，选手被扣除1分，系统进入下一个问题。选手的得分将被减去，该系统需要检查得分是否低于

0，如果是，这位选手的输入通道将被关闭。必须指出，如果竞争的标志是1时，它应该被清除。

图4 主程序流程

六、结论

抢答器是各种知识和智力竞赛中重要的设备之一，制造更好和更智能化的数字抢答器是非常重要的。在本文设计的抢答器可以实现其基本功能，通过实验测试，它设计合理，结构简单，通用性好，功能强大，抢答可靠以及快速反应出设计目标。然而，由于开发板的硬件限制，一些功能都没有能够实现，如开发板没有足够的LED数码管来显示所有选手的得分，同时主机不能根据问题的难度来调整答题时间等等。这些问题将在以后的发展中有待解决。

REFERENCES

[1] Steven F B, Daniel J P. Embedded systems–using the HCS12 microcontroller design

and application [M]. NewYork: Publishing House of Electronics Industry, America, 2006.

[2] Wang Yihuai, Liu Xiao. Embedded systems–the design and application of HCS12

micro controller [M]. Beijing: Beijing University of Aeronautics and Astronautics

Press, 2008.

[3] Wang Wei. Principle and applications of HCS12 microcontrollers [M].Beijing:

Beijing University of Aeronautics and Astronautics Press, 2007.

[4] Zhang Ruixi. Design of quiz responder [J]. Mechanical and Electrical Engineering

and Technology, 2007, vol.36, no.8, pp.51-52.

[5] Li Ming, Tan Andrew, Zhu Shunli. 8-way intelligent responder based on the LPC932

single chip microcontroller [J]. Ordnance Automation, 2007, vol.26, no.7, pp.70-71.

[6] Chou Kungming, Zhou Chenchen. Design of 9-way multi-functional quiz responder

based on t he single chip microcontroller AT89C2051 [J]. Modern electronic technology, 2006, vol.25, no.20, pp.4-6.

[7] Wang Gongtang, Yang Shanying. 16-way responder based on the PIC16F873 [J].

Computer Development & Applications, 2006, vol.19 , no.9, pp.9-13.

[8] Gong Changlay.Designofintelligent responder controlled by single chip

microcomputer [J].Guangdong Automation and Information Engineering, 2003, no.3, pp.28-30.1130.

本文来源：https://www.bwwdw.com/article/51de.html