Quartus_II设计说明英文版

Designing with Quartus IIJoe Yue(乐红才 乐红才) 乐红才 133******** joeyue@c3f4693987c24028915fc370Copyright ? 2005 Altera Corporation

ObjectivesCreate a New Quartus II Project Compile a Design into an FPGA Assign Design Constraints (Timing & Pin) Perform Timing Analysis & Obtain Results Create Simulation Waveform & Simulate a Design Configure an FPGA
Copyright ? 2005 Altera Corporation 2

Class AgendaProjects Design Methodology in Quartus? II Compilation Timing Analysis & Assignments Simulation Programming/Configuration
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Software & Development ToolsQuartus II? All Stratix, Cyclone & Hardcopy Devices ? APEX II, APEX 20K/E/C, Excalibur, & Mercury Devices ? FLEX 10K/A/E, ACEX 1K, FLEX 6000 Devices ? MAX II, MAX 7000S/AE/B, MAX 3000A Devices ? Free Version ? Not All Features & Devices IncludedSee c3f4693987c24028915fc370 for Feature Comparison
Quartus II Web Edition
MAX+PLUS? IICopyright ? 2005 Altera Corporation 4
? All FLEX, ACEX, & MAX Devices

Designing with Quartus IIQuartus II Development System Feature OverviewCopyright ? 2005 Altera Corporation

Quartus II Development SystemFully-Integrated Design Tool? Multiple Design Entry Methods ? Logic Synthesis ? Place & Route ? Simulation ? Timing Analysis ? Device Programming
Copyright ? 2005 Altera Corporation

Quartus II Operating Environment
Project Navigator
Status Window
Message Window
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Designing with Quartus IIDesign MethodologyCopyright ? 2005 Altera Corporation

Typical PLD Design FlowDesign Specification
Design Entry/RTL Coding- Behavioral or Structural Description of Design
RTL Simulation- Functional Simulation (Modelsim?, Quartus II) - Verify Logic Model & Data Flow (No Timing Delays)
LEM4K
M512
Synthesis- Translate Design into Device Specific Primitives - Optimization to Meet Required Area & Performance Constraints - Precision Synthesis, Synplify/Synplify Pro, Design Compiler FPGA, Quartus II
I/O
Place & Route- Map Primitives to Specific Locations inside Target Technology with Reference to Area & Performance Constraints - Specify Routing Resources to Be UsedCopyright ? 2005 Altera Corporation 9

Typical PLD Design Flowtclk
Timing Analysis- Verify Performance Specifications Were Met - Static Timing Analysis
Gate Level Simulation- Timing Simulation - Verify Design Will Work in Target Technology
PC Board Simulation & Test- Simulate Board Design - Program & Test Device on Board - Use SignalTap II for DebuggingCopyright ? 2005 Altera Corporation 10

Designing with Quartus IIQuartus II ProjectsCopyright ? 2005 Altera Corporation

New Project WizardFile Menu
Select Working Directory Name of Project Can Be Any Name; Recommend Using Top-Level File Name Top-level Entity Does Not Need to Be the Same Name as TopLevel File Name Create a New Project Based on an Existing Project & Settings
Copyright ? 2005 Altera Corporation 12

Add FilesAdd Design Files? ? ? ? ? Graphic (.BDF, .GDF) AHDL VHDL Verilog EDIF
Notes: ? Files in project directory do not need to be added ? Add top level file if filename & entity name are not the same
Add User Library Pathnames? User Libraries ? MegaCore?/AMPPSM Libraries ? Pre-Compiled VHDL Packages
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Device SelectionChoose Device Family
Choose Specific Part Number from List or Let Quartus II Choose Smallest Fastest Device Based on Filter Criteria
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EDA Tool SettingsChoose EDA Tools Add or Change Settings Later
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Done!
Review Results & Click on Finish
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MAX+PLUS II to Quartus IIConvert MAX+PLUS II Projects into Quartus II Projects Assignments Automatically Translated
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Project ManagementProject Archive & Restore? Creates Compressed Archive File (.QAR) ? Creates Archive Activity Log (.QARLOG) ? Copies & Save Duplicate of Project in New DirectoryProject File (QPF) Design Files Settings FilesCopy Project
Archive Project
Project Copy
Copyright ? 2005 Altera Corporation 18

Projects Entry SummaryProjects Necessary for Design Processing Use Project Wizard to Create New Projects Use Project Navigator to Study File & Entity Relationships within Project
Copyright ? 2005 Altera Corporation 19

Designing with Quartus IIDesign EntryCopyright ? 2005 Altera Corporation

Design Entry MethodsQuartus IIAHDL VHDL Verilog
? Text Editor
TopLevel File
Top-level design files can be schematic, HDL or 3rdParty Netlist File
? Schematic Editor ? Memory EditorHEX MIF Block Diagram File Graphic Design File
.bdf .gdf Block File
.bsf
.tdf
.vhd
.v
.edf .edif Text File
.v, vlg, .vhd, .vhdl, vqm Text File
Symbol File
Text File
Text File
Text File
Generated within Quartus II
Imported from 3rd-Party EDA tools
3rd-Party EDA Tools? EDIF ? HDL ? VQM
Mixing & Matching Design Files AllowedCopyright ? 2005 Altera Corporation 21

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