点阵程序

16*16点阵汉字显示程序

本程序汉字字体是使用横行显示，实验者课根据实际需要组合不同的字体和方向。更改的时候注意实体名更改和例华语句的使用。 模块1 se10

library ieee;

use ieee.std_logic_1164.all; entity sel0 is

port(clk:in std_logic;

a,b,c,d,e,f:in std_logic_vector(15 downto 0); sel0:out std_logic_vector(3 downto 0); dd:out std_logic_vector(15 downto 0)); end;

architecture one of sel0 is signal cq:integer range 0 to 15; signal q:integer range 0 to 599; signal c0: std_logic; begin

process(clk) begin

if clk'event and clk='1' then if cq<15 then cq<=cq+1; c0<='0'; else cq<=0; c0<='1'; end if; end if; end process; process(cq) begin

case cq is

when 0=>sel0<=\ when 1=>sel0<=\ when 2=>sel0<=\ when 3=>sel0<=\ when 4=>sel0<=\ when 5=>sel0<=\ when 6=>sel0<=\ when 7=>sel0<=\ when 8=>sel0<=\ when 9=>sel0<=\ when 10=>sel0<=\

when 11=>sel0<=\when 12=>sel0<=\when 13=>sel0<=\when 14=>sel0<=\when 15=>sel0<=\when others=>null; end case; end process; process(c0) begin

if c0'event and c0='1' then if q<599 then q<=q+1; else q<=0; end if; end if; end process; process(q) begin case q is when when when when

0 to 99 =>dd<=a; 100 to 199 =>dd<=b; 200 to 299 =>dd<=c; 300 to 399 =>dd<=d;

when 400 to 499 =>dd<=e; when 500 to 599 =>dd<=f; when others=>null; end case; end process; end one;

模块2 汉字 ‘王’

library ieee;

use ieee.std_logic_1164.all; entity wang is

port(clk:in std_logic;

d:out std_logic_vector(15 downto 0)); end;

architecture one of wang is signal cq:integer range 0 to 15; begin

process(clk)

begin

if clk'event and clk='1' then if cq<15 then cq<=cq+1; else cq<=0; end if; end if; end process; process(cq) begin

case cq is

when 0=>d<=\ when 1=>d<=\ when 2=>d<=\ when 3=>d<=\ when 4=>d<=\ when 5=>d<=\ when 6=>d<=\ when 7=>d<=\ when 8=>d<=\ when 9=>d<=\ when 10=>d<=\when 11=>d<=\when 12=>d<=\when 13=>d<=\when 14=>d<=\when 15=>d<=\when others=>null; end case; end process; end one;

模块3 汉字‘志’ library ieee;

use ieee.std_logic_1164.all; entity zhi is port(clk:in std_logic;

d:out std_logic_vector(15 downto 0)); end;

architecture one of zhi is

signal cq:integer range 0 to 15;

begin

process(clk) begin

if clk'event and clk='1' then if cq<15 then cq<=cq+1; else cq<=0; end if; end if; end process; process(cq) begin case cq is

when 0=>d<=\ when 1=>d<=\ when 2=>d<=\ when 3=>d<=\ when 4=>d<=\ when 5=>d<=\ when 6=>d<=\ when 7=>d<=\ when 8=>d<=\ when 9=>d<=\ when 10=>d<=\when 11=>d<=\when 12=>d<=\when 13=>d<=\when 14=>d<=\when 15=>d<=\when others=>null; end case; end process; end one;

模块4 汉字‘起’ library ieee;

use ieee.std_logic_1164.all; entity qi is

port(clk:in std_logic;

d:out std_logic_vector(15 downto 0)); end;

architecture one of qi is

signal cq:integer range 0 to 15;

begin

process(clk) begin

if clk'event and clk='1' then if cq<15 then cq<=cq+1; else cq<=0; end if; end if; end process; process(cq) begin case cq is

when 0=>d<=\ when 1=>d<=\ when 2=>d<=\ when 3=>d<=\ when 4=>d<=\ when 5=>d<=\ when 6=>d<=\ when 7=>d<=\ when 8=>d<=\ when 9=>d<=\ when 10=>d<=\when 11=>d<=\when 12=>d<=\when 13=>d<=\when 14=>d<=\when 15=>d<=\when others=>null; end case; end process; end one;

完全程序 library ieee;

use ieee.std_logic_1164.all; entity wangzhiqi is

port(clk:in std_logic;

sel:out std_logic_vector(3 downto 0); d:out std_logic_vector(15 downto 0));

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