数字电路课程设计《梁祝》乐曲 数字时钟 乒乓球游戏机 串并乘法

数字电路课程设计

题目1：《梁祝》乐曲 题目2：数字时钟 题目3：乒乓球游戏机 题目4：串并乘法器

课程名称： 数字电路课程设计 学 院： 专 业： 班 级： 学 号： 学生姓名：

成 绩：

2010 年 月 日

（一）《梁祝》乐曲演奏

一：系统功能概述

① 演奏电路逻辑图有三部分：音乐节拍和音调发生器、简谱码对应的分频预置

数查表电路、数控分频与演奏发生器。

② 乐曲的每个音符的发音频率值及其持续的时间是乐曲能够连续演奏所需的两个基本要素，设计演奏电路的关键就是获得这两个要素所对应的数值以及通过纯硬件的手段来利用这些数值实现所希望乐曲的演奏效果。 二、系统组成以及系统各部分的设计

顶层设计(SONGER.VHD)

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY Songer IS PORT ( CLK12MHZ : IN STD_LOGIC; CLK8HZ : IN STD_LOGIC;

LED8 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); SPKOUT : OUT STD_LOGIC ); END;

ARCHITECTURE one OF Songer IS

SIGNAL QI : STD_LOGIC_VECTOR(5 DOWNTO 0); COMPONENT NoteTabs

PORT ( clk : IN STD_LOGIC;

ToneIndex : OUT INTEGER RANGE 0 TO 15 ); END COMPONENT; COMPONENT ToneTaba

PORT ( Index : IN INTEGER RANGE 0 TO 15;

Tone : OUT INTEGER RANGE 0 TO 16#7FF# ); END COMPONENT; COMPONENT Speakera

PORT ( clk : IN STD_LOGIC;

Tone : IN INTEGER RANGE 0 TO 16#7FF#; SpkS : OUT STD_LOGIC ); END COMPONENT;

SIGNAL Tone : INTEGER RANGE 0 TO 16#7FF#; SIGNAL ToneIndex : INTEGER RANGE 0 TO 15; BEGIN

u1 : NoteTabs PORT MAP (clk=>CLK8HZ, ToneIndex=>ToneIndex); u2 : ToneTaba PORT MAP (Index=>ToneIndex, Tone=>Tone);

u3 : Speakera PORT MAP(clk=>CLK12MHZ,Tone=>Tone, SpkS=>SPKOUT );

PROCESS(CLK8HZ) BEGIN

IF CLK8HZ'EVENT AND CLK8HZ = '1' THEN QI <= QI + 1; END IF; END PROCESS;

LED8(3 DOWNTO 0) <= QI(5 DOWNTO 2); LED8(7 DOWNTO 4) <= QI(5 DOWNTO 2); LED8(11 DOWNTO 8) <= QI(5 DOWNTO 2); LED8(15 DOWNTO 12) <= QI(5 DOWNTO 2); LED8(19 DOWNTO 16) <= QI(5 DOWNTO 2); LED8(23 DOWNTO 20) <= QI(5 DOWNTO 2); LED8(27 DOWNTO 24) <= QI(5 DOWNTO 2); LED8(31 DOWNTO 28) <= QI(5 DOWNTO 2); END;

音乐节拍和音调发生器(NOTETABS.VHD)

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY NoteTabs IS

PORT ( clk : IN STD_LOGIC;

ToneIndex : OUT INTEGER RANGE 0 TO 15 ); END;

ARCHITECTURE one OF NoteTabs IS

SIGNAL Counter : INTEGER RANGE 0 TO 138; BEGIN

CNT8 : PROCESS(clk) BEGIN

IF Counter = 138 THEN Counter <= 0; ELSIF (clk'EVENT AND clk = '1') THEN Counter <= Counter + 1; END IF; END PROCESS;

Search : PROCESS(Counter) BEGIN

CASE Counter IS -- 译码器，查歌曲的简谱，查表结果为音调表的索引值 WHEN 00 => ToneIndex <= 3; -- 简谱\音 WHEN 01 => ToneIndex <= 3; -- 发4个时钟节拍 WHEN 02 => ToneIndex <= 3; WHEN 03 => ToneIndex <= 3;

WHEN 04 => ToneIndex <= 5; -- 简谱\音 WHEN 05 => ToneIndex <= 5; -- 发3个时钟节拍 WHEN 06 => ToneIndex <= 5;

WHEN 07 => ToneIndex <= 6; -- 简谱\音

WHEN 08 => ToneIndex <= 8; WHEN 09 => ToneIndex <= 8; WHEN 10 => ToneIndex <= 8; WHEN 11 => ToneIndex <= 9; WHEN 12 => ToneIndex <= 6; WHEN 13 => ToneIndex <= 8; WHEN 14 => ToneIndex <= 5; WHEN 15 => ToneIndex <= 5; WHEN 16 => ToneIndex <= 12; WHEN 17 => ToneIndex <= 12; WHEN 18 => ToneIndex <= 12; WHEN 19 => ToneIndex <= 15; WHEN 20 => ToneIndex <= 13; WHEN 21 => ToneIndex <= 12; WHEN 22 => ToneIndex <= 10; WHEN 23 => ToneIndex <= 12; WHEN 24 => ToneIndex <= 9; WHEN 25 => ToneIndex <= 9; WHEN 26 => ToneIndex <= 9; WHEN 27 => ToneIndex <= 9; WHEN 28 => ToneIndex <= 9; WHEN 29 => ToneIndex <= 9; WHEN 30 => ToneIndex <= 9; WHEN 31 => ToneIndex <= 0; WHEN 32 => ToneIndex <= 9; WHEN 33 => ToneIndex <= 9; WHEN 34 => ToneIndex <= 9; WHEN 35 => ToneIndex <= 10; WHEN 36 => ToneIndex <= 7; WHEN 37 => ToneIndex <= 7; WHEN 38 => ToneIndex <= 6; WHEN 39 => ToneIndex <= 6; WHEN 40 => ToneIndex <= 5; WHEN 41 => ToneIndex <= 5; WHEN 42 => ToneIndex <= 5; WHEN 43 => ToneIndex <= 6; WHEN 44 => ToneIndex <= 8; WHEN 45 => ToneIndex <= 8; WHEN 46 => ToneIndex <= 9; WHEN 47 => ToneIndex <= 9; WHEN 48 => ToneIndex <= 3; WHEN 49 => ToneIndex <= 3; WHEN 50 => ToneIndex <= 8; WHEN 51 => ToneIndex <= 8;

WHEN 52 => ToneIndex <= 6; WHEN 53 => ToneIndex <= 5; WHEN 54 => ToneIndex <= 6; WHEN 55 => ToneIndex <= 8; WHEN 56 => ToneIndex <= 5; WHEN 57 => ToneIndex <= 5; WHEN 58 => ToneIndex <= 5; WHEN 59 => ToneIndex <= 5; WHEN 60 => ToneIndex <= 5; WHEN 61 => ToneIndex <= 5; WHEN 62 => ToneIndex <= 5; WHEN 63 => ToneIndex <= 5; WHEN 64 => ToneIndex <= 10; WHEN 65 => ToneIndex <= 10; WHEN 66 => ToneIndex <= 10; WHEN 67 => ToneIndex <= 12; WHEN 68 => ToneIndex <= 7; WHEN 69 => ToneIndex <= 7; WHEN 70 => ToneIndex <= 9; WHEN 71 => ToneIndex <= 9; WHEN 72 => ToneIndex <= 6; WHEN 73 => ToneIndex <= 8; WHEN 74 => ToneIndex <= 5; WHEN 75 => ToneIndex <= 5; WHEN 76 => ToneIndex <= 5; WHEN 77 => ToneIndex <= 5; WHEN 78 => ToneIndex <= 5; WHEN 79 => ToneIndex <= 5; WHEN 80 => ToneIndex <= 3; WHEN 81 => ToneIndex <= 5; WHEN 82 => ToneIndex <= 3; WHEN 83 => ToneIndex <= 3; WHEN 84 => ToneIndex <= 5; WHEN 85 => ToneIndex <= 6; WHEN 86 => ToneIndex <= 7; WHEN 87 => ToneIndex <= 9; WHEN 88 => ToneIndex <= 6; WHEN 89 => ToneIndex <= 6; WHEN 90 => ToneIndex <= 6; WHEN 91 => ToneIndex <= 6; WHEN 92 => ToneIndex <= 6; WHEN 93 => ToneIndex <= 6; WHEN 94 => ToneIndex <= 5; WHEN 95 => ToneIndex <= 6;

WHEN 96 => ToneIndex <= 8; WHEN 97 => ToneIndex <= 8; WHEN 98 => ToneIndex <= 8; WHEN 99 => ToneIndex <= 9; WHEN 100 => ToneIndex <= 12; WHEN 101 => ToneIndex <= 12; WHEN 102 => ToneIndex <= 12; WHEN 103 => ToneIndex <= 10; WHEN 104 => ToneIndex <= 9; WHEN 105 => ToneIndex <= 9; WHEN 106 => ToneIndex <= 10; WHEN 107 => ToneIndex <= 9; WHEN 108 => ToneIndex <= 8; WHEN 109 => ToneIndex <= 8; WHEN 110 => ToneIndex <= 6; WHEN 111 => ToneIndex <= 5; WHEN 112 => ToneIndex <= 3; WHEN 113 => ToneIndex <= 3; WHEN 114 => ToneIndex <= 3; WHEN 115 => ToneIndex <= 3; WHEN 116 => ToneIndex <= 8; WHEN 117 => ToneIndex <= 8; WHEN 118 => ToneIndex <= 8; WHEN 119 => ToneIndex <= 8; WHEN 120 => ToneIndex <= 6; WHEN 121 => ToneIndex <= 8; WHEN 122 => ToneIndex <= 6; WHEN 123 => ToneIndex <= 5; WHEN 124 => ToneIndex <= 3; WHEN 125 => ToneIndex <= 5; WHEN 126 => ToneIndex <= 6; WHEN 127 => ToneIndex <= 8; WHEN 128 => ToneIndex <= 5; WHEN 129 => ToneIndex <= 5; WHEN 130 => ToneIndex <= 5; WHEN 131 => ToneIndex <= 5; WHEN 132 => ToneIndex <= 5; WHEN 133 => ToneIndex <= 5; WHEN 134 => ToneIndex <= 5; WHEN 135 => ToneIndex <= 5;

WHEN 136 => ToneIndex <= 0; WHEN 137 => ToneIndex <= 0; WHEN 138 => ToneIndex <= 0; WHEN OTHERS => NULL;

-- 简谱休止符à输出-- 频率为零 END CASE; END PROCESS; END;

简谱码对应的分频预置数查表电路（ToneTaba.VHD）

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_unsigned.ALL; ENTITY ToneTaba IS

PORT ( Index : IN INTEGER RANGE 0 TO 15; CODE : OUT INTEGER RANGE 0 TO 15; HIGH : OUT STD_LOGIC;

Tone : OUT INTEGER RANGE 0 TO 16#7FF# ); END;

ARCHITECTURE one OF ToneTaba IS BEGIN

Search : PROCESS(Index) BEGIN

CASE Index IS -- 译码电路，查表方式，控制音调的预置数 WHEN 0 => Tone <= 2047; CODE<=0; HIGH<='0'; WHEN 1 => Tone <= 773; CODE<=1; HIGH<='0'; WHEN 2 => Tone <= 912; CODE<=2; HIGH<='0'; WHEN 3 => Tone <= 1036; CODE<=3; HIGH<='0'; WHEN 5 => Tone <= 1197; CODE<=5; HIGH<='0'; WHEN 6 => Tone <= 1290; CODE<=6; HIGH<='0'; WHEN 7 => Tone <= 1372; CODE<=7; HIGH<='0'; WHEN 8 => Tone <= 1410; CODE<=1; HIGH<='1'; WHEN 9 => Tone <= 1480; CODE<=2; HIGH<='1'; WHEN 10 => Tone <= 1542; CODE<=3; HIGH<='1'; WHEN 12 => Tone <= 1622; CODE<=5; HIGH<='1'; WHEN 13 => Tone <= 1668; CODE<=6; HIGH<='1'; WHEN 15 => Tone <= 1728; CODE<=7; HIGH<='1'; WHEN OTHERS => NULL; END CASE; END PROCESS; END;

数控分频与演奏发生器（Speakera.VHD） LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY Speakera IS

PORT ( clk : IN STD_LOGIC;

Tone : IN INTEGER RANGE 0 TO 16#7FF#; SpkS : OUT STD_LOGIC ); END;

ARCHITECTURE one OF Speakera IS SIGNAL PreCLK : STD_LOGIC; SIGNAL FullSpkS : STD_LOGIC; BEGIN

DivideCLK : PROCESS(clk)

VARIABLE Count4 : INTEGER RANGE 0 TO 15; BEGIN

PreCLK <= '0';

-- 将CLK进行16分频，PreCLK为CLK的16分频 IF Count4 > 11 THEN PreCLK <= '1'; Count4 := 0;

ELSIF clk'EVENT AND clk = '1' THEN Count4 := Count4 + 1; END IF; END PROCESS;

GenSpkS : PROCESS(PreCLK, Tone)

VARIABLE Count11 : INTEGER RANGE 0 TO 16#7FF#; BEGIN

-- 11位可预置计数器

IF PreCLK'EVENT AND PreCLK = '1' THEN IF Count11 = 16#7FF# THEN Count11 := Tone;

FullSpkS <= '1'; ELSE

Count11 := Count11 + 1; FullSpkS <= '0'; END IF; END IF; END PROCESS;

DelaySpkS : PROCESS(FullSpkS) VARIABLE Count2 : STD_LOGIC; BEGIN

-- 将输出再进行2分频，将脉冲展宽，以使扬声器有足够功率发音 IF FullSpkS'EVENT AND FullSpkS = '1' THEN Count2 := NOT Count2;

IF Count2 = '1' THEN SpkS <= '1'; ELSE

SpkS <= '0'; END IF; END IF; END PROCESS; END;

三：系统以及各个模块的仿真波形

音乐节拍和音调发生器的仿真波形

简谱码对应的分频预置数查表电路仿真波形

音乐节拍和音调发生器仿真波形

数控分频与演奏发生器仿真波形

四：系统调试运行结果说明与分析

实验箱选择模式0。将设计出的演奏电路的程序经过编译（Compiler）后，选择FLEX10K系列中EPF10K10LC84-4作为目标器件（Assign/Device），并进行管脚锁定（Floorplan Editor）。器件编程(Programmer)，将编译生成的*.sof文件下载到目标芯片。实验箱自带蜂鸣器（Speaker）奏出“梁祝”的旋律，由此说明实验成功。

五：结论及体会

程序可以完成预定的功能，而且本系统还可以演奏出其他的曲子，只需将其简谱分频预置数写入ToneTaba.VHD，再将该曲子的节拍表输入到NoteTabs.VHD中，重新编译后，下载即可完成。通过这次实验，使我更加熟练的掌握了调制编译的过程，加深了对实验的兴趣。

（二）数字钟

一：系统功能概述

① 一个具有“时”、“分”、“秒”十进制数字显示（小时从00-23）计时器。 ② 具有手动校时、校分的功能。

二:系统组成以及系统各部分的设计

顶层文件(SHUZIZHONG.VHD)

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity shuzizhong is

port(clk,set,change,s1,s2,s3:in std_logic;

second1,second2,minite1,minite2,hour1,hour2:out std_logic_vector(3 downto 0); cout:out std_logic); end entity;

architecture one of shuzizhong is begin

pro1:process(clk,set,s1,s2,s3,change) variable

msecond1,msecond2,mminite1,mminite2,mhour11,mhour12,mhour21,mhour22:std_logic_vector(3 downto 0); begin

if clk'event and clk='1' then

if set='1' then -----启动校验 if s1='1'

then msecond1:=msecond1+1; if msecond1=\

then msecond1:=\

msecond2:=msecond2+1; if msecond2=\ then msecond2:=\ end if; end if;

end if; --------秒校验 if s2='1' then

mminite1:=mminite1+1;

if mminite1=\

then mminite1:=\

mminite2:=mminite2+1; if mminite2=\

then mminite2:=\ end if; end if;

end if; ---------分校验 if s3='1' then

mhour11:=mhour11+1; mhour21:=mhour21+1;

if mhour11=\ mhour12:=mhour12+1;

end if;

if mhour11=\and mhour12=\

then mhour11:=\

end if;

if mhour21=\ mhour22:=mhour22+1;

end if;

if mhour21=\mhour22=\

then mhour21:=\

end if;

end if;-------时校验

else msecond1:=msecond1+1;-----正常计时工作 if msecond1=\

then msecond1:=\

msecond2:=msecond2+1; if msecond2=\

then msecond2:=\

mminite1:=mminite1+1; if mminite1=\

then mminite1:=\

mminite2:=mminite2+1; if mminite2=\

then mminite2:=\ mhour11:=mhour11+1; mhour21:=mhour21+1;

if mhour11=\ mhour12:=mhour12+1;

end if;

if mhour11=\and mhour12=\

then mhour11:=\

end if;-------12小时制 if mhour21=\ mhour22:=mhour22+1;

end if;

if mhour21=\mhour22=\

then mhour21:=\

end if;----------24小时制

end if; end if; end if; end if;

if (msecond1=\and (msecond2=\and (mminite1=\and (mminite2=\

then cout<='1'; else cout<='0'; end if; end if; end if;

second1<=msecond1; second2<=msecond2; minite1<=mminite1; minite2<=mminite2;

if change='0' then hour1<=mhour11;hour2<=mhour12;

else hour1<=mhour21;hour2<=mhour22;------12/24小时制转换 end if;

end process;

end architecture one;

三:系统以及各个模块的仿真波形

顶层文件仿真波形

四、系统调试运行结果说明与分析

实验箱选择模式6。CLK接入1HZ的信号，数字钟开始计数，按下SET键进行时，分，秒的校准（分别按下S1,S2,S3进行校准），按下CHANGE键进行12/24小时制的切换，数码显示1，2，3，4，5，6分别显示秒，分和小时。

五：结论与体会

通过调试，该系统能够完成预期的目标，并且计时较为准确，各部分功能完

成的也很好。这是继第一次实验后的又一成功，尽管程序还不是自己编写的，但是使我们看到了数电实验丰富的内容和独特的魅力。

（三）乒乓游戏机

一：系统功能概述

① 两人乒乓球游戏能够模拟乒乓球比赛的基本过程和规则，并能自动裁判计分，在游戏中，以一排发光管交替发光知识乒乓球的行进路径，其行进速度可有输入的时钟信号clk控制。 ② Catcher是乒乓球街球控制模块，即发光管亮到最后一个的瞬间，若检测到对应的表示球拍的键的信号，立即将“球”反向运行：如果没有检测到该键信号，将给出出错音，同时为对方加分，并将计分现实出来。 ③ Cout4和cout10分被是失球计数器的高低位计数模块。Direction是乒乓球行进方向控制模块，主要由发球键控制。Sound是失球提示发声模块。

二：系统组成以及系统各部分的设计

总控制模块(BALLCTRL.VHD)

library ieee;

use ieee.std_logic_1164.all; entity ballctrl is

port(clr:in std_logic;

——系统复位

bain:in std_logic; bbin:in std_logic; serclka:in std_logic; serclkb:in std_logic;

clk:in std_logic; bdout:out std_logic; serve:out std_logic; serclk:out std_logic; ballclr:out std_logic; ballen:out std_logic); end entity ballctrl;

architecture behave of ballctrl is signal bd:std_logic; signal ser:std_logic; begin

bd<=bain or bbin;

ser<=serclka or serclkb; serclk<=ser; bdout<=bd; process(clr,clk,bd) begin

if(clr='1')then serve<='1'; ballclr<='1'; Else if(bd='1')then ballclr<='1'; if(ser='1')then ballen<='1'; serve<='0'; else

ballen<='0'; serve<='1'; end if; else

ballclr<='0'; end if; end if;

end process;

end architecture behave;

——左球拍 ——右球拍 ——左球拍准确接球或发球 ——右球拍准确接球或发球 ——乒乓球灯移动时钟 ——球拍接球脉冲 ——发球状态信号 ——球拍准确接球信号 ——乒乓球灯清零信号 ——乒乓球灯使能

——球拍准确接球信号 ——球拍接球脉冲

——系统复位

——系统处在发球状态 ——乒乓球灯清零 ——系统正常 ——球拍发球或接球时 ——乒乓球灯清零

——球拍发球或准确接球 ——乒乓球灯使能允许 ——系统处在接球状态

——乒乓球等被禁止 ——系统处在发球状态

——没有发球或接球时乒乓灯不清零

乒乓球灯模块(BALLPATH.VHD)

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity ballpath is

port(clk:in std_logic; ——乒乓球灯前进时钟 clr:in std_logic; ——乒乓球灯清零 way:in std_logic; ——乒乓球灯前进方向 en:in std_logic; ——乒乓球灯使能

ballout:out std_logic_vector(7 downto 0)); ——乒乓球灯用来观察乒乓球的路线 end entity ballpath;

architecture behave of ballpath is

signal lamp:std_logic_vector(9 downto 0); begin

process(clk,clr,en) begin

if(clr='1')then ——清零 lamp<=\ elsif en='0'then

elsif(clk'event and clk='1')then ——使能允许，乒乓球灯前进 if(way='1')then ——乒乓球灯右移 lamp(9 downto 1)<=lamp(8 downto 0); lamp(0)<='0'; Else ——乒乓球灯左移 lamp(8 downto 0)<=lamp(9 downto 1); lamp(9)<='0'; end if; end if;

ballout<=lamp(8 downto 1); end process;

end architecture behave;

乒乓球拍模块(CATCHER.VHD)

library ieee;

use ieee.std_logic_1164.all; entity catcher is

port(ball:in std_logic; net:in std_logic; serclk复位

bclk:in std_logic; serve:in std_logic; couclk:out std_logic; serclk:out std_logic); end entity catcher;

architecture behave of catcher is begin

——接球点，即乒乓球灯的末端

——乒乓球灯的中点，乒乓球过中点时，couclr，

——球拍接球信号 ——发球信号

——正确接球信号，接到球时为1

process(bclk,net) begin

if(net='1')then serclk<='0'; couclk<='0';

elsif(bclk'event and bclk='1')then if(serve='1')then serclk<='1'; Else if(ball='1')then serclk<='1'; Else serclk<='0'; couclk<='1'; end if; end if; end if; end process;

end architecture behave;

——乒乓球过中点时，couclr，serclk复位

——球拍接球时 ——系统处于发球状态时 ——发球成功 ——系统处于接球状态 ——乒乓球恰好落在接球点上 ——接球成功

——乒乓球没落在接球点上 ——接球失败

乒乓球前进方向产生模块(MWAY.VHD)

library ieee;

use ieee.std_logic_1164.all; entity mway is

port(servea:in std_logic; serveb:in std_logic; way:out std_logic); end entity mway;

architecture behave of mway is begin

process(servea,serveb) begin

if(servea='1')then way<='1'; elsif(serveb='1')then way<='0'; end if; end process;

end architecture behave;

——左选手发球信号 ——右选手发球信号

——乒乓球灯前进方向信号

——左选手发球 ——方向向右 ——右选手发球 ——方向向左

失球提示(SOUND.VHD)

library ieee;

use ieee.std_logic_1164.all; entity sound is

port(clk:in std_logic; sig:in std_logic; en:in std_logic; sout:out std_logic); end entity sound;

architecture behave of sound is begin

sout<=clk and(not sig)and en end architecture behave;

——发声时钟 ——正确接球信号 ——球拍接球脉冲 ——提示声输出，接小喇叭

——球拍接球，没接到时，发出提示音

十进制计数器用作失败低位计数(COUT10.VHD)

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cout10 is

port(clk,clr:in std_logic; cout:out std_logic;

qout:out std_logic_vector(3 downto 0)); end entity cout10;

architecture behave of cout10 is

signal qqout:std_logic_vector(3 downto 0); begin

process(clr,clk) begin

if(clr='1')then

qqout<=\ cout<='0';

elsif(clk'event and clk='1')then if(qqout>\ qqout<=\ cout<='1'; else

qqout<=qqout+'1'; cout<='0'; end if; end if;

qout<=qqout; end process;

end architecture behave;

四进制计数器用作失败球高位计数(COUT4.VHD)

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;

entity cout4 is

port(clk,clr:in std_logic; cout:out std_logic;

qout:out std_logic_vector(3 downto 0)); end cout4;

architecture behave of cout4 is

signal qqout:std_logic_vector(3 downto 0); begin

process(clr,clk) begin

if(clr='1')then qqout<=\cout<='0';

elsif(clk'event and clk='1')then if(qqout>\qqout<=\cout<='1'; else

qqout<=qqout+'1'; cout<='0'; end if; end if;

qout<=qqout; end process; end behave;

乒乓球游戏顶层文件(PINGPANG.VHD)

library ieee;

use ieee.std_logic_1164.all; entity pingpang is

port(bain,bbin,clr,clk,souclk:in std_logic;

ballout:out std_logic_vector(7 downto 0);

countah,countal:out std_logic_vector(3 downto 0); countbh,countbl:out std_logic_vector(3 downto 0); lamp,speaker:out std_logic); end entity pingpang;

architecture behave of pingpang is component sound

port(clk,sig,en:in std_logic; sout:out std_logic); end component; component ballctrl

port(clr,bain,bbin,serclka,serclkb,clk:in std_logic; bdout,serve,serclk,ballclr,ballen:out std_logic);

end component; component ballpath

port(clk,clr,way,en:in std_logic;

ballout:out std_logic_vector(7 downto 0)); end component; component catcher

port(ball,net,bclk,serve:in std_logic; couclk,serclk:out std_logic); end component; component cout10

port(clk,clr:in std_logic; cout:out std_logic;

qout:out std_logic_vector(3 downto 0)); end component; component cout4

port(clk,clr:in std_logic; cout:out std_logic;

qout:out std_logic_vector(3 downto 0)); end component; component mway

port(servea,serveb:in std_logic; way:out std_logic); end component; signal net,couclkah,

couclkal,couclkbh,

couclkbl,cah,cbh:std_logic; signal serve,serclka,serclkb, serclk,ballclr,bdout, way,ballen:std_logic;

signal bbll:std_logic_vector(7 downto 0); begin

net<=bbll(4); ballout<=bbll; lamp<=clk;

uah:cout4 port map(couclkah,clr,cah,countah); ual:cout10 port map(couclkal,clr,couclkah,countal); ubh:cout4 port map(couclkbh,clr,cbh,countbh); ubl:cout10 port map(couclkbl,clr,couclkbh,countbl);

ubda:catcher port map(bbll(0),net,bain,serve,couclkal,serclka); ubdb:catcher port map(bbll(7),net,bbin,serve,couclkbl,serclkb); ucpu:ballctrl

port map(clr,bain,bbin,serclka,serclkb,clk,bdout,serve,serclk,ballclr,ballen); uway:mway port map(serclka,serclkb,way);

uball:ballpath port map(clk,ballclr,way,ballen,bbll);

usound:sound port map(souclk,ballen,bdout,speaker); end architecture behave;

三：系统以及各个模块的仿真波形

乒乓球前进方向产生模块仿真波形

失球提示模块仿真波形

乒乓球游戏顶层文件仿真波形

四、系统调试运行结果说明与分析

实验箱选择模式5。CLK接入信号，一排发光管交替发光知识乒乓球的行进路径，当发光管亮到最后一个的瞬间，若检测到对应的表示球拍的键的信号，立即将“球”反向运行：如果没有检测到该键信号，将给出出错音，同时为对方加分，并将计分显示出来。

五：结论与体会

在实际的操作中，由于各种因素，游戏时并不十分的流畅，但程序可以实现

预期的功能。实验还是成功的，当然没有老师的帮助做起来还是很有难度的。

（四）通用串并乘法器

一：系统功能概述

① 串并乘法器，即指输入既有串行数据，也有并行数据。通常，串行数据作为被乘数，并行数据作为乘数，乘积串行输出。

② 串并乘法器的结构非常有规律，由与门、D触发器和全加器构成。

二：系统组成以及系统各部分的设计

顶层文件（multiplier.vhd） library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use work.mypackage.all;

entity multiplier is generic(n:integer:=8); port(

rst:in std_logic; --复位 clk:in std_logic; --时钟 a:in std_logic; --被乘数

b:in std_logic_vector(n-1 downto 0); --乘数 q:out std_logic--乘积 );

end multiplier;

architecture structural of multiplier is

signal and_out:std_logic_vector(n-1 downto 0); signal dff_out:std_logic_vector(n-1 downto 0); begin

g1:for i in 0 to n-1 generate andx:myand2 port map (

a=>a, b=>b(i),

c=>and_out(i) );

end generate;

g2:for i in 0 to n-2 generate pipex:pipe port map (

rst=>rst, --复位

clk=>clk, --时钟

a=>and_out(i), --输入

b=>dff_out(i+1), --输入

q=>dff_out(i) --输出 );

end generate;

dffx:mydff port map (

rst=>rst, --复位

clk=>clk, --时钟

d=>and_out(n-1), --输入

q=>dff_out(n-1) --输出 );

q<=dff_out(0); end structural;

全加器模块（full_adder.vhd）

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all;

entity full_adder is port(

a:in std_logic; --被加数

b:in std_logic; --加数

cin:in std_logic; --进位输入

c:out std_logic; --和

cout:out std_logic--进位输出 );

end full_adder;

architecture behave of full_adder is begin

c<=a xor b xor cin;

cout<=(a and b)or(a and cin)or(b and cin); end behave;

流水线单元（pipe.vhd）

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use work.mypackage.all;

entity pipe is port(

rst:in std_logic; --复位

clk:in std_logic; --时钟

a:in std_logic; --输入

b:in std_logic;

q:out std_logic--输出 );

end pipe;

architecture structural of pipe is signal c:std_logic; signal cin:std_logic; signal cout:std_logic; begin

u1:component full_adder port map( a=>a, b=>b, cin=>cin, c=>c,

cout=>cout );

u2:component mydff port map( rst=>rst,

clk=>clk, d=>cout, q=>cin );

u3:component mydff port map( rst=>rst, clk=>clk, d=>c, q=>q );

end structural;

描述与门的模块（myand2.vhd）

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity myand2 is port(

a:in std_logic; b:in std_logic; c:out std_logic );

end myand2;

architecture behave of myand2 is begin

c <=a and b; end behave;

D触发器（mydff.vhd）

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all;

entity mydff is port(

rst:in std_logic; clk:in std_logic; d:in std_logic; q:out std_logic );

end mydff;

architecture behave of mydff is begin

process(rst,clk) begin

if rst='1' then q<='0';

elsif rising_edge(clk)then q<=d; end if;

end process; end behave;

程序包（mypackage.vhd）

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all;

package mypackage is component myand2 is port(

a:in std_logic; b:in std_logic; c:out std_logic );

end component;

component full_adder is port(

a:in std_logic; b:in std_logic; cin:in std_logic; c:out std_logic; cout:out std_logic );

end component; component mydff is port(

rst:in std_logic; clk:in std_logic; d:in std_logic; q:out std_logic );

end component; component pipe is port(

a:in std_logic; b:in std_logic; clk:in std_logic; rst:in std_logic; q:out std_logic );

end component; end mypackage;

三：系统以及各个模块的仿真波形

顶层文件仿真波形

四：系统调试运行结果说明与分析

实验箱选择模式8 。乘数由并行输入，被乘数由串行输入。当被乘数还在串行输入时，就得到部分乘积结果是串并乘法器的一大特色，因此，特别适合用作流水线处理。

五：结论与体会

本次实验完成的是通用串并乘法器，通过调试可以完成预期功能，但是介于实验箱的范围问题有一定的局限性。经过这几次的数电实验，使我增强了对实验的兴趣以及动手能力，使理论的知识变为实际的东西…总之，我受益匪浅。

end component; component pipe is port(

a:in std_logic; b:in std_logic; clk:in std_logic; rst:in std_logic; q:out std_logic );

end component; end mypackage;

三：系统以及各个模块的仿真波形

顶层文件仿真波形

四：系统调试运行结果说明与分析

实验箱选择模式8 。乘数由并行输入，被乘数由串行输入。当被乘数还在串行输入时，就得到部分乘积结果是串并乘法器的一大特色，因此，特别适合用作流水线处理。

五：结论与体会

本次实验完成的是通用串并乘法器，通过调试可以完成预期功能，但是介于实验箱的范围问题有一定的局限性。经过这几次的数电实验，使我增强了对实验的兴趣以及动手能力，使理论的知识变为实际的东西…总之，我受益匪浅。

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